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starfire wrote: > Are there any FPGA parts available today that can contain a 32-bit, > free-running counter running at 1GHz and a 32-bit storage register to take a > snapshot of the count and read it to a slower external interface? > > The Xilinx Virtex II Pro seems to go up to about 325MHz... Short answer is no. Getting a divide by 2 close to 1GHz on a room temp typical basis is probably do-able, check with Peter A. at Xilinx ? Full margin, 32bit count and capture requires carry logic and so is going to be slower. If you really want to measure time, (or create pulse widths), then FPGAs do have resources that can go under 1ns in time resolve. -jgArticle: 71626
Hi, Duane Clark ,
Yes, thx , as you expected, in the post-synthesis file, the generic
declaration is resolved, but in the testbench file , I use the same
testbench file with behavioul simulation (with generic declaration ). so in
post-synthesis simulation, UUT is not binding. Thanks for your help.
best regards,
Jimmy
"Duane Clark" <junkmail@junkmail.com> wrote in message
news:ce0mvr0285o@news4.newsguy.com...
> Jimmy wrote:
> > Hi, all ,
> >
> > When simulating the behavioral model, it is ok, but when I simulating
the
> > post-translate vhdl model, the simulation can't generate valid results
> > (output are all uncertain state U). from the warning, it seems the
> > UnitUnderTest has not been affiliated, Could you help explain what
happens ?
> > thx,
> >
> > ** Warning: [1] top_rxfrontend_TB.vhd(143): No default binding for
component
> > 'top_rxfrontend'. (Generic 'bitwidth' is not on the entity.) -->
actaully I
> > do have this on the entity.
> >
>
> If I understand what you are saying, then the problem is that your
> testbench is setting that generic, but the generic does not exist on the
> post-translate (I assume post-synthesis?) model.
>
> That would be expected; generics are resolved at synthesis time, and do
> not appear in the post synthesis models. Take a look at the generated
file.
>
> --
> My real email is akamail.com@dclark (or something like that).
Article: 71627On Mon, 26 Jul 2004 11:19:29 +1200, Jim Granville <no.spam@designtools.co.nz> wrote: >starfire wrote: >> Are there any FPGA parts available today that can contain a 32-bit, >> free-running counter running at 1GHz and a 32-bit storage register to take a >> snapshot of the count and read it to a slower external interface? >> >> The Xilinx Virtex II Pro seems to go up to about 325MHz... I've done (tiny) Johnson counters in Virtex II Pro that would go to more than twice that speed. They could be used as a prescaler for a larger binary counter. 800MHz seems to be about the limit. Perhaps the OP should wait for Virtex 4. (What about Peter Alfke's frequency counter? Didn't he claim 1GHz in V2P?) Regards, Allan.Article: 71628
Thanks for the response. My application is for precise time correlation readings between random input pulses starting with a reset/sync pulse. The thought is if a free-running counter with 1ns resolution were reset to zero on receipt of the reset/sync pulse then a snapshot of the count made when a series of pulses are received (a separate 32-bit counter value when each pulse is received), a precise time correlation could be made from the sync to any input and from any input to any other input. The reset/sync pulse would normally be received before allowing the counter to overflow (typically about 35ms). What resources are you referring to when you say FPGAs have resources that can go under 1ns in time resolve? Dave "Jim Granville" <no.spam@designtools.co.nz> wrote in message news:SdXMc.280$zS6.50495@news02.tsnz.net... > starfire wrote: > > Are there any FPGA parts available today that can contain a 32-bit, > > free-running counter running at 1GHz and a 32-bit storage register to take a > > snapshot of the count and read it to a slower external interface? > > > > The Xilinx Virtex II Pro seems to go up to about 325MHz... > > Short answer is no. > Getting a divide by 2 close to 1GHz on a room temp typical basis is > probably do-able, check with Peter A. at Xilinx ? > > Full margin, 32bit count and capture requires carry logic and so is > going to be slower. > > If you really want to measure time, (or create pulse widths), > then FPGAs do have resources that can go under 1ns in time resolve. > > -jg >Article: 71629
"Allan Herriman" <allan.herriman.hates.spam@ctam.com.au.invalid> wrote in message news:hgt8g05ihvgi86ei0hmvdi19pj7b9a6ca0@4ax.com... > On Mon, 26 Jul 2004 11:19:29 +1200, Jim Granville > <no.spam@designtools.co.nz> wrote: > > >starfire wrote: > >> Are there any FPGA parts available today that can contain a 32-bit, > >> free-running counter running at 1GHz and a 32-bit storage register to take a > >> snapshot of the count and read it to a slower external interface? > >> > >> The Xilinx Virtex II Pro seems to go up to about 325MHz... > > I've done (tiny) Johnson counters in Virtex II Pro that would go to > more than twice that speed. They could be used as a prescaler for a > larger binary counter. > > 800MHz seems to be about the limit. Perhaps the OP should wait for > Virtex 4. A few months ago Xilinx announced that they had achieved 1 GHz performance in the lab, so it's probably a couple of years away for production devices. LeonArticle: 71630
starfire wrote:
> Thanks for the response.
>
> My application is for precise time correlation readings between random input
> pulses starting with a reset/sync pulse. The thought is if a free-running
> counter with 1ns resolution were reset to zero on receipt of the reset/sync
> pulse then a snapshot of the count made when a series of pulses are received
> (a separate 32-bit counter value when each pulse is received), a precise
> time correlation could be made from the sync to any input and from any input
> to any other input. The reset/sync pulse would normally be received before
> allowing the counter to overflow (typically about 35ms).
Sounds like a time-domain problem...
> What resources are you referring to when you say FPGAs have resources that
> can go under 1ns in time resolve?
Consider a 250MHz freq, with 4 phases in a DLL/PLL, capture of those
resolves to 1ns,but only needs to toggle at 250MHz.
Or, a long simple carry chain, with many capture registers :
An edge can capture to the delay quantize, so 200 chain of
200ps each, is 40ns. This will need alternate calibrate/measure,
as the delays are silicon derived, so are Vcc/Temp variable.
Some DLLs/DCM allow finer phase adj than 4, so 8 phase clock, and 8
copies of 125MHz counters/capture would resolve to 1ns (each IP edge).
You will need to watch aperture and metastable effects in cross-clock
domains, but the x8 copy scheme would allow you to check the integrity,
as all counters should be within 1 count of one another.
So you might read [+1][+1][+1][Whoops][+0][+0]{+0][+0]
[Whoops] is a wildly variant value, that indicates the sample edge
violated the [DeltaQt]+ [DeltaDt] aperture time.
As a general indication of the counter speeds/width, these are from
a Lattice data sheet ( not clear if these are guaranteed, or typical )
16-bit counter 360 MHz
32-bit counter 280 MHz
64-bit counter 180 MHz
-jg
Article: 71631Hi, can anybody tell me how to get the total gate count approximation from Logic Elements (LEs) in Altera Stratix and APEX device??? Thank you very much.Article: 71632
> What resources are you referring to when you say FPGAs have resources that > can go under 1ns in time resolve? well - there are still the RocketIOs ... You can easily reach 0.5 ns There was a thread in March - look atArticle: 71633
The gate count is a random number generated by marketing used to 'prove' one FPGA is better than another. Its usually based upon the number of and gates you can implement multiplied by a fudge factor. "Jasmine Hau" <hauyuanwen1980@yahoo.com> wrote in message news:fc6016ce.0407252155.6c7df59b@posting.google.com... > Hi, can anybody tell me how to get the total gate count approximation > from Logic Elements (LEs) in Altera Stratix and APEX device??? Thank > you very much.Article: 71634
Hi newsgroup people, does someone know where to find some information about an Altera Cyclone Memory Evaluation Board for DDR SDRAM ? The only board I could find is the Lancelot from www.fgpa.nl Are there other boards? Thank you for your help.Article: 71635
On Mon, 26 Jul 2004 08:47:28 +0200, Michael Schöberl <MSchoeberl@ratnet.stw.uni-erlangen.de> wrote: >> What resources are you referring to when you say FPGAs have resources that >> can go under 1ns in time resolve? > >well - there are still the RocketIOs ... You can easily reach 0.5 ns >There was a thread in March - look at >Message-ID: <BC8772E1.5C19%peter@xilinx.com> > >(with RocketIO-X you could even go further..) http://groups.google.com/groups?threadm=BC8772E1.5C19%25peter%40xilinx.com will work better for most people, as very few news servers will hold a message from March. Regards, Allan.Article: 71636
I think you don't have your software setting correctly. "Jimmy" <mljiang@eee.hku.hk> wrote in message news:<ce0jvj$hh$1@hkueee5.eee.hku.hk>... > Hi, all , > > When simulating the behavioral model, it is ok, but when I simulating the > post-translate vhdl model, the simulation can't generate valid results > (output are all uncertain state U). from the warning, it seems the > UnitUnderTest has not been affiliated, Could you help explain what happens ? > thx, > > ** Warning: [1] top_rxfrontend_TB.vhd(143): No default binding for component > 'top_rxfrontend'. (Generic 'bitwidth' is not on the entity.) --> actaully I > do have this on the entity. > > # ** Warning: (vsim-3473) Component 'uut' is not bound. > > best regards, > JimmyArticle: 71637
Have a look at the internal macrocell structure. It is different depending on the family. It basically is a Flipflop with some logic in front. The compiler converts your wishes to connections. Depending on your preference speed may be the focus or size. The resulting connections leave some unused gates. The rough LE-to-gatecount estimate are ballpark figures and just tell you about the order. Make sure not to plan with an FPGA that is too small. You best do a design with the supplied tools and let the tool choose a chip for your. Then have a look at the unused gates and think about future wishes and such. Rene -- Ing.Buero R.Tschaggelar - http://www.ibrtses.com & commercial newsgroups - http://www.talkto.net Jasmine Hau wrote: > Hi, can anybody tell me how to get the total gate count approximation > from Logic Elements (LEs) in Altera Stratix and APEX device??? Thank > you very much.Article: 71638
hauyuanwen1980@yahoo.com (Jasmine Hau) wrote in message news:<fc6016ce.0407252155.6c7df59b@posting.google.com>... > Hi, can anybody tell me how to get the total gate count approximation > from Logic Elements (LEs) in Altera Stratix and APEX device??? Thank > you very much. Check out AN 110: Gate Counting Methodology for APEX 20K Devices - http://www.altera.com/literature/an/an110.pdf LE's from APEX roughly compare to Stratix LE's if LUT's and Registers is what you need. K.R. KarlArticle: 71639
Hi all, I have just made the last release 0.7 of the freeware WinFilter available on the web. http://www.winfilter.20m.com WinFilter is a software tool provided as freeware to design digital filter. A GUI makes it very user friendly. This software can design as well IIR filters as FIR filters and can generate the C and VHDL code. The filter coefficients are now quantizied in float, 16-bit or 8-bit. FIR filter are now synthezis in VHDL (speed or size optimization) with a Resources Usage Estimation. Cheers, Adrian -----= Posted via Newsfeeds.Com, Uncensored Usenet News =----- http://www.newsfeeds.com - The #1 Newsgroup Service in the World! -----== Over 100,000 Newsgroups - 19 Different Servers! =-----Article: 71640
hauyuanwen1980@yahoo.com (Jasmine Hau) wrote in message news:<fc6016ce.0407252155.6c7df59b@posting.google.com>... > Hi, can anybody tell me how to get the total gate count approximation > from Logic Elements (LEs) in Altera Stratix and APEX device??? Thank > you very much. Hi Jasmine, maybe you could have a look at a data sheet of Altera Stratix devices where the build up of such a Logic Element is explained. I guess there you should be able to find the number of gates per LE. Rgds AndréArticle: 71641
Hello,everyone!I made a design following the tutorial in the nios develop kit and do the pin assignment as the example the factotry supplys.Then I downloaded to apex board using quartusII .But I cannot download my execute code to the FPGA .The sdk shell annouce that waiting for the target.........why?Thanks.Article: 71642
Hi out there, I have read an article about a clock multiplexer BUFGMUX which is involved in the VIRTEX II devices. Did somebody have any experience with that mux ? Is there something comparable in Altera Stratix/Cyclone devices ? I would appreciate any info. Thank you.Article: 71643
Hello! I have a problem with the swift interface and ModelSim.. when I try to load my project the follow error are returned: # Loading D:/CAE_Tools/Modeltech_5.8/win32pe/libsm.dll # ** Error: Failed to find LMC SmartModel libswift entry in project file. # ** Fatal: Foreign module requested halt. I would like to know the cause of this error.. Best regards, alessioArticle: 71644
GS, The ip of the 3.125 Gbs transceivers in the Virtex II Pro was developed by Connexant, and does not belong to us. We do not have the luxury of disclosing the verilog, even if we wanted to. Now, for the other Rocket I/O (tm) developed by us, we do have that option. I will let the folks in charge know. Thanks, Austin General Schvantzkoph wrote: > On Sun, 25 Jul 2004 08:10:33 +0000, Tim wrote: > > >>Unfortunately, sim/n of SWIFT models requires a SWIFT-model supporting simulator >>- bit of a bugger if you've only got Modelsim XE. > > > The performance is also awful. My testbench takes a 10 to 1 performance > hit when using the RocketIO SWIFT models (I use them in both NCverilog and > ModelSim, it cripples both of them). Would Peter or Austin please explain > why Xilinx decided to use SWIFT models instead of a plain Verilog model. > The secrets in a SerDes are at the transistor level not at the logic > level. A nice fast bus functional Verilog model would have been prefered > by all. >Article: 71645
news@sulimma.de (Kolja Sulimma) wrote in message > If you do not require large quantities only CPLD are available in that > quantity. Ooops. Should have been: "If you do not require large quantities only CPLD are available for that price." Kolja SulimmaArticle: 71646
starfire wrote:
>
> Are there any FPGA parts available today that can contain a 32-bit,
> free-running counter running at 1GHz and a 32-bit storage register to take a
> snapshot of the count and read it to a slower external interface?
>
> The Xilinx Virtex II Pro seems to go up to about 325MHz...
I am surprised that no one has mentioned that you can pipeline a counter
to get much higher speeds. This takes more logic and your capture
registers must also be pipelined, but you can get much higher speeds
this way. Each bit of the counter has two FF outputs, one is that bit
of the count and the other is the carry out to the next stage. So each
bit of the counter will be one clock behind the next lower bit. It only
requires a single stage of carry propogation, so longer counters do not
run slower. This will run at about the same speed as a toggle FF.
Ci-1 ---- ----
-------| & |--------|D Q|--- Ci
+---| | | |
| ---- clk---|> |
+------------+ ----
---- |
|D Q|---+-------- Bi
clk | |
-------|> |
----
--
Rick "rickman" Collins
rick.collins@XYarius.com
Ignore the reply address. To email me use the above address with the XY
removed.
Arius - A Signal Processing Solutions Company
Specializing in DSP and FPGA design URL http://www.arius.com
4 King Ave 301-682-7772 Voice
Frederick, MD 21701-3110 301-682-7666 FAX
Article: 71647Vikram Thank you for your response. I have been in contact with local Xilinx FAEs. They are not saying either that XC2S300E-6-FG456 device would not support PCI32/33 standard. They even provided us with the UCF file without FLOORPLANNING. Since the Spartan 2E is just a cost reduced version of the virtex E device they are not sure how the device will perform without floorplanning.What is your opinion? Please let me know. thanks Krishna Kumar DSP Systems Engineer Signalogic Inc Dallas, TX Vikram Pasham <Vikram.Pasham@xilinx.com> wrote in message news:<4101ED63.F1C68A16@xilinx.com>... > > Would it be safe to assume > > that the FG456 version would meet the timing of the PCI interface. Has > > anybody implemented a PCI core in the device that I am talking about? > > Please let me know. Any comments and suggestions towards device > > selection would also be appreciated > > XC2S300E-6-FG456 supports PCI 64/33 and I don't expect any problems with > PCI 32/33. > > PCI 32/33 LogiCORE only includes UCF file (pin out) for supported devices. > Try contacting your FAE or hotline to obtain UCF file for PCI 32/33 > targeting FG456 device. > > Regards > VikramArticle: 71648
When we experiment in the lab, we do that with (pre)production devices. So we are then weeks or a few months ahead of general availability. Peter Alfke, Xilinx Applications > > A few months ago Xilinx announced that they had achieved 1 GHz performance > in the lab, so it's probably a couple of years away for production devices. > > Leon > >Article: 71649
I think your safest bet is to sample the input with four staggered 250 MHz clocks, feeding four shift registers.Then differentialte the edges and move them into a common 250 MHz clock domain. Or you use 8 phases for an even safer circuit. Virtex-II can adjust the clock in 50 ps increments, and 250 MHz is reasonable, while 125 MHz is easy, and definitely guaranteed to work. You can capture the data, store the arrival time of 512 input pulses in a BlockRAM and read the data out at your convenience. The trick of using MGTs has not been proven yet, but this thread rekindled my interest... Peter Alfke, Xilinx Applications. > From: "starfire" <starfire151@cableone.net> > Organization: Posted via Supernews, http://www.supernews.com > Reply-To: "starfire" <starfire151@cableone.net> > Newsgroups: comp.arch.fpga > Date: Sun, 25 Jul 2004 11:07:58 -0600 > Subject: 1GHz FPGA counters > > Are there any FPGA parts available today that can contain a 32-bit, > free-running counter running at 1GHz and a 32-bit storage register to take a > snapshot of the count and read it to a slower external interface? > > The Xilinx Virtex II Pro seems to go up to about 325MHz... > > Thanks. > > Dave > >
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