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ALuPin@web.de (ALuPin) wrote in message news:<b8a9a7b0.0407280514.48df66a9@posting.google.com>... > Hi, > > I have the following problem: > > The Altera Cyclone device I am using does have two PLLs. > > Because of the fact that I am using only one PLL the compiler > seems to use PLL1 on bank 1 of the device. > > But I need to route the external clock output of the PLL to bank 3 of > the device. For that purpose I need PLL2 at bank 3 to be used. > > How can I tell the compiler not to use PLL1 (bank 1) but PLL2 (bank 3) ? > Is there some option? > The steps to do this are as follows, after you have compiled the design once: 1. Open the Assignment Editor, using Tools->Assignment Editor. 2. Click on the Category drop down at the top of the Assignment Editor to say PLL. 3. Double Click in an empty cell in the To column and then click on the right arrow button to open the Node finder. Select the PLL name that you created. (if you do not compile the design as specified in Step1 you will not see the PLL name). 4. Click on the cell in the Location column and select PLL_2 from the drop down. 5. Compile the design. Alternatively if you prefer the command line type into the Quartus tcl console: set_location_assignment -to "foo:inst" PLL_2 where "foo:inst" is the instance that represents the PLL. Hope this helps. Subroto Datta Altera Corp.Article: 71726
rickman wrote: (SNIP) > So > every time I routed the design, I had to tweek that one route in the > chip editor regardless of the time to market impact. Besides, the time > to market is fixed... my overtime is not. I'd rather spend a few extra > minutes every time I do a route than fight a tool for weeks. Hi Rick, If as you say, you haven't used FPGA Editor in a few years, then you haven't seen the relatively new feature, Directed Routing. It would be useful for your example in that you would only need to manually route the connection once and then save the directed routing constraints to the UCF file. From that point on, the PAR routing will be determined by the constraint. See Tools --> Driected Routing Constraints. This feature can also be used along with RPMs to replace the functionality of routed hard macros. As long as the relative pin locations and routing resources are the same as the original case, the directed routing constraints will work. This doesn't address the issue of manually routing in the first place which I agree is difficult. Regards, BretArticle: 71727
Hello Does anybody know where to find the Spartan2E FG456 package file. I need this file for creating a schematic part symbol. As an example for a package file I was able to find for virtex 2 in the link http://www.xilinx.com/products/virtex/v2packages.htm Please let me know. thanks Krishna KumarArticle: 71728
In article <ce8p5u$r8c3@cliff.xsj.xilinx.com>,
Austin Lesea <austin@xilinx.com> wrote:
>Michael,
>Series capacitors? Why? When you AC couple, now you have the impedance
>bump due to the layout from the caps, and their own ESL/ESR.
Solder some extras in parallel with them, but I doubt this is his issue.
We've sent 2.5 Gb/sec SONET through capacitors and jumpers (stubs when open)
without problems (the FR-4 helps you by reducing the high frequencies).
Here's a low tech long shot: maybe a ball is opening when the chip heats up.
It wouldn't be always open, otherwise the TDR would have picked it up. So
is it broken in one instance (one particular board, one location) or
in several?
Rule out other low tech problems as well, like incorrect supply voltage.
--
/* jhallen@world.std.com (192.74.137.5) */ /* Joseph H. Allen */
int a[1817];main(z,p,q,r){for(p=80;q+p-80;p-=2*a[p])for(z=9;z--;)q=3&(r=time(0)
+r*57)/7,q=q?q-1?q-2?1-p%79?-1:0:p%79-77?1:0:p<1659?79:0:p>158?-79:0,q?!a[p+q*2
]?a[p+=a[p+=q]=q]=q:0:0;for(;q++-1817;)printf(q%79?"%c":"%c\n"," #"[!a[q-1]]);}
Article: 71729Hi Philip, Thanks for those US patent references. It contains a detailed info of almost all the things i looked for.. --raj Philip Freidin <philip@fliptronics.com> wrote in message news:<2gpeg0da7n78n2vj1ohasuhhcjnul595ap@4ax.com>... > On 27 Jul 2004 21:38:07 -0700, rajarsheeb@yahoo.com (raj) wrote: > >Thanks Rick for your inputs. > >Can you suggest some pointers regarding these? > >--raj > > Have a look at a similar reqest and my response at: > > http://www.fpga-faq.com/archives/55100.html#55101 > > There is a wealth of detailed info available at www.uspto.gov > for example patent 4,870,302 would be a good place to start. > > start here: http://patft.uspto.gov/netahtml/search-bool.html > > Others that might interest you include: > > 5631577 > 5598424 > 5742531 > 5995988 > > Philip Freidin > > > =================== > Philip Freidin > philip.freidin@fpga-faq.com > Host for WWW.FPGA-FAQ.COMArticle: 71730
widding@birger.com (Erik Widding) wrote in message news:<afe40eec.0407271638.28365ac6@posting.google.com>... > > As we could not wait for the bugs to be fixed, we developed a PCI > to PLB, and PCI to OPB bridge, with DMA (pci master) support on > the PLB side. This core supports bursting on all but the OPB buses > at present. We can make this available on a commercial basis. It > is wrapped around the Xilinx PCI logicore, which I should note is > one of the best documented, most flexible, pieces of IP we have > ever used. It has been brought to my attention that the above paragraph appears to be an offer to redistribute the Xilinx PCI Logicore. It was my intention to offer our wrapper sans the Xilinx core. I appologize for any confusion this has caused. Regards, Erik Widding. --- Birger Engineering, Inc. -------------------------------- 617.695.9233 100 Boylston St #1070; Boston, MA 02116 -------- http://www.birger.comArticle: 71731
praveen wrote: > Hello, > What is the differences between FPGA and CPLD? > > What basis on which i should select. whether to go for cpld or fpga? 10 years ago, things were relatively simple : FPGA's were pretty much all RAM/loader designs, with low power, and granular logic. CPLDs were were higher power, fast with wide-logic terms, and limited in register count. These days, there is much more overlap and bluring of the lines. # Some FPGAs are FLASH (Lattice, Actel) # Some CPLDs have granular logic ( MAX II ) # Some CPLDs have RAM/Loader built in ( MAX II, Coolrunner... ) # For lowest static power, modern CPLDs are << modern FPGA The first point of selection would be the register count, then the logic/RAM/DSP considerations. You could, in some cases, design with both ( or use uC + FPGA ) to solve all the design problems. -jgArticle: 71732
Austin Lesea wrote: > Rick, > > And thus the battle is joined.....again > > Yes, well, we have only been at this for twenty years now, and we are > still refining the whole process. Routing by hand is a pretty useful > thing to know (when all else fails, or there is something that just has > to be done a certain way), but it is also something that leads to the > longest time to market, so it naturally does not get much attention (why > should it, when it delays the sale of a part?). > > One issue in making FPGA_Editor look like the hardware schematic, is > that we have to make the hardware view match the software view. <snip> I believe rickman was talking about the routing aspect, so he does not require, nor expect, that the hardware view should match the software view. The SW only has to display the routing choices, ideally in a delay-proportional manner - ie it is information the tools already have, it is just not as easy to visually scan for 'oops' results. The std human eyeball is very good at inspecting a route-pattern, and seeing too-long paths. Given the trends in modern flows, perhaps this visual inspect tool could have a histogram option, that plots local-flight-times by route-segment ? -jgArticle: 71733
Hello, I have been using the Riscwatch box w/ RISCwatch ver. 5.1 software. I am running Linux on our embedded PPC405D. The trace captures the instructions with their virtual addresses. However, when an interrupt is detected, the processor uses the physical addresses, at which point Riscwatch complains it is "not configured" to read those addresses. I suspect that it thinks that the physical address is virtual, so when it goes into the TLB and/or page table for the translation, it can't find it since there isn't obviously a translation. In other words, I think that Riscwatch should switch to real mode instead at that point. How can configure RISCwatch to access those interrupt address locations that need physical address? Anyone encountered this problem and found a way around it? I e-mailed IBM about it, but haven't gotten a response yet... Thanks, NNArticle: 71734
is it possible to connect two entities with instantiating them as components.Article: 71735
How about an FPGA which looks like a CPLD (in programming terms) No boot prom or external logic, instead this has internal eeprom. http://www.latticesemi.com/products/fpga/xpga/index.cfmArticle: 71736
Hi, Is there someone who can help me to find good documents on the wishbone protocol ? Some sort of introduction... Thanks, TomArticle: 71737
praveen wrote: > Hello, > What is the differences between FPGA and CPLD? > > What basis on which i should select. whether to go for cpld or fpga? > CPLDs are most often used for less datapath intensive timing-critical designs (i.e. more control-path like stuff), while FPGAs are fine for highly datapath intensive designs. FPGAs are rather easily scalable. That is, they have a structure comparable to US-like (i.e. "constructed") cities. You have a very regular grid with buildings (i.e. logic blocks) as well as horizontal and vertical streets (i.e. the connections). You can easily extend the structure at the borders. CPLDs have a completely different structure. Mostly, there is a centralized connection structure and the logic elements are grouped around it. Thus, the analogy is something like a farm. You can recognize easily that such a design does not scale very well. Because of that, the CPLDs have a rather small capacity when compared to FPGAs. However, they have the big advantage of a predictably fast interconnection. I.e. it does not matter where the logic elements are positioned - the delay of the connections between them is almost the same. This is not the case for FPGAs. There, the farther the elements are away from each other, the higher the delay. Besides this difference, CPLDs have mostly much more powerful logic elements than FPGAs. This also attributes to the use of CPLDs especially for control paths. Another difference that has been already cited by others is typically the non-volatile nature of CPLDs and the volatile nature of FPGAs. Regards, MarioArticle: 71738
Tom wrote: > Hi, > > Is there someone who can help me to find good documents on the wishbone > protocol ? Some sort of introduction... Tom, are you aware of this site: http://www.opencores.org/projects.cgi/web/wishbone/wishbone Regards, MarioArticle: 71739
Hi all,
I need some help here for implementing an efficient adder with carry
out.
Target : V2Pro
System : WinXP, ISE 6.2.03 sp3
I am trying to implement a 16 bit adder with carry out. I use the vhdl
description for this as stated in the XST user guide (see src code
added at the bottom of this post):
q <= ('0'&a) + ('0'&b);
where a and b are 16 bits, q is 17 bits.
After PAR I see that the MSB of q (which is the carry out) is not
using the carry chain, but uses local routing. SO : functionally it is
OK, but timing is sub-optimal (about 250MHz in -5 V2Pro).
When I implement a 17 bit adder with carry out (so 1 bit larger) :
carry chain is OK, and we can get better timing (up to 290 MHz).
I also tried the adder from CoreGen but the result is the same.
Is there anyone who managed to make an adder with carry-out that uses
the carry chain all the way, regardless of the width?
Your help is much appreciated,
Bart
---------------------------------------------------------------
--
-- File tstAdderCy.vhd
-- Author BADZ
--
-- Target XC2VP20-5ff896 / XST ISE6.2.03i
--
-- Function : 16 bit adder with carry out
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
-- synopsys translate_off
library unisim;
use unisim.vcomponents.all;
-- synopsys translate_on
entity tstAdderCy is
port (
sClk : in std_logic;
a : in std_logic_vector(15 downto 0);
b : in std_logic_vector(15 downto 0);
out1 : out std_logic_vector(16 downto 0)
);
end tstAdderCy;
architecture arch of tstAdderCy is
signal areg, breg : std_logic_vector(15 downto 0);
signal areg2, breg2 : std_logic_vector(15 downto 0);
signal tmp1 : std_logic_vector(16 downto 0);
begin
process(sClk)
begin
if rising_edge(sClk) then
-- tck 1
areg <= a;
breg <= b;
-- tck 2
areg2 <= areg;
breg2 <= breg;
-- tck 3
tmp1 <= ("0"&areg2) + ("0"&breg2); -- MSB of adder = last
carry out bit, but MAP does NOT use dedicated carry-nets => not OK for
timing
-- tck4
out1 <= tmp1;
end if;
end process;
end arch;
--------------------------------------------------------------
Article: 71740
On 29 Jul 2004 04:20:49 -0700, zeeman_be@yahoo.com (Bart De Zwaef)
wrote:
>Hi all,
>
>I need some help here for implementing an efficient adder with carry
>out.
>Target : V2Pro
>System : WinXP, ISE 6.2.03 sp3
>
>I am trying to implement a 16 bit adder with carry out. I use the vhdl
>description for this as stated in the XST user guide (see src code
>added at the bottom of this post):
>
>q <= ('0'&a) + ('0'&b);
>where a and b are 16 bits, q is 17 bits.
>
>After PAR I see that the MSB of q (which is the carry out) is not
>using the carry chain, but uses local routing. SO : functionally it is
>OK, but timing is sub-optimal (about 250MHz in -5 V2Pro).
>
>When I implement a 17 bit adder with carry out (so 1 bit larger) :
>carry chain is OK, and we can get better timing (up to 290 MHz).
>
>I also tried the adder from CoreGen but the result is the same.
>Is there anyone who managed to make an adder with carry-out that uses
>the carry chain all the way, regardless of the width?
>
>Your help is much appreciated,
>Bart
Hi Bart,
I have observed exactly the same symptoms, but with another
synthesiser (Synplify Pro). I think the problem is with MAP rather
than the synthesiser. MAP doesn't seem to handle the last bit in an
odd length carry chain well.
My solution (as usual) was to create a module that instantiated the
unisim components directly (with RLOC attributes), so that I got
exactly what I wanted.
BTW, this bug has been around for at least three years. At the time,
I was having a lot of trouble implementing a 17 and 33 bit adders. I
came to the conclusion that Xilinx's test suite probably only has even
length adders.
Regards,
Allan.
Article: 71741Hi You are not using C<0> bit any where in your design. I am not sure why Xilinx and Altera tools are giving different warnings. In both tools they are not implementing the C<0> bit internally. (you can see this through the RTL view provided in quartus and xilinx tools) Xilinx is giving you a warining so that you can remove that bit from your vhdl file. Altera is not giving any warning but both s/w won't implement that bit bye bijoy David Dye <davidd@xilinx.com> wrote in message news:<4107C89E.9020705@xilinx.com>... > Shahabuddin, > > I ran this code through ISE/WebPack 6.2.03i (the current version), and I > see the following warning issued during HDL Synthesis: > > WARNING:Xst:1780 - Signal <C<0>> is never used or assigned. > > Any unused or unconnected signal should trigger this warning in XST. > > thanks, > david. > > Shahab wrote: > > Hi.. > > > > I have one question regarding xilinx ise webpack. > > > > Why it doesn?t give any error of type missing source code . bcoz I tried > > to run some codes on xilinx ise webpack and then on altera maxpllus II. > > > > On altera I was continuously getting messges like missing source code > > "C0" while the same code was running fine on xilinx tool. > > > > the code is : > > > > library ieee; > > use ieee.std_logic_1164.all; > > > > entity fib is > > port (Clock,Clear: in std_ulogic; > > Load: in std_ulogic; > > Data_in: in std_ulogic_vector(15 downto 0); > > S: out std_ulogic_vector(15 downto 0)); > > end entity fib; > > > > architecture behavior of fib is > > signal Restart,Cout: std_ulogic; > > signal Stmp: std_ulogic_vector(15 downto 0); > > signal X, Y: std_ulogic_vector(15 downto 0); > > signal C : std_ulogic_vector (15 downto 0 ); > > signal Zero: std_ulogic; > > signal CarryIn, CarryOut: std_ulogic_vector(15 downto 0); > > > > begin > > P1: process(Clock) > > begin > > if rising_edge(Clock) then > > Restart <= Cout; end if; end process P1; > > > > Stmp <= X xor y xor CarryIn; Zero <= '1' when Stmp = "0000000000000000" > > else '0'; > > > > CarryIn <= C(15 downto 1) & '0'; CarryOut <= (Y and X) or ((Y or X) and > > CarryIn); C(15 downto 1) <= CarryOut(14 downto 0); Cout <= CarryOut(15); > > > > P2: process(Clock,Clear,Restart) > > begin > > if Clear = '1' or Restart = '1' then > > X <= "0000000000000000"; Y <= "0000000000000000"; elsif > > rising_edge(Clock) then if Load = '1' then X <= Data_in; elsif Zero = > > '1' then X <= "0000000000000001"; else X <= Y; end if; Y <= Stmp; end > > if; end process P2; > > > > S <= Stmp; end behavior; > > > > I would like to know what is the addition in xilinx ise which altera > > maxplus II doesn?t have? > > > > Waiting for your reply. > > > > Shahabuddin InamdarArticle: 71742
me@linnix.info-for.us (Linnix) wrote: > praveenkumar1979@rediffmail.com (praveen) wrote in message news:<ff8a3afb.0407280557.36cb274f@posting.google.com>... > > Hello, > > What is the differences between FPGA and CPLD? > > General logics vs. Simple reg/decoder > Expensive ($10 - $20) vs. Cheap ($1 - $2) > Big (> 100 pins) vs. Small (> 44 pins) I use Fpgas in 84cqfp while I have just read, that Altera ships its new MaxII CPLD in up to 324 pin BGA. I think the first point ist the best way to differ between CPLD and Fpga. bye ThomasArticle: 71743
Hello I'm wondering how configurations registers are usually implemented. By this I mean I have in my design value I want to be run-time configurable. So each of this value is read (and read only), and on the other side, there is an address / data / strobe bus. So that a controller can read/write a register given it's adress. I'm looking for a space efficent way. I don't think I can use memory blocks for this since they are all read in // ... What I've come up with so far is type reg_space is array (integer range <>) of std_logic_vector(31 downto 0); signal registers : reg_space(63 downto 0); signal address : std_logic_vector(5 downto 0); Then to write a value in a process : registers(address) <= one_32bits_regs; But that last statment is incorrect ... He doesn't wan address to index registers. SylvainArticle: 71744
Rene Tschaggelar <none@none.net> wrote: > praveen wrote: > > What is the differences between FPGA and CPLD? > > The common understanding is that CPLDs are EEPOM or Flash based > and have to be programmed once. They have up to say 512 Flipflops. > FPGAs on the other hand are RAM based, meaning they have to be > programmed at every powerup. This usually happens with a small > external Flash, a CPU or whatever. The smallest FPFA is far bigger > than the biggest CPLD. That's pretty wrong. Actel has flashbased Fpgas (and antifuse based). The main difference is that CPLDs are mainly focused on Input->(fast)Logic->Register->Output while Fpgas are typically slower for CPLD tasks, but have more configuration possibillities and support more complex logic structures. A typical CPLD design would have fast but simple operations while a fpga has complex operations based on many internal registers. bye ThomasArticle: 71745
You can't use a std_logic_vector as index - use an integer. If you need the address as output you have to convert it. Manfred "Sylvain Munaut" <tnt_at_246tNt_dot_com@reducespam.com> schrieb im Newsbeitrag news:4108e760$0$31480$ba620e4c@news.skynet.be... > Hello > > I'm wondering how configurations registers are usually implemented. By this I mean I have in my design value I want to be run-time configurable. So each of this value is read (and read only), and on the other side, there is an address / data / strobe bus. So that a controller can read/write a register given it's adress. > > I'm looking for a space efficent way. I don't think I can use memory blocks for this since they are all read in // ... > > What I've come up with so far is > > type reg_space is array (integer range <>) of std_logic_vector(31 downto 0); > signal registers : reg_space(63 downto 0); > signal address : std_logic_vector(5 downto 0); > > > Then to write a value in a process : > > registers(address) <= one_32bits_regs; > > > But that last statment is incorrect ... He doesn't wan address to index registers. > > > > SylvainArticle: 71746
Another point blurring the line between FPGA and CPLD is pin-to-pin speed. 10 years ago an FPGA was clearly not suited to fast asynchronous designs. Modern FPGA's, while not as fast as the fastest modern CPLD are often fast enough for functions like address decoding and asynchronous memory interface. Also you will find both FPGA's and CPLD's with programmable I/O standards (LVTTL, LVCMOS, SSTL, HSTL, LVDS...) Price per gate is still less in FPGA, but the overall price range now overlaps considerably. Still: if the design is static and fits in a CPLD, you're probably going to get off cheaper with a CPLD. if the design requires instant-on you're again probably better off with a CPLD, although a few FPGA's have this feature. if the design requires flexibility to download different logic depending on the end use, you're generally better off with FPGA due to both the SRAM-based infinite-reload capability, and ease of fitting designs after the pinout has been fixed. Jim Granville <no.spam@designtools.co.nz> wrote in message news:<YfXNc.909$zS6.112816@news02.tsnz.net>... > praveen wrote: > > Hello, > > What is the differences between FPGA and CPLD? > > > > What basis on which i should select. whether to go for cpld or fpga? > > 10 years ago, things were relatively simple : > FPGA's were pretty much all RAM/loader designs, with low power, > and granular logic. > CPLDs were were higher power, fast with wide-logic terms, and > limited in register count. > > These days, there is much more overlap and bluring of the lines. > > # Some FPGAs are FLASH (Lattice, Actel) > # Some CPLDs have granular logic ( MAX II ) > # Some CPLDs have RAM/Loader built in ( MAX II, Coolrunner... ) > # For lowest static power, modern CPLDs are << modern FPGA > > The first point of selection would be the register count, then > the logic/RAM/DSP considerations. > > You could, in some cases, design with both ( or use uC + FPGA ) > to solve all the design problems. > > -jgArticle: 71747
It sounds like you want a "de-compiler" What you get from the schematics is structural VHDL describing the library modules and their connections from the netlist. You would need a tool that understood the functions of the library primitives and converted the instances into code that infers the same function. I've never seen anything like that. "buke2" <cubah@tlen.pl> wrote in message news:<ce7m97$16g$1@nemesis.news.tpi.pl>... > Hello all, > anybody knows how can I extract equations from Xilinx schematic? > I tried in Schematic Editor: Option->ExportNetlist and VHD file has been > generated...but to get clear equations (Out=f(In)) I must translate whole of > file... > > Maybe somhere is tool for extracting euations from VHDL file? > > Regards > KubaArticle: 71748
I don't read need the address at output, it's read from fpga pins ( I know, here I put it as signal but it's a in port in my design ). How would I convert it to integer ? does that involves logic or it's just synctatic sugar ? Sylvain Manfred Balik wrote: > You can't use a std_logic_vector as index - use an integer. > If you need the address as output you have to convert it. > Manfred > > "Sylvain Munaut" <tnt_at_246tNt_dot_com@reducespam.com> schrieb im > Newsbeitrag news:4108e760$0$31480$ba620e4c@news.skynet.be... > >>Hello >> >>I'm wondering how configurations registers are usually implemented. By > > this I mean I have in my design value I want to be run-time configurable. So > each of this value is read (and read only), and on the other side, there is > an address / data / strobe bus. So that a controller can read/write a > register given it's adress. > >>I'm looking for a space efficent way. I don't think I can use memory > > blocks for this since they are all read in // ... > >>What I've come up with so far is >> >>type reg_space is array (integer range <>) of std_logic_vector(31 downto > > 0); > >>signal registers : reg_space(63 downto 0); >>signal address : std_logic_vector(5 downto 0); >> >> >>Then to write a value in a process : >> >>registers(address) <= one_32bits_regs; >> >> >>But that last statment is incorrect ... He doesn't wan address to index > > registers. > >> >> >>Sylvain > > >Article: 71749
Sounds a little complicated. Any random number generator 101 for me? Plus, how can FPGA tossing give me random number with normal distribution? Austin Lesea <austin@xilinx.com> wrote in message news:<ce8dob$r8a2@cliff.xsj.xilinx.com>... > Yup, > > But I was trying to deal with the original generator! But you are > absolutely correct! Nice to remember if you suspect someone has an > unfair coin...... > > Best to test the original random number generator (as close to the core > of its function). > > Then one can add correction for 1/0 density, as you suggest. That does > not solve for frequency effects, however. > > The NIST suite of tests, or Diehard tests are best applied to the core > generator, so you can see its problems. Then there are known and > accepted techniques to use a biased generator, or even a RNG with > frequency problems to create a better TRNG. > > Austin > > Nicholas Weaver wrote: > > In article <ce6dhn$r892@cliff.xsj.xilinx.com>, > > Austin Lesea <austin@xilinx.com> wrote: > > > >>Symon, > >> > >>Your method is greatly flawed. In addition to being very slow, it is > >>subject to the imbalance of the weight of the device. You would first > >>have to add weight or trim weight to make sure the toss was fair. > > > > > > Nah, a biased coin is perfectly fine: > > > > Flip twice: > > HH -> try again > > HT -> Heads > > TH -> Tails > > TT -> try again.
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