Custom Search
Site Home Archive Home FAQ Home How to search the Archive How to Navigate the Archive
Compare FPGA features and resources
Threads starting:
Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z
Thanks for the references, Tom. I looked briefly at the abstracts of a few, and they are quite relevant. I will look at them in more detail. Fred -- Fred Ma Dept. of Electronics, Carleton University Ottawa, Ontario, CanadaArticle: 71251
Allan Herriman <allan.herriman.hates.spam@ctam.com.au.invalid> wrote in message news:<2fl4f0logarjcjnhkh3ovi9eckaqqkj0jo@4ax.com>... > On 12 Jul 2004 01:43:55 -0700, moti@terasync.net (Moti Cohen) wrote: thnaks.. luckily, I found a program in the web that generates a complete ethernet packet. This is the link if anyone needs a similar thing.. http://www.fpga4fun.com/10BASE-T2.html Regards, Moti. > > >Hy guys, I'm currently working on a 10/100 ETHERNET mac implementation > >in an FPGA (using vhdl). in order to simulate my state machine I need > >to feed a real ETHERNET packet to it (in order to see if the crc check > >is exeuted correctly etc.). I will realy appreciate to get a complete > >ETHERNET packet (all bytes from PREAMBLE to FCS) so I could insert it > >to my modelsim simulation. > > > >the format I'm expecting is as follows.. > > > >[55][55][55]... -> .. [FCS3][FCS2][FCS1][FCS0] > > You could use a network sniffer to capture a packet from your LAN. > This will not capture the preamble and is unlikely to capture the CRC. > You may get lucky though. > I just checked with Ethereal ( http://www.ethereal.com/ ) and it > didn't capture the CRC on my hardware :( > > Or, you could ask on news:comp.dcom.lans.ethernet, where this question > would be on-topic. > > Regards, > Allan.Article: 71252
it seems most likely your FPGA will be very underutilized...Go for CPLD... Kelvin "Jim Granville" <no.spam@designtools.co.nz> wrote in message news:FWGFc.6084$NA1.570776@news02.tsnz.net... > John Jacobs wrote: > > A new large-diameter, permanent magnet motor line is currently under design > > for very low speed (2 rad/sec), high-precision (10 urad) applications. For a > > 3-phase motor, torque ripple is ~7%, with ripple inversely proportional to > > the number of phases. > > That's true for a fixed voltage/sine drive : with electronics it does > not have to be either. > > > > > An attractive alternative to the standard 3-phase controller is an FPGA > > multi-phase controller where each stator coil is individually controlled. > > For the preliminary design, somewhere in the range of 30 stator coils will > > be utilized. > > > > Has anyone had any experience in using an FPGA for this type of application? > > Commercial drivers are primarily based on either trapezoidal or sinusoidal > > commutation schemes, and it would seem that since each coil could be > > individually controlled, either scheme could be readily implemented. > > Commercial and open cores all seem to be based on the standard 3-phase > > windings. > > FPGA would be well suited to this, as would higher end DSPs, and some > DSP vendors have specific motor development kits. > At the extremes of precision, the problems are not just electrical - > the best motor-optimise designs I have seen, include a Motor-Cal-ROM, > that is the calibrations of that particular motor. > High precision absolute Rotary encoder feedback is another method to > check/calibrate the motor behaviour. Also remember copper wire has a > significant temperature coefficent. > > -jg >Article: 71253
Hi, I am having a problem during the synthesis (with ISE) of my design, with the following error message : "ERROR:HDLCompilers:88 - Parameter 'INIT' does not exist in module 'FD'" Here are some details on this design : I am using a component I wrote in vhdl which instanciates a KCPSM 3 with a program rom.This component synthesizes perfectly, but when I'm trying to synthesize the top-level design, XST crashes. Actually, in the top-level, I am using other modules, written in verilog by Xilinx, which uses FD's.I think the problem is that the module definitions (in verilog) for synthesis black boxes for theses "FD" modules does not match with the corresponding component declarations in vhdl of a FD flip flop, because in vhdl this declarations INCLUDES a generic, which is the init value "INIT"... How can I solve this problem?Article: 71254
My best guess would be : to simply signal that the program is not dead and suggest to be a bit patient, the process being time consuming. Matthew E Rosenthal <mer2@andrew.cmu.edu> wrote in message news:<Pine.GSO.4.58-035.0407122225260.3311@unix5.andrew.cmu.edu>... > Just curious while running P&R in ISE > during the placement part it runs through several phases, 1.1, 2.2, 3.3, > 4.5, 5.8, etc > usually during phase 5.8 I see several rows of text containing just > dots(...), there are different numbers of dots per line. > > Wut do these dots mean? > > MattArticle: 71255
Got any Verilog parser? Kelvin "Sumit Gupta" <sumitg@gmail.com> wrote in message news:82b44722.0407121536.88095e0@posting.google.com... > Hi all > > I wrote a VHDL parser as part of another larger software tool about 6 > years ago. The webpage, on which the parser is, is going to be > retired soon. So, if anyone is interested, here is a link to my > parser: > > http://www.cecs.uci.edu/~iesag/oldPage/Topts/ > > Regards > SumitArticle: 71256
Peter wrote: > > In its normal use as series terminator, DCI shows insignificant additional > power dissipation ( and zero additional system power compared to external > resistors). > A bit more than zero power is needed for Virtex 2 DCI when you include the worst case VRP/VRN overhead power of ~200 mW/bank. Should be much better in V2Pro and S3 with the new DCI control logic to cleanly stop the DCI updates. Brian Peter Alfke <peter@xilinx.com> wrote in message news:<BD18132B.76CC%peter@xilinx.com>... > Let's squash an urban legend: > In its normal use as series terminator, DCI shows insignificant additional > power dissipation ( and zero additional system power compared to external > resistors). > It is only when DCI is used as parallel termination that it draws a > continuous current and thus dissipates significant power. > Peter Alfke > > > > > As for the DCI it does work, but my experience it's a real power hog. > > We had a 64-bit DDR interface and turned it on for a trial, and what > > used to be only a moderately warm FPGA turned into a burn-your-finger > > cooker.Article: 71257
Mikhail, When interfacing external memories with Microblaze you want to use the memory controllers includes in the Embedded Development Kit (EDK) and not the Logicores. For the SDRAM interface you want to use the OPB_SDRAM controller. For the SBSRAM interface you want to use the OPB_EMC controller. For the FLASH interface you want to use the OPB_EMC controller. Both of these cores are supported for Spartan-3 in the latest EDK 6.2 service pack 2 release. Shalin- MM wrote: > Hi all, > > Does anyone have any experience in interfacing SDRAM, SBSRAM and FLASH to > MicroBlaze in Spartan-3? I am somewhat confused with the number of various > memory controllers mentioned on the EDK web pages, albeit many of them don't > name Spartan-3 amongst their target technologies... Can this be done with > just Logicores? > > > Thanks, > /Mikhail > >Article: 71258
Below, I have included example code on how to infer or instantiate a FD
in VHDL and Verilog. You need to use a defparam for the initialization
string in Verilog. These examples are taken from the Libraries Guide
that can be found at:
-- go to http://support.xilinx.com/
-- click on "Documentation" on the top black bar
-- click on "Software Manuals" at the top of the page
-- click "6.1i SW Manuals" at the top of the page
-- click "HTML Collection"
-- expand "Libraries Guide" on the left
-- expand "Design Elements"
-- highlight "FD"
Cheers,
Shalin-
VHDL Inference Code
architecture Behavioral of fd is
begin
process (C)
begin
if C'event and C='1' then
Q <= D;
end if;
end process;
end Behavioral;
Verilog Inference Code
always @ (posedge C) begin
Q <= D;
end
VHDL Instantiation Template
-- Component Declaration for FD should be placed
-- after architecture statement but before begin keyword
component FD
-- synthesis translate_off
generic (INIT : bit := '1');
-- synthesis translate_on
port (Q : out STD_ULOGIC;
C : in STD_ULOGIC;
D : in STD_ULOGIC);
end component;
-- Component Attribute specification for FD
-- should be placed after architecture declaration but
-- before the begin keyword
attribute INIT : string;
attribute INIT of FD_instance_name : label is "0";
-- values can be (0 or 1)
-- Component Instantiation for FD should be placed
-- in architecture after the begin keyword
FD_INSTANCE_NAME : FD
-- synthesis translate_off
generic map (INIT => bit_value)
-- synthesis translate_on
port map (Q => user_Q,
C => user_C,
D => user_D);
Verilog Instantiation Template
FD FD_instance_name (.Q (user_Q),
.C (user_C),
.D (user_D));
defparam FD_instance_name.INIT = bit_value;
Nico wrote:
> Hi,
> I am having a problem during the synthesis (with ISE) of my design, with
> the following error message :
> "ERROR:HDLCompilers:88 - Parameter
> 'INIT' does not exist in module 'FD'"
> Here are some details on this design : I am using a component I wrote in
> vhdl which instanciates a KCPSM 3 with a program rom.This component
> synthesizes perfectly, but when I'm trying to synthesize the top-level
> design, XST crashes.
> Actually, in the top-level, I am using other modules, written in verilog
> by Xilinx, which uses FD's.I think the problem is that the module
> definitions (in verilog) for synthesis black boxes for theses "FD"
> modules does not match with the corresponding component declarations in
> vhdl of a FD flip flop, because in vhdl this declarations INCLUDES a
> generic, which is the init value "INIT"...
> How can I solve this problem?
Article: 71259An important detail that I ommited : obviously when you use a KCPSM 3, the program rom is described in HDL (here in VHDL) using attribute definitions to describe the contents of the rom, that's the "INIT" statements I am talking about. My problem is that there seems to be some kind of non-compatiblity with VHDL mixed with Verilog..Article: 71260
pinod01@sympatico.ca (Pino) wrote in message news:<b7ed9648.0407011330.6a729843@posting.google.com>... > Jesse, > > I sent you an e-mail directly but in case I would like to see > those system files if you have them. Although my suspicion is that > your file contains a NIOS master(cpu) which will function correctly > and allow SOPC builder to automatically connect the interfaces > seemlinglessly. However, I did not experience this with my designed > Master. All controllers (slave peripherals) used are directly from > Altera taken from within the SOPC builder system content menu. I am > aware of the two modes to configure the SDRAM, but neither functions > correctly with my master peripheral; however, only with the cpu (NIOS) > does it automatically connect with no errors. The question I still > ponder on is that whether you can indeed design a Master peripheral > using the Avalon Bus or does SOPC builder by default assume that the > only Master peripheral for the automatic connectivity is the "cpu" (ie > NIOS)? If you have a chance I sent you my Master.vhd file and you > can monitor the error I'm getting. Again, it's for this reason why I > have hypothesized my comment in the latter. Don't know if I have done > something erroneous. > > Regards, > Pino > > kempaj@yahoo.com (Jesse Kempa) wrote in message news:<95776079.0406300951.753e78cb@posting.google.com>... > > pinod01@sympatico.ca (Pino) wrote in message news:<b7ed9648.0406291101.30563548@posting.google.com>... > > <snip> > > > > > > tri_state_bridge_0/avalon_slave is not connected to any Master. > > > Please connect it to a master of type avalon. > > > > > > Note that the Master peripheral defined is of type avalon and so is > > > the SDRAM controller (as defined within the Memory devices in the > > > System Contents directory tree). > > > > > > Can someone explain how I can properly connect a Master peripheral > > > (user-defined of course) to the SDRAM controller slave? Why does the > > > tristate bridge not allow this connection to occur? > > > > > > P.S. If this same excercise is done using a NIOS processor master + > > > tristate bridge + SDRAM controller everything is connected with no > > > errors. The only difference that I see is that my Master is a > > > user-defined peripheral. > > > > > > > > > Regards, > > > Pino > > > > Hi Pino, > > > > I believe the problem here is because of the various ways you can > > construct a system with SDRAM. First, are you using Altera's SDRAM > > controller that comes with Nios/SOPC Builder? Our controller has two > > modes of operation with respect to its external pins: > > > > 1. No pin 'sharing'. This is the default behavior, and is what you'd > > select if your board had I/O pins dedicated to SDRAM and SDRAM only. > > In this mode, your master (or a CPU) connects directly to the SDRAM > > controller. There should be no tri-state bridge in between (in fact, > > SOPC Builder shouldn't let you make this connection legally, perhaps > > this is where the issue is...) > > > > 2. SDRAM controller shares some of its pins with a tri-state bus. This > > allows you to save FPGA I/O if your system also has some other > > external memory (Flash, SRAM, etc.). Specifically the dq/dqm/address > > pins are shared. This is activated with a checkbox in the SDRAM > > controller GUI in SOPC Builder. In this mode, Avalon masters *must > > also* directly connect to the controller (your logic, Nios, etc.), but > > in addition, there will be a "More <sdram name> Settings" Page in SOPC > > Builder that appears, and allows you to choose which (if more than > > one) tri-state bridge you wish to route the shared I/O through. In > > this case, the Avalon master/slave connections you make will be > > similar to the first mode I described above: The master (your logic) > > would connect directly to the SDRAM controller, in addition to the > > tri-state bridge. > > > > I just made a simple test-case to verify this using QII4.0/SOPCB4.0 > > and it generates fine/no warning messages. If you want, feel free to > > email me and I will send you the system's files. > > > > Jesse Kempa > > Altera Corp. > > jkempa at altera dot com Just thought I'd provide a quick follow-up and a thanks to Jesse for the help. Others may be reading this and would be of interest. It seems there are several things to do when creating a Master peripheral 1 - I was assigning a bidirectional pin for reading & writing to memory. This is incorrect and as per the Avalon specifications, there must be a unidirection pin for both a read and a write. 2 - apparently you do not need the tristate bridge to be included in teh SOPC builder design. This is used only for external off-chip buses. In my case, I only wanted to have a connection to the SDRAM. Therefore, you must select the option within the SDRAM controller in the System Wizard to "NO shared pins". These two steps make the difference and allows you to compile the generated code.Article: 71261
I allways get the Quartus Warning: Warning: Can't find design file .../projectname0.rtl.mif I found out, this file is from a large Constant in my VHDL-Code which generates a ROM. The file is an "Other File" in the Project Navigator - if I "Remove this File from Project" the warning is generated at the next time compiling the project and the the file is in the list "Other Files" again. What does this warning mean? Should I do anything? Thanks, ManfredArticle: 71262
hmurray@suespammers.org (Hal Murray) wrote in message news:<P5idnUTP6qa7023d4p2dnA@megapath.net>... > >If your input clock (to the FPGA) is connected to an IBUFG (a clock-capable > >IOB), then to a DLL or DCM, then to a BUFG (with the output of the BUFG > >connected to the DLL/DCM's feedback port), then the edges of your input > >clock will be coincident with the clock edges on the FPGA's internal clock > >net (i.e., the output of the BUFG). This is known as "de-skewing" an input > >clock. This clock net can be used to clock the IOB registers -- and when you > >do this, the timing relationship, at the IOB's register input, is known with > >respect to your external clock. This is critical when your data rate is > >fairly high. > > Good point. Thanks. > > Note that any delay in the clock distribution turns into hold time > requirements at the input to the IOB. Hold times are evil. They > hurt even if the clock is not running fast. > > Older Xilinx chips had a delay in the IOB that was long enough > to cover that hold time, and an option to bypass it in order > to reduce the setup time. Thanks all for you Inputs. Regards, Muthu SArticle: 71263
Hello, Even the 2:1 Mux has static hazard if we consider all the gates are unit delay elements. Hence do we need to do special RTL coding to avoid those? OR Synthesis tools are intelligent enough to add the extra logics (Similar to K-Map manual analysis) to avoid Hazard. Thanks in advance. Regards, Muthu SArticle: 71264
To all,
With the help of some of the newsgroup members (thanks alot) I
have been able to generate a sopc design with a user-defined master
with the Micron SDRAM controller using the library functions in SOPC
Builder. After I generated the system and download it to the FPGA on
a 1s10 Development Kit evaluation board, I realized that I was not
able to read/write to the memory. When I probed the evaluation board
which has a fan-out clock buffer, there was no clock feeding the
SDRAM. The fan-out buffer has 2 inputs, one coming from the on-board
50 MHz oscillator and the other coming from the FPGA. The second
output is what is tied to the SDRAM. This allows the FPGA to generate
a higher clock rate for the SDRAM. The problem is that when the
evaluation board is powered-up, I can actively see a clock signal at
the output of the FPGA. This is because on boot-up the Flash contains
the SAFE mode program running a webserver client. However, when I
download my program, the FPGA line seems to go low or into tri-state
and there is no clock generated. Can anyone help me resolve how to
enable this output line on the FPGA to retain it's clock?
Regards,
Pino
Article: 71265Thanks Shalin. Do you have by any chance a practical example of a similar memory configuration showing how to multiplex the control pins of the 2 controllers? I am in the board level design stage with this project and I need to define the FPGA pinout before plunging deep into studying the cores. /Mikhail "Shalin Sheth" <Shalin.Sheth@xilinx.com> wrote in message news:40F3D34E.6020706@xilinx.com... > Mikhail, > > When interfacing external memories with Microblaze you want to use the > memory controllers includes in the Embedded Development Kit (EDK) and > not the Logicores. > > For the SDRAM interface you want to use the OPB_SDRAM controller. > For the SBSRAM interface you want to use the OPB_EMC controller. > For the FLASH interface you want to use the OPB_EMC controller. > > Both of these cores are supported for Spartan-3 in the latest EDK 6.2 > service pack 2 release. > > Shalin- >Article: 71266
Hi Manfred,
This warning means that Quartus is unable to read the mif file, and
therefore your ROM will not be initialized. I suspect it is the relative
path that begins with ../ that is causing the problem, or the double
extension(.rtl.mif) in the file name. If you are using a Megawizard to
create the ROM, first specify a fully resolved path to the mif file. An
example of such a path would be d:\bar\foo.mif I am assuming that you have
created the mif file, and that it is not autogenerated.
If that does not work email me the piece of VHDL code that generates this
ROM and we will be able to help you out.
- Subroto Datta
Altera Corp.
"Manfred Balik" <e8825130@stud4.tuwien.ac.at> wrote in message
news:40f3e342$0$29350$3b214f66@tunews.univie.ac.at...
> I allways get the Quartus Warning:
>
> Warning: Can't find design file .../projectname0.rtl.mif
>
> I found out, this file is from a large Constant in my VHDL-Code which
> generates a ROM.
> The file is an "Other File" in the Project Navigator - if I "Remove this
> File from Project" the warning is generated at the next time compiling the
> project and the the file is in the list "Other Files" again.
>
> What does this warning mean?
> Should I do anything?
>
> Thanks, Manfred
>
>
Article: 71267
Martin Thompson wrote:
> Ahh, I may have missed the fact you were using the Quartus simulator -
> that may or may not be VHDL-compliant in its usage of these symbols -
> my comments were aimed purely from the VHDl point of view.
The Quartus simulator uses waveforms on the netlist.
It can't handle any HDL.
-- Mike Treseler
Article: 71268Hi, does anybody know if the Virtex 4 family still has some dynamic partial reconfiguration capability? I haven't found this information on their website :( AndreasArticle: 71269
I have now implemented the protection against race condition as a result of asynchronous reset, as proposed by Phil and others. The machine hasn't locked after that, so hopefully that was the solution. I learnt a lot through this discussion. Thanks a lot to all who contributed! /JerkerArticle: 71270
Andreas, V4 has the ICAP (internal configuration access port) that has been in since Virtex II. V4 also has some other reconfiguration features, but those will have to wait until characterization is complete to be disclosed. Austin Andreas Sch. wrote: > Hi, > > does anybody know if the Virtex 4 family > still has some dynamic partial reconfiguration > capability? I haven't found this information > on their website :( > > AndreasArticle: 71271
Hello Rajeev, My apologies for not asking you first whether you were using the builtin Quartus II simulator or an external simulator. The Quartus II simulator in versions 4.1 and earlier ignores 'X' events on the select signal of a mux. This is a bug and will be fixed in Quartus II 4.2. To work around this problem you wil need to do a timing (aka post-layout simulation). The post-layout netlist is written using VHDL and Verilog library models which support the 'X' behavior correctly. You will need access to a VHDL/Verilog simulator like the Modelsim or NC-Sim among others. - Subroto Datta Altera Corp.Article: 71272
Austin Lesea wrote: > V4 has the ICAP (internal configuration access port) that has been in > since Virtex II. > > V4 also has some other reconfiguration features, but those will have > to wait until characterization is complete to be disclosed. Approximately when do you expect that we will be able to read the sort of technical detail that appeals to this newsgroup? After the summer holidays? Early next year? Late next year? Would Halloween be appropriate?Article: 71273
Hi, I've used PLX in the past. They are quite good for support and tools. Yes, you need some configuration tools to set up the registers, handshaking, etc. Regards, Luc On 11 Jul 2004 14:11:18 -0700, fpgadev@yahoo.com (AndyAtHome) wrote: >Hi All, > >I'm need to interface a Xilinx Virtex to a PCI Bus. The Xilinx PCI IP >core is too costly for the volumes I will be building, so I'm looking >at PCI controller chips. > >From experience can anybody recommend a vendor, such as Quicklogic, >AMCC, Tundra, etc. > >Thanks, > >Andy.Article: 71274
johnjakson@yahoo.com (john jakson) wrote in message news:<adb3971c.0407010714.565d691f@posting.google.com>... > Sounds suspiciously like credit card sz of which armoid comes to mind. > > http://armoid.com/store/catalog/product_info.php?products_id=28&osCsid=4f58554bddd3dd7b0e86fd94df0b2808 That's close to what I need, but it is still a bit too large unfortunately. The area I need is actually about 1/4th that of a credit card. > I have seen a no of weeny size boards but can't recall where, the low > cost guys often have little formats > > xess, burch, etc > > http://www.fpga-faq.com/FPGA_Boards.shtml Yeah, I had gone through every board within my price range on that page... none of them were small enough. The only ones I've seen so far within the dimensions I require were the UC1394a series of PLCCs by Traquair. http://www.traquair.com/catalog/ultracompact.products.html Definately the right size, even with more features than I need, but I was unable to find any kind of pricing on it. -DAG
Site Home Archive Home FAQ Home How to search the Archive How to Navigate the Archive
Compare FPGA features and resources
Threads starting:
Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z