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In article <40f3b85c@news.starhub.net.sg>, Kelvin <student@nowhere.com> wrote: >Got any Verilog parser? > Check out Icarus Verilog: http://www.icarus.com/eda/verilog/ PhilArticle: 71276
steven derrien <steven_derrien@yahoo.fr> wrote in message news:<ccu7n3$acg$1@python.ifsic.univ-rennes1.fr>... > Hi, > > Has anybody been trying to use gprof within the NIOS II IDE ? > We have some problems regarding the profiling data that is > send through the jtag interface directly to the IDE console window. > > We had a look to the documentation but there is little information > regarding the use of the profiler with the NIOS II. > > It seems that, to the difference of NIOS I, the profiling data > is sent as binary data, resulting in the following stdout trace : > > < Here the program standard output > > **gmon.out data follows** > < non readable binary data > > nios2-terminal: exiting due to ^D on remote > > Does anybody knows how to solve this issue ? > > Thank you in advance, > > Steven Hi Steven, Here are the basic steps to using GPROF in Nios II: (In the IDE): 1. Add a compiler switch, "-pg", for your src code project (in the C/C++ build area of the project properties). This is standard fare for using GPROF regardless of processor. 2. Add the same "-pg" switch for the compiler in your system library project. 3. Check the "use profiling library" checkbox in syslib properties. (From the SDK Shell): 4. Run your program: Use nios2-terminal's "--gmon" switch which will automatically capture the profiling data into a 'gmon.out' file after your program finishes execution. This has to be done from the command line, not the IDE. Note: nios2-terminal must be started with the processor in a paused state. You can do this by opening two SDK shell windows, downloading your program using "nios2-download <elf file>" (which downloads your code and leaves the processor paused), then running "nios2-terminal --gmon" in the second window, and finally running "nios2-download -g" in the first to start execution. More notes: Your application must return from main() because the profiling library's data dump is triggered by reaching atexit(). Also, the above notes assume that you're using the JTAG UART for STDIO; for the conventional UART we cannot support GPROF with the above flow just yet (this is scheduled for the next release) 5. Place the "gmon.out" file (generated in step 4) into the same dir as your .elf file 6. Run nios2-elf-gprof <elf file name> gmon.out > <output file name> 7. Examine the output file for results. The above flow was actually easier than I had expected given my GPROF experience with other processors :) However, I am sending an enhancement request to our engineering team to make the above flow all happen from within the IDE so that the SDK shell business isn't necessary. Also, I'll see to it that this is looked at for a relevant app note when the time comes; in addition to GPROF there is a performance counter peripheral (which is documented in the Nios II kit) which is useful for profiling sections of code -- such an app note will likely describe the use of both tools. Jesse Kempa Altera Corp. jkempa at altera dot comArticle: 71277
Joseph H Allen wrote: > > Do any placement algorithms try to make regular structures? For datapaths, > for example? This is how a human would do it, and might give excellent > results in some cases. Joseph, I'm no expert in the area, but seem to recall seeing this. Look up the authors of C compilers for Garp, I think one of them works on a fast linear placement algorithm. It might be from arraying bit slices. I expect the granularity of one's slice to be highly dependent on the target platforms array architecture. > Although, you certainly want to architect FPGAs with enough routing > resources so that regular structures are not needed. That's the constant balance, it seems. Deciding ow to focused to make your application domain, which determines the suite of applications (and kinds of operations) you need to support, which helps you avoid excessive flexibility in the array architecture. It's pretty vague, but it seems to be the general motivation for reconfigurable logic. Fred -- Fred Ma Dept. of Electronics, Carleton University Ottawa, Ontario, CanadaArticle: 71278
paul_sereno@hotmail.com (Paul Sereno) wrote in message news:<3d7510b4.0407021019.c3a5df5@posting.google.com>... > I am just wandering if any of you have take a look at the Lattice > FPGAs. I do like the DSP functions. > is out there any serious comparation against SpartanIII and Cyclone? The local Lattice FAE gave us the low-down. Looks like a decent set of chips. One thing we REALLY liked is that if you go with the devices that use an external configuration EPROM (rather than the family with the internal config flash), you can use a standard (read: CHEAP) SPI device, rather than a non-cheap specific config chip. I've always wondered why Brand A and Brand X continue to use their expensive config parts. Actually, that's not true -- I know why. Seriously, what's the point of using a $10 FPGA when the config EPROM is also $10? -aArticle: 71279
Hi, still sticked in the sdram controller project. I use a micron 256mb sdram following is its datasheet and simulation module's web address : http://www.micron.com/products/DRAM/SDRAM/part.aspx?part=MT48LC16M16A2TG I now want to know whether a read or write successful or not. Can someone tell me which array of variable in micron's simulation module I should put in the "watch" ? The micron module is quite complicated. I have problem now to get the timing right. Of course I know if I cannot read the thing I write, it is wrong, problem is that maybe the read has a bad timing too. So I need to see the internal content. I use vhdl module. Thanks StevenArticle: 71280
Hey Tim, Give the bloke a break, mate! If you jump down his throat every time he tries to give us a lead, he's gonna stop posting. Why not use the titbit like I intend to? Start hassling your FAE for some more info under NDA. Cheers, Syms. "Tim" <tim@rockylogic.com.nooospam.com> wrote in message news:cd16ka$ai0$1$830fa795@news.demon.co.uk... > Austin Lesea wrote: > > > V4 has the ICAP (internal configuration access port) that has been in > > since Virtex II. > > > > V4 also has some other reconfiguration features, but those will have > > to wait until characterization is complete to be disclosed. > > Approximately when do you expect that we will be able to read > the sort of technical detail that appeals to this newsgroup? > > After the summer holidays? Early next year? Late next year? > > Would Halloween be appropriate? > >Article: 71281
How about trying a post P&R simulation? Cheers, Syms. "Kevin White" <kevinjwhite@comcast.net> wrote in message news:a8425c6f.0407102012.202d7bac@posting.google.com... > Hi, > > Has anybody managed to get the C16 processor from opencores.org to > function correctly? > > I am trying to use it with a Digilent board with a Spartan IIe > XC2S300E and Xilinx tools version 6.2.03i. > > The code required modification to port it to this board and it > simulates fine with Modelsim but when the code executes it ignores > even simple instructions such as JUMP. The program counter just keeps > incrementing. I can see that the instructions are in memory OK. Its > as if the Xilinx tools are not synthesizing the VHDL correctly. > > Any hints will be welcome. > > thanks > > KevinArticle: 71282
Steven wrote: > Hi, > > I now want to know whether a read or write successful or not. Can > someone tell me which array of variable in micron's simulation module > I should put in the "watch" ? The micron module is quite complicated. > I have problem now to get the timing right. Of course I know if I > cannot read the thing I write, it is wrong, problem is that maybe the > read has a bad timing too. So I need to see the internal content. > > I use vhdl module. That should be easy to determine from the source code. The data is stored in the variables Bank0-3. But if you can cosimulate with Verilog, I would suggest using the Verilog model. It is more up to date, though judging by the change log the changes are relatively minor. But a big advantage is that it prints out reads and writes, including the address and contents. Though in some situations that might be considered a disadvantage. -- My real email is akamail.com@dclark (or something like that).Article: 71283
Symon wrote: > Hey Tim, > Give the bloke a break, mate! If you jump down his throat every time > he tries to give us a lead, he's gonna stop posting. Why not use the > titbit like I intend to? Start hassling your FAE for some more info > under NDA. Well, it was an innocent inquiry. And AL will pass if he can't say anything. As soon as one speaks to an FAE the whole sales thing starts. Sometimes product planning has to be approached by searching for an intersection between the customers' unlimited wants and the technology which is available at the price point. Browsing the data is the first step, long before a posssible order is on the radar.Article: 71284
"Andy Peters" <Bassman59a@yahoo.com> wrote in message news:9a2c3a75.0407131029.137e7596@posting.google.com... > paul_sereno@hotmail.com (Paul Sereno) wrote in message news:<3d7510b4.0407021019.c3a5df5@posting.google.com>... > > I am just wandering if any of you have take a look at the Lattice > > FPGAs. I do like the DSP functions. > > is out there any serious comparation against SpartanIII and Cyclone? > > The local Lattice FAE gave us the low-down. Looks like a decent set > of chips. > > One thing we REALLY liked is that if you go with the devices that use > an external configuration EPROM (rather than the family with the > internal config flash), you can use a standard (read: CHEAP) SPI > device, rather than a non-cheap specific config chip. > > I've always wondered why Brand A and Brand X continue to use their > expensive config parts. Actually, that's not true -- I know why. > Seriously, what's the point of using a $10 FPGA when the config EPROM > is also $10? Altera has addressed this problem with the Cyclone family - the configuration devices are quite cheap. LeonArticle: 71285
Andy Peters <Bassman59a@yahoo.com> wrote: : paul_sereno@hotmail.com (Paul Sereno) wrote in message news:<3d7510b4.0407021019.c3a5df5@posting.google.com>... : > I am just wandering if any of you have take a look at the Lattice : > FPGAs. I do like the DSP functions. : > is out there any serious comparation against SpartanIII and Cyclone? : The local Lattice FAE gave us the low-down. Looks like a decent set : of chips. : One thing we REALLY liked is that if you go with the devices that use : an external configuration EPROM (rather than the family with the : internal config flash), you can use a standard (read: CHEAP) SPI : device, rather than a non-cheap specific config chip. : I've always wondered why Brand A and Brand X continue to use their : expensive config parts. Actually, that's not true -- I know why. : Seriously, what's the point of using a $10 FPGA when the config EPROM : is also $10? X tries to come up with the XCF Series, also the XCF has still delivery problems. Bye -- Uwe Bonnes bon@elektron.ikp.physik.tu-darmstadt.de Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt --------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------Article: 71286
Johan Bernspång <xjohbex@xfoix.se> wrote in message news:<ccjddj$39r$1@mercur.foi.se>... > Hi all, > > What would be the optimal way, in terms of device utilization and > functionality, to exstend the length of the time a signal is asserted > from one clock cycle to four clock cycles. I.e. > [pseduo code:] > if signal a is asserted then > signal b is asserted for four clk; > > Is it possible to accomplish the function by utilizing an SRL16, or is > there a better solution? Or should I simply create four delayed versions > > of signal a, and OR them together to form signal b? > > I'm working with a Virtex-2 device. > > regards I have used a 3-bit synchronous loadable counter for this task. MSB is high for 4 ticks, and serves both as count-enable and output. You can count either up or down. This uses 3 registers. With 2 registers you could count 0,1,2,3,0=stop, output would be OR of both registers and the input. Now an SRL16 can be 16 registers, so as you say perhaps there is a clever solution with this... -rajeev-Article: 71287
A Xilinx App Note was suggested. Here is an attempt. Let me know if it makes sense. Beware of Start-Up Synchronization Errors Peter Alfke, July 12, 2004 All Xilinx FPGAs provide global (p)reset to all internal flip-flops and latches, which means that every flip-flop is either set or cleared (configuration option) when the FPGA goes active after configuration has been completed. This attractive feature requires no general routing resources. It is ³for free², but like with many ³free² offers, there can be strange side effects. € The (p)reset signal is distributed across the whole chip, and it is not very fast. Tens of nanoseconds delay are common on large chips. € The (p)reset signal is synchronous with either CCLK or, better, with the user clock, but there may be more than one user clock. € The user clock is normally running while the FPGA is being configured. This is only tolerable because flip-flops are being held (p)reset, nodes are forced High, and outputs are being held inactive, as described in the configuration documentation. These three features combined can cause unreliable start-up after configuration, when the trailing edge of the asynchronous (p)reset signal has so much skew or uncertainty with respect to any flip-flop clock, that some flip-flops can begin operating on different clock cycles. This might lead to an irrelevant start-up glitch, but it might also cause a state machine to enter an illegal state, or even to freeze up. There are several alternate solutions to this problem. 1. Disable all clocking until about 100 ns after the end of GSR, the automatic global signal that asynchronously (p)resets all flip-flops. 2. Distribute a synchronous CE (clock disable) signal with a tight distribution delay of less than one clock period. 3. Analyze the design for sensitive circuitry, e.g. state machines, and create a localized synchronous CE signal that delays operation for several clock cycles after the end of GSR. A convenient reset synchronizer and stretcher consists of a flip-flop with the usual GSR reset, with a High on its D input, and with its Q output driving the SRL16 input to its own LUT. The SRL16 output then goes High a controlled number of clock pulses after the end of GSR. This is a good signal to use for driving the CE input of critical state machines. Ken Chapman published a longer and more entertaining description in TechXclusives. Click on this insanely long URL: http://support.xilinx.com/xlnx/xweb/xil_tx_display.jsp?sGlobalNavPick=&sSeco ndaryNavPick=&category=&iLanguageID=1&multPartNum=1&sTechX_ID=kc_smart_reset Peter Alfke > From: "Jerker Hammarberg \(DST\)" <jerkerNO@SPAMdst.se> > Organization: DST Control AB > Newsgroups: comp.arch.fpga,comp.lang.vhdl > Date: Tue, 13 Jul 2004 18:14:14 +0200 > Subject: Re: FSM in illegal state (conclusion) > > I have now implemented the protection against race condition as a result of > asynchronous reset, as proposed by Phil and others. The machine hasn't > locked after that, so hopefully that was the solution. > > I learnt a lot through this discussion. Thanks a lot to all who contributed! > > /Jerker > >Article: 71288
As far as I could discover, this is still a propriatary device, and therefore you could not use a standard SPI flash instead. If no competition (read pin/pin compatible replacement) is possible, Altera could keep up the price as high as they want. With standard SPI flash, I have the choice of at least 5 different suppliers, no potentialy delivery problems, and guaranteed lowest price. Thus driving the total solution cost to a minimum. Luc On Tue, 13 Jul 2004 20:52:44 +0100, "Leon Heller" <leon_heller@hotmail.com> wrote: >"Andy Peters" <Bassman59a@yahoo.com> wrote in message >news:9a2c3a75.0407131029.137e7596@posting.google.com... >> paul_sereno@hotmail.com (Paul Sereno) wrote in message >news:<3d7510b4.0407021019.c3a5df5@posting.google.com>... >> > I am just wandering if any of you have take a look at the Lattice >> > FPGAs. I do like the DSP functions. >> > is out there any serious comparation against SpartanIII and Cyclone? >> >> The local Lattice FAE gave us the low-down. Looks like a decent set >> of chips. >> >> One thing we REALLY liked is that if you go with the devices that use >> an external configuration EPROM (rather than the family with the >> internal config flash), you can use a standard (read: CHEAP) SPI >> device, rather than a non-cheap specific config chip. >> >> I've always wondered why Brand A and Brand X continue to use their >> expensive config parts. Actually, that's not true -- I know why. >> Seriously, what's the point of using a $10 FPGA when the config EPROM >> is also $10? > >Altera has addressed this problem with the Cyclone family - the >configuration devices are quite cheap. > >Leon >Article: 71289
You'll need to provide more details as to how you set up the memory as
well as the filter. If the sample rate is one clock per sample, then it
is not really appropriate to use the memory because you are using only one
location per memory (and wasting the rest).
What is the ratio of your data rate to the clock?
How many taps is your filter?
Wilhelm Klink wrote:
> I've got an FIR design that runs out of FPGA memory in an ep1s60 when
> I set the data width to 24-bit (The design fits with a data width of
> 16-bit). However only 13% of the total memory is used. I assume the
> problem is that I have lots of smaller memories, and they cannot share
> the same memory blocks (M512, M4K, M-RAM). Can anyone who has
> experienced this problem share their strategies for dealing with this.
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 71290Pino, Do you have your PLL external output clock tied to the SDRAM clock pin? (plus all the other sdram pins?) Did you start with an example like "Thrifty" etc.? Ken "Pino" <pinod01@sympatico.ca> wrote in message news:b7ed9648.0407130601.6c8fae00@posting.google.com... > To all, > > With the help of some of the newsgroup members (thanks alot) I > have been able to generate a sopc design with a user-defined master > with the Micron SDRAM controller using the library functions in SOPC > Builder. After I generated the system and download it to the FPGA on > a 1s10 Development Kit evaluation board, I realized that I was not > able to read/write to the memory. When I probed the evaluation board > which has a fan-out clock buffer, there was no clock feeding the > SDRAM. The fan-out buffer has 2 inputs, one coming from the on-board > 50 MHz oscillator and the other coming from the FPGA. The second > output is what is tied to the SDRAM. This allows the FPGA to generate > a higher clock rate for the SDRAM. The problem is that when the > evaluation board is powered-up, I can actively see a clock signal at > the output of the FPGA. This is because on boot-up the Flash contains > the SAFE mode program running a webserver client. However, when I > download my program, the FPGA line seems to go low or into tri-state > and there is no clock generated. Can anyone help me resolve how to > enable this output line on the FPGA to retain it's clock? > > Regards, > PinoArticle: 71291
Hey all, I have a synchronus reset signal that has a very large fanout. Is it advisable to put this signal on a bufg? Thanks MattArticle: 71292
Peter,
Since the Xilinx parts have internal POR, it seems a
shame not to use it. However, since GSR is slow, we
are cautioned against using it due to problems like
these.
Is there a way to connect the output of GSR to the
input of the circuit that Ken Chapman suggested in
the section "Strategy for the 0.01% of cases" of his
TechXclusive and leave off the asynchronous reset input.
Would this be a way that I can effectively cause all of
resets (or critical resets) for a clock domain to be
deasserted at the same time without having to
have a redundant external POR?
If this is possible, is there a VHDL coding methodology
that you can recommend? The big missing piece for me
is how do I access the output of GSR?
#1: Explicitly through instantiation?
#2: Implicitly through initializing the VHDL
signals that create the registers?
Although this technique seems possible in XST,
would it also work the same in other synthesis tools?
#3: Put the reset logic in a separate hierarchical
block and explicitly code an asynchronous reset, but
at the next level of the design tie the asynchronous
reset to a constant inactive value?
If I have multiple FPGAs and they are all connected
in a serial fashion for configuration, is the internal
POR released at approximately the same time?
The details of POR and GSR functionality has always been a
little troubling to me, is there a good (really detailed)
application note that you can recommend.
Regards,
Jim Lewis
SynthWorks VHDL Training
> Ken Chapman published a longer and more entertaining description in
> TechXclusives.
> Click on this insanely long URL:
>
> http://support.xilinx.com/xlnx/xweb/xil_tx_display.jsp?sGlobalNavPick=&sSeco
> ndaryNavPick=&category=&iLanguageID=1&multPartNum=1&sTechX_ID=kc_smart_reset
> A Xilinx App Note was suggested. Here is an attempt.
> Let me know if it makes sense.
>
> Beware of Start-Up Synchronization Errors
> Peter Alfke, July 12, 2004
>
> All Xilinx FPGAs provide global (p)reset to all internal flip-flops and
> latches, which means that every flip-flop is either set or cleared
> (configuration option) when the FPGA goes active after configuration has
> been completed. This attractive feature requires no general routing
> resources. It is ³for free², but like with many ³free² offers, there can be
> strange side effects.
>
> € The (p)reset signal is distributed across the whole chip, and it is not
> very fast. Tens of nanoseconds delay are common on large chips.
> € The (p)reset signal is synchronous with either CCLK or, better, with the
> user clock, but there may be more than one user clock.
> € The user clock is normally running while the FPGA is being configured.
> This is only tolerable because flip-flops are being held (p)reset, nodes are
> forced High, and outputs are being held inactive, as described in the
> configuration documentation.
>
> These three features combined can cause unreliable start-up after
> configuration, when the trailing edge of the asynchronous (p)reset signal
> has so much skew or uncertainty with respect to any flip-flop clock, that
> some flip-flops can begin operating on different clock cycles. This might
> lead to an irrelevant start-up glitch, but it might also cause a state
> machine to enter an illegal state, or even to freeze up.
>
> There are several alternate solutions to this problem.
>
> 1.
> Disable all clocking until about 100 ns after the end of GSR, the automatic
> global signal that asynchronously (p)resets all flip-flops.
>
> 2.
> Distribute a synchronous CE (clock disable) signal with a tight distribution
> delay of less than one clock period.
>
> 3.
> Analyze the design for sensitive circuitry, e.g. state machines, and create
> a localized synchronous CE signal that delays operation for several clock
> cycles after the end of GSR.
>
> A convenient reset synchronizer and stretcher consists of a flip-flop with
> the usual GSR reset, with a High on its D input, and with its Q output
> driving the SRL16 input to its own LUT. The SRL16 output then goes High a
> controlled number of clock pulses after the end of GSR. This is a good
> signal to use for driving the CE input of critical state machines.
>
> Ken Chapman published a longer and more entertaining description in
> TechXclusives.
> Click on this insanely long URL:
>
> http://support.xilinx.com/xlnx/xweb/xil_tx_display.jsp?sGlobalNavPick=&sSeco
> ndaryNavPick=&category=&iLanguageID=1&multPartNum=1&sTechX_ID=kc_smart_reset
>
>
> Peter Alfke
>
>
>
>
>
>
>>From: "Jerker Hammarberg \(DST\)" <jerkerNO@SPAMdst.se>
>>Organization: DST Control AB
>>Newsgroups: comp.arch.fpga,comp.lang.vhdl
>>Date: Tue, 13 Jul 2004 18:14:14 +0200
>>Subject: Re: FSM in illegal state (conclusion)
>>
>>I have now implemented the protection against race condition as a result of
>>asynchronous reset, as proposed by Phil and others. The machine hasn't
>>locked after that, so hopefully that was the solution.
>>
>>I learnt a lot through this discussion. Thanks a lot to all who contributed!
>>
>>/Jerker
>>
>>
>
>
Article: 71293Let me calm down the waves: There was a press release that we have Vitex-4 parts. So you can be sure that we are very busy testing and verifying the design, functionality and performance. We know these parts inside and out, but we are not gonna tell. Formal public announcement of technical details and availability is being orchestrated by Marketing. There are many aspects: Too early, and you designers complain about lack of availability. Too late, and we lose a design-in window and thus share of market. The technical press needs some lead-time, and we have to prepare, revise, polish and distribute many hundreds of pages of technical documentation. (I am involved in that). The official release will be a big event, and nobody should underestimate the amount of coordinated effort, and the need for keeping the details under wraps until then. Don't forget that there is at least one competitor just waiting to exploit the smallest of missteps. We don't want to give him any ammunition. But we also want to keep the user community excited and happy. So, we will release the information "when the time is right". Stay tuned! Peter Alfke > From: "Tim" <tim@rockylogic.com.nooospam.com> > Newsgroups: comp.arch.fpga > Date: Tue, 13 Jul 2004 20:35:44 +0100 > Subject: Re: Xilinx Virtex 4 > > Symon wrote: >> Hey Tim, >> Give the bloke a break, mate! If you jump down his throat every time >> he tries to give us a lead, he's gonna stop posting. Why not use the >> titbit like I intend to? Start hassling your FAE for some more info >> under NDA. > > Well, it was an innocent inquiry. And AL will pass if he > can't say anything. > > As soon as one speaks to an FAE the whole sales thing > starts. Sometimes product planning has to be approached > by searching for an intersection between the customers' > unlimited wants and the technology which is available > at the price point. Browsing the data is the first step, > long before a posssible order is on the radar. > >Article: 71294
I guess the combination of Wincupl and a 16V8 will be pretty much steam
technology for most of you but it is a real mystery to me.
I blew up some 16V8 stepper sequencers the other day and I have to
program up some replacements. All I have is some software to program the
ATF16V8B chips and wincupl.
This is my first try at this game but I have the state machine working
after many hours of searching and puzzling and it behaves the same as
the original chips. BUT...
The driver board has an enable input which should turn off the motors.
In the current design, that is done by setting the outputs all high when
ENABLE is active. unfortunately, this only happens if a clock pulse is
applied as (I suppose) it has to get clocked through the output registers.
Is there a way to make the ENABLE input force the outputs to a
predetermined state with or without a clock pulse?
I would also be grateful for any other assistance you could give.
Here is the CUPL file as it stands:
Name JSMOTOR ;
PartNo 00 ;
Date 13/07/2004 ;
Revision 01 ;
Designer Engineer ;
Company Helicron ;
Assembly None ;
Location ;
Device g16v8a ;
/** Inputs **/
Pin 1 = clk ;
Pin 2 = DIR;
Pin 3 = ENA ;
Pin 9 = FULL;
pin 11 = !OE;
/** Outputs **/
Pin [12..15] = [Q3..0]; /** **/
field stpctrl = [Q3..0];
$Define S0 'b'0000
$Define S1 'b'1000
$Define S2 'b'1010
$Define S3 'b'0010
$Define S4 'b'0110
$Define S5 'b'0100
$Define S6 'b'0101
$Define S7 'b'0001
$Define S8 'b'1001
$Define S9 'b'1111
field mode = [ENA,FULL,DIR];
up = mode:7;
hup = mode:5;
down = mode:6;
hdown = mode:4;
clear = mode:[0,1,2,3];
Sequence stpctrl {
present S9
if up next S2;
if down next S2;
if hup next S1;
if hdown next S1;
present S0
if up next S2;
if down next S2;
if hup next S1;
if hdown next S1;
present S1
if up next S2;
if down next S8;
if hup next S2;
if hdown next S8;
present S2
if up next S4;
if down next S8;
if hup next S3;
if hdown next S1;
present S3
if up next S4;
if down next S2;
if hup next S4;
if hdown next S2;
present S4
if up next S6;
if down next S2;
if hup next S5;
if hdown next S3;
present S5
if up next S6;
if down next S4;
if hup next S6;
if hdown next S4;
present S6
if up next S8;
if down next S4;
if hup next S7;
if hdown next S5;
present S7
if up next S8;
if down next S6;
if hup next S8;
if hdown next S6;
present S8
if up next S2;
if down next S6;
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Pete Harrison
http://micromouse.cannock.ac.uk/
Article: 71295>Is there a way to make the ENABLE input force the outputs to a >predetermined state with or without a clock pulse? Use it as a tri-state enable? Needs external pull ups or downs. -- The suespammers.org mail server is located in California. So are all my other mailboxes. Please do not send unsolicited bulk e-mail or unsolicited commercial e-mail to my suespammers.org address or any of my other addresses. These are my opinions, not necessarily my employer's. I hate spam.Article: 71296
hello am an mcu developper on 8051 . never use xilinx fpga wana build an application and i don't know if an fpga is the best for my product i try to have the more low cost and "more compact" but i can't compare (not enought information)! My application request: low cost for end user (i wana put my application freely on the net (i can program for the end user the chip if they don't have the programmer) and make the pcb ) litle description : usb chip bluetooth chip can use usb and bluethoot uart (usb always on in order to fix bluetooth : on/off adress....) insitu mcu 2v7 with : -23 adc low resolution 8/10 bit (200 sample/s) -6 adc high resolution 12/16 bit (200 to 400 sample/s) -1 temp sensor (compensate captor) in my application my mcu read adc and make 3 array one low resolution ; one high resolution before compensate & one array after compensate . got some calcul in order to correct the value of the high resolution array (the captor must be compensate). load the 2 array on request on my computer . my questions: does the xilinx low cost fpga from your point of view can be a solution for this application and wich one ? or i must stay on my mcu solution ? how does bluetooth and usb are implemented on fpga (insitus on special fpga or addon with other chip) ? think this apllication could be a good reason for me to try fpga and learn more about it ! thanks for your help y.sudrie from france :)Article: 71297
On Wed, 14 Jul 2004 00:29:38 GMT, Pete Harrison <peter_harrison@ntlworld.com> wrote: >I guess the combination of Wincupl and a 16V8 will be pretty much steam >technology for most of you but it is a real mystery to me. On the other hand, a 16V8 or 22V10 is often the perfect size. >I blew up some 16V8 stepper sequencers the other day and I have to >program up some replacements. All I have is some software to program the >ATF16V8B chips and wincupl. > >This is my first try at this game but I have the state machine working >after many hours of searching and puzzling and it behaves the same as >the original chips. BUT... > >The driver board has an enable input which should turn off the motors. >In the current design, that is done by setting the outputs all high when >ENABLE is active. unfortunately, this only happens if a clock pulse is >applied as (I suppose) it has to get clocked through the output registers. > >Is there a way to make the ENABLE input force the outputs to a >predetermined state with or without a clock pulse? You have your registers on four of the output pins. Route those values combinatorially to the remaining four outputs so that, for example, (if ENA reset is "motors off"; flip to !ENA if not so). pin [16..19] = Y[3..0]; ... Y0 = ENA & Q0; Y1 = ENA & Q1; Y2 = ENA & Q2; Y3 = ENA & Q3; (Is there a shorthand notation for that? My CUPL is a bit rusty.) If you're already wired to come off of 12..15, move the registered outputs up a nibble, of course. A disadvantage (or maybe an advantage) is that the registers don't change value if only ENA changes, so going back to the active state will restore the stepper bits to where they were (if no clk changes...). -- Rich Webb Norfolk, VAArticle: 71298
Matthew E Rosenthal wrote:
> Hey all,
> I have a synchronus reset signal that has a very large fanout.
> Is it advisable to put this signal on a bufg?
Howdy Matt,
Unfortunately, the global clock buffers are only usable for clocks on
Xilinx devices. Since it is synchronous, you might try letting the
tools chew on it (if you haven't already) with local routing and see
what timing results. If that is too painful, consider switching to the
GSR (there are safe and easy ways to use it).
Good luck,
Marc
Article: 71299Generally, if you can easily do it in a CPU that's probably cheaper. I didn't see anything in your description that looked like it would fit better on a FPGA than on a CPU. -- The suespammers.org mail server is located in California. So are all my other mailboxes. Please do not send unsolicited bulk e-mail or unsolicited commercial e-mail to my suespammers.org address or any of my other addresses. These are my opinions, not necessarily my employer's. I hate spam.
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