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jon@beniston.com (Jon Beniston) wrote in message news:<e87b9ce8.0405140056.23ca67ac@posting.google.com>... > > > Ok, maybe not that particular case, but most other configurations of > > > dual-port RAM can be infered. In Verilog at least, isn't this a > > > problem with the language rather than the FPGA tools (i.e. you can't > > > write to the same variable from two different processes)? > > > > Verilog does not have this restriction. I've searched the LRM and > > I've run testcases through two reputable implementations without > > complaints (ncverilog, icarus). > > You are correct. Although it is only ever supported for simulation. I > can kind of understand why though. Take the following: > > module test(c1, c2, a, b, d); > input c1, c2, a, b; > output d; > reg d; > always @(posedge c1) > d <= a; > always @(posedge c2) > d <= b; > endmodule > > What logic would you synthesize it to? Have you tried this with a > behavioural synthesis tool? Maybe that could do a better job. > > > Hence my frustration. We can precisely describe a dual port block-ram > > in Verilog, yet the tools draw a blank. We can even preset RAMs with > > values, but most, if not all, completely disregard initial statements. > > Isn't this fixed in v200x? I do agree it's all a bit crap. > > Cheers, > JonB BRams are a very special case since most of the time the 2 address are different so the 2 clock domains are fully independant. If the address should be the same then the result of the 2 concurrent writes is undefined but the user should have taken care about that. given that, the synthesis should be able to handle it with a warning for same addresses. regards johnjakson_usa_comArticle: 69601
Fred Ma wrote: > I'm actually not trying to model the ALU-like cell. I'm trying to > generate random netlist of those cells. However, a completely > random net list is not realistic. Ray Andraka wrote: > Why? Hi, Ray, Not sure if you remember, but we met (I think at FCCM) a few years back. Hope things are going well with you. Why am I trying to generate pseudorandom netlists? I'm testing out a placement algorithm for ALU arrays. Why is a random netlist not realistic? Designs usually have some kind of hierarchy (effective hierarchy, even if not explicit). I'm not an expert in this area, but I've looked at a few papers on graph clustering algorithms. Hierarchical information is often captured as a rooted tree, where each internal node represents a subgraph of the netlist with a somewhat minimal cutset (compared to an arbitrarcy cut at the same level of clustering). A truly random graph will probably not have the same degree of hierarchical structure. You can still force-feed it into a clustering algorthm to impose hierarchy, but the criteria for choosing subgraphs will probably not be that distinct between candidate subgraphs. Intuitively, I don't expect a totally random graph to be easily placable because there's too much random interdepedence between arbitrary nodes. A real netlist has more localization of interconnect. I'm currently looking through some papers on the topic of random graph generation by Hutton & Pistorius (upon their recommendation). However, they are meant for FPGAs, whereas the cell I mentioned in my original post is quite different. There are far fewer of them in a circuit, and there are many more inputs. I'm trying to get some guiding considerations to cobble my own quick-and-dirty code in matlab. Fred -- Fred Ma, fma@doe.carleton.ca Dept. of Electronics, Carleton University, Ottawa, Ontario, Canada *| If I don't reply to your email, please sent it again. I may |* *| have erased along with the deluge of post-filter spam. |*Article: 69602
Fred Ma wrote: > > Hierarchical information is often captured as > a rooted tree, where each internal node represents a subgraph of the > netlist with a somewhat minimal cutset (compared to an arbitrarcy cut > at the same level of clustering). A truly random graph will probably > not have the same degree of hierarchical structure. You can still > force-feed it into a clustering algorthm to impose hierarchy, but the > criteria for choosing subgraphs will probably not be that distinct > between candidate subgraphs. I just read what I wrote -- it's clear to someone who has seen it before, but confusing otherwise. The rooted tree is different from graph for the netlist. The tree just captures subsumption information (a parent node subsumes a child node, thus forming a more aggregate node, or "supernode"). If you travel down a path on the rooted tree, you are travelling deeper and deeper into the nested supernodes. When you reach the leaf nodes at the bottom of the tree, you reached the actual nodes in the circuit graph. The physical interconnect doesn't show up in the rooted tree at all. Actually, maybe that picture isn't so obscure. I think it might be commoon placed for graph partitioning algorithms. Fred -- Fred Ma, fma@doe.carleton.ca Dept. of Electronics, Carleton University, Ottawa, Ontario, Canada *| If I don't reply to your email, please sent it again. I may |* *| have erased along with the deluge of post-filter spam. |*Article: 69603
geoffrey wall <wallge@eng.fsu.edu> wrote in message news:<c82o6r$g2m$1@news.fsu.edu>... > Im looking to do some real-time video processing algorithms, > but i am mostly a software person... i need an fpga with good > development tools (not buggy) that will be easy to use for someone who > is learning how to program hdl and use the hardware for the first time. > Ideally i would like a powerful and flexible board with good development > tools, good tech support and documentation. Any suggestions? What ever you do, don't buy ANYTHING from Nu Horizons. Their customer service sucks! And they discontinue products with no notice.Article: 69604
"geoffrey wall" <wallge@eng.fsu.edu> wrote in message news:c82o6r$g2m$1@news.fsu.edu... > Im looking to do some real-time video processing algorithms, > but i am mostly a software person... i need an fpga with good > development tools (not buggy) that will be easy to use for someone who > is learning how to program hdl and use the hardware for the first time. > Ideally i would like a powerful and flexible board with good development > tools, good tech support and documentation. Any suggestions? > > thanks > A different question to ask is what is the budget for an fpga board ? And what size do you need ? For lower end boards take a look at www.digilentinc.com Have you guys had a look at the Anlog devices black fin boards ? http://www.analogdevices.com/Analog_Root/static/promotions/blackfin750/?CT=adi_webcastad2_homepage.gif http://www.analogdevices.com/processors/epProductPage/0,2542,BF533%252DHARDWARE,00.htm http://www.analogdevices.com/processors/epProductPage/0,2542,BF561%252DHARDWARE,00.htmArticle: 69605
Your best bet would be to get Lattice to send you a copy of ispDesign Expert V8.4 (ispDE V8.4) it will support isp1032-60 and isp1032E-70 devices, all the older devices. Request a license as well based on your C drive serial number. Go to a DOS prompt and type "C:\vol" and send the request to lic_admin@latticesemi.com along with old Lattice key ID (10 digit number). Try Lattice Tech Support. techsupport@latticesemi.com They should be able to help. The spawning problem I ran into a few years ago. If I remember correctly the pdsplus environment variable had spaces after the last character: pdsplus=C:\pdsplus\bin (do not have any spaces after the n in bin) this was in a really old version of the software V5.0 or older. Also no spaces where you install the software and no spaces in file names or directory names. If you can get the ispDE V8.4 to get to the older devices you will need to get that info from Lattice. Just let them know what you need. Hope this helps. --Coop Jim Granville <no.spam@designtools.co.nz> wrote in message news:<4R%oc.1958$FN.211542@news02.tsnz.net>... > Fabio G. wrote: > <snip> > > I looked in SYNDPM.exe with an HEX file viewer. > > I found some messages: > > > > LatticeStdioWinID LatticeAppQuit LatticeAppStart suspend continue > > terminate beat SYNDPM EXIT MESSAGE Syndpm Exiting %d > > PDS_SYNDPM_DEBUG SYNDPM DEBUG MESSAGE SYNDPM CLOSING APPLICATION > > SynDPM Closing Application %d, imm:%d SYNDPM abel_yield ended > > SYNDPM MESSAGE Syndpm break received %d %s SYNDPM abel_yield > > started Sent Heart Beat to Synario environment SYNDPM To Synario > > PDS_SYNDPM_HEARTMSG %s: Child process (%d) exited with status:%d. > > Wait Child *** Process is gone?... > > Child process ID = %d, is active. > > PDS_SYNDPM_CHILDPROC %s: Wait Child *** received child %d quit > > with status %d > > %s: Wait Child *** received child %d started. > > No response from LSC Compiler... > > Click cancel to abort returning from spawnvp. > > %s: Using Current Child Id (%d) instead of handle. > > %s: Child Proc %s ID -- %d > > Request to close syndpm received. Syndpm exiting with status %d > > %s > > %s > > ****HERE ******** Received process exit status -1 Possible system > > problem to spawn child process PDS_DPM_EXE SYNDPM LICENSE ERROR > > for the ispDS+ 5.1 compiler. > > FlexLM License file must be copied to the above location > > License file %s not found. > > Application Registered SYNDPM DEBUG ispDS+ rt PDS_SYNDPM_ARGS > > LATTICE_CONSOLE_ID=%u %s/bin/dpm.exe Environment Variable PDSPLUS > > is undefined. PDSPLUS=d:\pdsplus PDSPLUS=%s > > PATH=%s > > PATH=%s\bin;%s; PATH Cannot open current context SYNDPM CONTEXT > > Env License File Set License File > > LM_LICENSE_FILE=%s\license\license.dat PDS_LIC=%s PDSPLUS=%s > > LM_LICENSE_FILE=%s FOUND LM_LICENSE_FILE LM_LICENSE_FILE PDSLic > > PDS_LIC Failed to get PDSPLUS context string SYNARIO PDSPath ENV > > PDSPath SYNARIO PDSPLUS ENV PDS_SYNDPM_ENV PDSPLUS syndpm.log wt > > PDS_SYNDPM_LOG=1 c:\tmp\syndpm.log PDS_STDIO_DEBUG=1 > > c:\tmp\syndpm.sio PDS_SYNDPM_HEARTMSG=1 c:\tmp\syndpm.hbt > > PDS_SYNDPM_ENV=1 c:\tmp\syndpm.env PDS_SYNDPM_ARGS=1 > > c:\tmp\syndpm.arg PDS_SYNDPM_DIOMSG=1 c:\tmp\syndpm.msg > > PDS_SYNDPM_DEBUG=1 c:\tmp\syndpm.dbg PDS_SYNDPM_LOG SYNDPM > > TKOutputProcMsg Data String(%d): '%s' PDS_SYNDPM_DIOMSG Syndpm > > Terminate msg received %d OWNER_PROCESS CREATE COM WINDOW %s: > > Failed to Create Application's COM window. > > STDIO PROC %d laStdioCommClass > > Hmmm, sounds like this fitter uses the KEY and license scheme of a > certain release Synario, so you will need to have all that correctly > installed and setup. > > > Maybe with other changes I could find the solution, but I've already > > lost too much time: I'll try to use the alternative design flow chain. > > If the 'E' version fits, and you have a tool flow for that, sounds like > you are OK. > > -jgArticle: 69606
The plastic packages used in through hole technology were never subjected to the extreme temperatures of surface mounting. When a small amount of moisture is absorbed and then heated during surface mounting, the package can fracture or even explode when the moisture turns to steam. -- Greg readgc.invalid@hotmail.com.invalid (Remove the '.invalid' twice to send Email) "William H. Maddox III" <NOSPAMmaddox@NOSPAMtransmetaDOTCOM> wrote in message news:1084578360.741900@palladium.transmeta.com... > Plastic packages have been used for years, but it is only very recently > that I've heard of moisture absorption becoming big issue. Clearly, with > such dramatic effects on reliability, it can't be that we just were ignorant > of a long-standing problem. What is it about these parts that causes the > moisture sensitivity, or why has it become such an issue recently? > > --BillArticle: 69607
Hi, I know I should be posting this to Altera Support, but I am in a bit of a hurry and hoping someone on the grp could advise me in parallel. I get a Quartus internal error while it's doing a P&R. Has anyone seen this before?? Any workarounds? I see this on 2 different machines both with enough RAM(1GB). ---------------------------------------------------------------------------- Internal Error: Sub-system: CDB_ATOM, File: cdb_atom_netlist.cpp, Line: 1585 iter == m_created_from_map.end() (Fitter pre-processing) Quartus II Version 3.0 Build 245 10/09/2003 SJ Full Version Service Pack Installed: 2 --------------------------------------------------- Thanks & Regards TushitArticle: 69608
johnjakson@yahoo.com (john jakson) wrote in message news:<adb3971c.0405141717.7eea7369@posting.google.com>... > jon@beniston.com (Jon Beniston) wrote in message news:<e87b9ce8.0405140056.23ca67ac@posting.google.com>... > > > > Ok, maybe not that particular case, but most other configurations of > > > > dual-port RAM can be infered. In Verilog at least, isn't this a > > > > problem with the language rather than the FPGA tools (i.e. you can't > > > > write to the same variable from two different processes)? > > > > > > Verilog does not have this restriction. I've searched the LRM and > > > I've run testcases through two reputable implementations without > > > complaints (ncverilog, icarus). > > > > You are correct. Although it is only ever supported for simulation. I > > can kind of understand why though. Take the following: > > > > module test(c1, c2, a, b, d); > > input c1, c2, a, b; > > output d; > > reg d; > > always @(posedge c1) > > d <= a; > > always @(posedge c2) > > d <= b; > > endmodule > > > > What logic would you synthesize it to? Have you tried this with a > > behavioural synthesis tool? Maybe that could do a better job. > > > > > Hence my frustration. We can precisely describe a dual port block-ram > > > in Verilog, yet the tools draw a blank. We can even preset RAMs with > > > values, but most, if not all, completely disregard initial statements. > > > > Isn't this fixed in v200x? I do agree it's all a bit crap. > > > > Cheers, > > JonB > > BRams are a very special case since most of the time the 2 address are > different so the 2 clock domains are fully independant. If the address > should be the same then the result of the 2 concurrent writes is > undefined but the user should have taken care about that. given that, > the synthesis should be able to handle it with a warning for same > addresses. Sure, but it seemed like the OP was suggesting that synthesis tools should support everything possible in the language. Cheers, JonBArticle: 69609
Hi, I'm looking for a way to get or generate small netlists of high level cells to test a placement algorithm. I don't need timing or functional information about the netslist. I posted a description of this in the original thread. Many of the papers I've read refer to the MCNC testbenches at http://www.cbl.ncsu.edu. Many of the links on their benchmark page seem to be obsolete. In particular, most links that can provide background to navigate the site (and its various test suites) are no longer available. These include the technical reports, the Benchmark-review, and the ftp address. Is there some kind of guide information that helps visitors to the site choose a test suite? MCNC seems to be very prevalent, so I assume this "high-level view" information exists somewhere (maybe in the technical reports?). A paper I found that seemed like it might help is ACM/SIGDA Design Automation Benchmarks: Catalyst or Anathema Franc Brglez IEEE Design & Test of Computers (magazine) 10(3), Sept., 1993, pp. 87--91. Strangely, this paper seems to have disappeared from the web. It doesn't show up in that issue in IEEE Explore. Our library also has access to ACM, which merely points to the IEEE society website. There, a user login is needed to get the article. So despite my personally subscribing to D. and T., and the library having access to IEEE and ACM, I can't get it. Thanks for any pointers to where the technical reports might still be available. Or, if there is some kind of summary/overview that can help in determining which of the test suites to start looking at first, I'd appreciate a referral to that, too. How do other newcomers go about getting this "roadmap"? Fred -- Fred Ma, fma@doe.carleton.ca Dept. of Electronics, Carleton University, Ottawa, Ontario, Canada *| If I don't reply to your email, please sent it again. I may |* *| have erased along with the deluge of post-filter spam. |*Article: 69610
Fred Ma <fma@doe.carleton.ca> wrote in message news:<40A5873B.DC4721CA@doe.carleton.ca>... > Fred Ma wrote: snipping > Actually, maybe that picture isn't so obscure. I think it might be > commoon placed for graph partitioning algorithms. > > Fred Ok so you are doing P/R work, sort of guessed. Why not hand design a reasonable datapath with lots of options that can be parameterised. Atleast in verilog (& probably VHDL) you can 'define just like in C, and in verilog2000 use generate (VHDL does that too). With that, 1 good datapath can now spawn possibly 100s of variations small & large. For instance design a hierarchy of cells with specific ports. Now create alternates for a no of these, a good candidate would be the alu adder. You can have a dumb ripple adder, carry save added, carry lookahead and so on, all pin compatible but using wildy different amounts of logic, some regular & some not. If your datapath has half a dozen widgets, you could make 2,3 ^6 versions in no time and they would be plausible. We end up doing that anyway but chucking the slower ones along the way. You could do same in a toy meta HDL if you add a define or generate primitive to it. regards johnjakson_usa_comArticle: 69611
"William H. Maddox III" <NOSPAMmaddox@NOSPAMtransmetaDOTCOM> wrote in message news:<1084578360.741900@palladium.transmeta.com>... > Plastic packages have been used for years, but it is only very recently > that I've heard of moisture absorption becoming big issue. Clearly, with > such dramatic effects on reliability, it can't be that we just were ignorant > of a long-standing problem. What is it about these parts that causes the > moisture sensitivity, or why has it become such an issue recently? > > --Bill Actually its been an issue ever since plastic has been used atleast as far back as I know 25yrs+. ofcourse the plastics are not your typical "plastic" but are engineered to have the kinds of properties needed to house ICs. They need to resist moisture, need to be strong enough, and mustn't contain too much radioactive material, that was the big one that cought DRAM folks off gaurd 20yrs ago when the US found out how much better Japan was at packaging. Theres far more to it than that, google chip packaging etc to find more regards johnjakson_usa_comArticle: 69612
"Jon Beniston" <jon@beniston.com> wrote in message news:e87b9ce8.0405141709.5ef4798f@posting.google.com... > Roger Larsson <roger.larsson@skelleftea.mail.telia.com> wrote in message news:<HN7pc.59087$mU6.238562@newsb.telia.net>... > > Tom Hawkins wrote: > > > > > 2. With Confluence under GPL, I have yet to receive a single bug > > > report or source code contribution. > > > > > > > For some tools it can take a very long time to build a userbase. > > Step 1. You need to know about it. > > - I know about Confluence. > > Step 2. You need to have something suitable to try it with. > > - Maybe this summer... > > Step 3. It needs to be good enough. > > No idea... since I have not tried it yet. > > Step 4a. It needs to have bugs to give you bug reports :-) > > Step 4b. It needs to be incomplete to give you feature requests. > > Step 4c. It needs to be programmed in a language that your small > target audience have heard of! How many Verilog/VHDL coders also know > OCaml? C or Java and you might have a chance... > That's certainly a point when you are looking for code contributions, and for many open source projects it makes sense to consider that when choosing the language. But for something like Confluence, I don't think that Tom is looking for so much in the way of direct coding help at the moment - feedback and ideas are important, along with contributions to the library, examples and documentation (how many good Verilog/VHDL coders are also good at "normal" software development, especially something as specialised as implementing functional programming languages, regardless of the language?). I am a great supporter of choosing the right language (or right tool of any kind, for that matter) for the job - popularity might be one consideration, but it's not the only one. In fact, why would anyone be interested in confluence in the first place if they were not happy to consider new languages? The choice of ocaml makes a lot of sense here, actually - it is a functional programming language itself (with bits of imperitive language added - sort of the opposite of Python, but for the same reasons), so it matches the style of confluence programming well. It was actually top of my "languages to learn when I have the time" list, but confluence sneaked in on top...Article: 69613
john jakson wrote: > > Why not hand design a reasonable datapath with lots of options that > can be parameterised. > > Atleast in verilog (& probably VHDL) you can 'define just like in C, > and in verilog2000 use generate (VHDL does that too). > > With that, 1 good datapath can now spawn possibly 100s of variations > small & large. For instance design a hierarchy of cells with specific > ports. Now create alternates for a no of these, a good candidate would > be the alu adder. You can have a dumb ripple adder, carry save added, > carry lookahead and so on, all pin compatible but using wildy > different amounts of logic, some regular & some not. > > If your datapath has half a dozen widgets, you could make 2,3 ^6 > versions in no time and they would be plausible. We end up doing that > anyway but chucking the slower ones along the way. You could do same > in a toy meta HDL if you add a define or generate primitive to it. I can't really change the design of the cell (which is already at a high level). I can only interconnect them in different ways. The exact behaviour of the cells are determined by control signals (not shown). So I have to create random netlists of identical cells i.e. the cells are the same throughout each netlist, as well as between netlists. Fred -- Fred Ma, fma@doe.carleton.ca Dept. of Electronics, Carleton University, Ottawa, Ontario, Canada *| If I don't reply to your email, please sent it again. I may |* *| have erased along with the deluge of post-filter spam. |*Article: 69614
Tushit, This error is in a low level library and is difficult to explain the cause without analyzing it with a debugger. In the meantime if you do not have access to Quartus II 4.0 send me a qar (Quartus Archive) file of your project, and I can compile the design with 4.0 to find out if that will help you. - Subroto Datta Altera Corp. "tushit" <tushitjain@yahoo.com> wrote in message news:ec6aab0.0405150101.32610c46@posting.google.com... > Hi, > I know I should be posting this to Altera Support, but I am in a bit > of a hurry and hoping someone on the grp could advise me in parallel. > I get a Quartus internal error while it's doing a P&R. Has anyone seen > this before?? Any workarounds? I see this on 2 different machines both > with enough RAM(1GB). > > -------------------------------------------------------------------------- -- > Internal Error: Sub-system: CDB_ATOM, File: cdb_atom_netlist.cpp, > Line: 1585 > iter == m_created_from_map.end() > (Fitter pre-processing) > Quartus II Version 3.0 Build 245 10/09/2003 SJ Full Version > Service Pack Installed: 2 > --------------------------------------------------- > > Thanks & Regards > TushitArticle: 69615
"Dave Marsh" <me@privacy.net> wrote in message news:<40a4ce89$0$4587$db0fefd9@news.zen.co.uk>... > "Andy Peters" <Bassman59a@yahoo.com> wrote in message > news:9a2c3a75.0405131635.25f8ea90@posting.google.com... > > "Leon Heller" <leon_heller@hotmail.com> wrote in message > news:<40a0ebc8$0$25328$cc9e4d1f@news-text.dial.pipex.com>... > > > > > > Reflow soldering without baking them (probably 120 C for 24 hours) might > > > give problems. Hand soldering should be OK: I never have problems, > anyway. > > > > I'm not so sure about that. I bought a handful of microcontrollers > > about a year ago and stuffed boards, and all was fine. I never > > resealed the bag (I don't have the facility) so they sat until I used > > them a month ago. I handsoldered one prototype and it failed in a > > particular way. After much gnashing of teeth (I hate shotgunning > > parts), I removed the micro and replaced it with another from the same > > bag, which worked. I have since hand-built three more prototypes and > > I've had a 50% fallout. I guess I should've baked the parts... > > > > -a > > Thanks Andy. That's interesting - One of the assembly houses I've come > across on the web says the parts would need baking before they will hand > solder them . This seems to concur with your experiences. > > Dave Perhaps one of those BlackNdecker toaster ovens will do the job since they were mentioned awhile back as being useable for home based reflow ovens in another thread on BGA pcb work. regards johnjakson_usa_comArticle: 69616
Hi, I have created a IPIF device based on ssp1 for a MicroBlaze system. I have tested each device and they correctly generate interrupts. Now I have to use INTC to handle more than one interrupt signals and some external interrupt signals. By default IPIF ssp1 uses generic driver, that seems not support PARAMETER INT_HANDLER. 1.How can attach a int_handler to IPIF device? I have to write a specific driver for each IPIF device? 2.It's possible to specify interrupt level for external interrupt signals? ThanksArticle: 69617
Jon Beniston wrote: >>>Ok, maybe not that particular case, but most other configurations of >>>dual-port RAM can be infered. In Verilog at least, isn't this a >>>problem with the language rather than the FPGA tools (i.e. you can't >>>write to the same variable from two different processes)? >> >>Verilog does not have this restriction. I've searched the LRM and >>I've run testcases through two reputable implementations without >>complaints (ncverilog, icarus). > > > You are correct. Although it is only ever supported for simulation. I > can kind of understand why though. Take the following: > > module test(c1, c2, a, b, d); > input c1, c2, a, b; > output d; > reg d; > always @(posedge c1) > d <= a; > always @(posedge c2) > d <= b; > endmodule > > What logic would you synthesize it to? Have you tried this with a > behavioural synthesis tool? Maybe that could do a better job. > Another interesting question about the proposed code above is, during a given simulation cycle if both clocks rise at the same time, which executes first in simulation? Can you re-write the code so that one always has wins or if both happen a the same time an 'X' is generated on d? Cheers, JimArticle: 69618
What I did for Google was this: FPGA OR ASIC "blob analysis" which gave about 165 hits, but none of them seem to point me in the direction of any source code or even to any theoretical discussions. If you think I should try another search then please do suggest something. Someone was king enough to email me personally and suggested looking for some articals by Sumitomo, which produced a blob analysis chip some years ago. I don't know if that chip still exist and I can't find the articles mentioned. I added Sumitomo to the search above and received only three hits, none of them talked about blob analysis. > > Still looking for some suggestions. > > Consider google.com > > http://www.itee.uq.edu.au/~damien/GuRoo/theses/Wong.pdf > > -- Mike TreselerArticle: 69619
I'm using an FPGA (a Xilinx Spartan 3 XC3S400-4PQ208) in a design where one of it's functions is to sit between a cpu's SDRAM controller address and control lines and the sdram chips in order to register and buffer the signals and generate some additional chip selects. The data lines are not buffered. The processor in question (an Analog Devices ADSP-BF532) has the ability to pipeline the SDRAM address and control signals to support the delay introduced by this sort of buffering by one cycle. address, control, clock signals (A0-12, DQMB0-1, RAS#, CAS#, clk, etc.): CPU <-> FPGA <-> SDRAM data signals (D0-D15): CPU <-> SDRAM The question is how to analyze how long the FPGA needs to register the address and control lines on the input pins at the first rising edge of the clock signal received from the processor and then be able to have the buffered address and control lines available on the output pins on the FPGA at next rising edge of the clock. I'm not sure what I should be looking at in the timing analyzer to get the best estimate of what the timing parameters involved are. Also, what constraints should I set to minimize the timing overhead? Thanks EdArticle: 69620
"Brad Smallridge" <bradsmallridge@dslextreme.com> wrote in message
news:10ad0596rrmu4da@corp.supernews.com...
> What I did for Google was this:
>
> FPGA OR ASIC "blob analysis"
>
> which gave about 165 hits, but none of them seem to
> point me in the direction of any source code or even to
> any theoretical discussions. If you think I should
> try another search then please do suggest something.
Are you trying to what the CMU CAM does? Have you read the CMU papers? Blob
analysis doesn't mean anything to me so I'm guessing here, but perhaps you
meant center-of-mass type things?
The image processing stuff is generally DSP based as the algoritms are to
delineate an area using a standard convolver algorithm and then to track its
"center of mass" using standard graphics techniques for finding the center
of a polygon. (See Eberly's FAQ for that code).
Off the top of my head I'm guessing you could do some clever stuff whereby
you keep an array of pixels in a the block ram of an FPGA, and use some form
of iso-bar type system to connect regions with similar pixels. I'm not sure
what the logic would look like, something like
for (pixel = 2048 downto 0)
begin
if ( NEIGHBOR(0,pixel) or
NEIGHBOR(1, pixel) or
NEIGHBOR(2, pixel) or
NEIGHBOR(3, pixel) or
...
NEIGHBOR(7, pixel) ) then
group[pixel] <= group_id;
group_id++;
end if;
end for;
Like I said, I'm no expert. Basically you want logic that creates a
comparator whose inputs are the logically adjacent pixels for each
individual pixel, and a second array which is the group membership function
(in or out). If you set a specific criteria for membership (like the pixel
is a particular color) then this will probably work for you.
Then on each vertical retrace you need to compute the center of mass of
pixels in the "group."
--Chuck
Article: 69621geoffrey wall <wallge@eng.fsu.edu> wrote in message news:<c830uc$ha1$1@news.fsu.edu>... > actually, i think we are going to try both solutions(dsp and fpga) and > see how they compare with each other. thanks for the feedback. I'll be interested to hear your conclusions. I did a design study for my application a couple of years ago. Pentium vs DSP vs FPGA. The application did not leap out at me as a no-brainer for the FPGA -- processing of data packets, what I would call general scientific computation including division, straight-line fit and some minimization. The figure of merit was processing rate (packets per second) per dollar. And I certainly made a number of hand-waving assumptions in my estimation. Yet (to my surprise) the Pentium and DSP chip came out roughly equivalent. The FPGA won by a factor of 5. Now development effort is another story... Regards, -rajeev-Article: 69622
Mario Trams <Mario.Trams@informatik.tu-chemnitz.de> wrote: > it is difficult to diagnose this without seeing the code. I would guess > that there is a little mistake in your code. Well, the code is pretty much clean ... every entity interacting with the bus has a single process with a case statement that was generated from an already proven set of FSMs. But curiously enough, all the VHDL code works now. The only thing I did was to remove one or two extraneous signals that were declared but never used by any entity. Is it because the synthesiser's attempts at optimisation are so aggressive as to cause unexpected problems? > When you describe busses and you synthesize it for a PLD, this is > usually mapped into a MUX/DMUX structure (PLDs do not have tristatable > drivers). > > Most FPGAs (so the Virtex) have tristatable drivers and can handle > real busses. That makes sense. I am new to actual synthesis of hardware, this continues to be a learning experience for me. > You say that the synthesis for a CoolRunner CPLD worked fine. > Have you simulated and verified the backannotated design? Pointers for a complete newbie please ... I am aware that you are supposed to iterate at every stage of the process to smoothen out any wrinkles that may cause unexpected problems. The build process in ISE generates tons of information through various reports, but I don't know how to make proper use of that ... URLs / FAQs / tutes on this would be most useful. Thanks, Ashant.Article: 69623
Hello,
i am trying to learn how to use ModelSim with a VHDL Testbench, but i don't
find any answers on a few of my answers.
At the moment i start ModelSim always via "Simulate Post-Translate VHDL"
from Xilinx Project Navigator.
1) I can see all my stimuli, which are mainly the external in- and outputs.
They seems to toggle fine. But how can i display the internal signals ? Is
the only solution to assign a port to an internal signal to see it in
ModelSim. I already tried to simply define new signals, they are drawn in
ModelSim, but it seems they are not connected to the real signals. I think i
was able to add internal signals via "Signal" window, but next time i
simulate the signal was lost again...
2) I am currently can simulate my design once. When i external edit my vhdl
source or testbench i always must close ModelSim and restart it via Xilinx
Projects Manager. If i don't close it, i get an error message, that
"ModelSim is already running". Is there a more convenient way ?
3) I found a few nice commands like "view wave", "add wave *". Is there a
command for full zoom ? Where can i say, that certain commands should be
executed e.g. after drawing of a wave ?
4) Every time when i open ModelSim the wave window is only a small window,
positioned at right/lower corner of my screen. I already edited the wave
window "geometry", saved it to default name modelsim.tcl of my project
directory. But on next restart same windows size and position as before.
Must i move this file to a certain position. Is there a command like "use
preferences" that i can execute like in question 3 ?
5) In my vhdl source file i use a "std_ulogic_vector", because i want to use
tristate pins, for bidirectional data transfer of data. In the testbench the
xilinx tool created a testbench with "std_logic_vector". It compiles fine.
When i change it to "std_ulogic_vector" in testbench, ModelSim brings a
compile error, that source and testbench does not fit together. I already
use 'Z' for assignments and it seems to work. Should i just ignore this or
must i pay attention when doing it this way ? ModelSim can handle tristate
logic ?
6) Is there a FAQ for such questions ?
So enough for now,
Martin Maurer
Article: 69624geoffrey wall <wallge@eng.fsu.edu> wrote in message news:<c82o6r$g2m$1@news.fsu.edu>... > Im looking to do some real-time video processing algorithms, > but i am mostly a software person... i need an fpga with good > development tools (not buggy) that will be easy to use for someone who > is learning how to program hdl and use the hardware for the first time. > Ideally i would like a powerful and flexible board with good development > tools, good tech support and documentation. Any suggestions? > > thanks I normally don't plug my employer's products, but what you're asking for is covered quite nicely by the embedded dev kits from Altera as well as from our partner Microtronix. I suggest this approach as putting processor core(s) on the FPGA is very simple these days; for someone with software experience this can make getting started with hardware design a bit more simple as a processor allows you to bring up a design/debug/interface to your hardware with familiar means (software dev. & debug). Also consider a soft-processor has terrific potential for controlling the various hardware processing blocks in a design very easily. Also note that with any of these products you aren't required to use the processor; they're really just FPGA dev. boards with additional design tools/IP/RTOS support in the box. http://www.microtronix.com/ http://www.altera.com/products/ip/processors/nios/kits/nio-dev_kits.html Jesse Kempa Altera Corp. jkempa at altera dot com
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