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Hi *, I need some pointers from the gurus... I have two different designs, let's call them A and B. Both use 3 DCMs, both have the same input clock (it's all running in the FPGA on the same board). The DCMs in both designs are used to generate the same mupltiple frequencies, and are connected identically (i.e. regarding the BUFGs for the input and feedback and such). In design A, the DCMs lock, in B they won't, even if I manually put DCMs and the corresponding BUFGs in the same positions as in the design A via UCF constraints. So basically what I have is identical DCMs, hooked up identically, with identical input clocks, but in one design they won't lock. Now if I load design A into the FPGA, wait for the DCMs to lock, and then load the other design, the DCMs stay locked and everything work's fine. How can this be? Does the load on the output of a DCM affect it's ability to lock somehow? What else can cause DCMs not to lock despite of valid input frequency? cu, SeanArticle: 69826
Hello, I am a newbie in VHDL and have not much experience with FPGA implementation. To change that I am doing a self-study project that includes implementing some signal processing functions in VHDL and putting it on a Spartan II. To start simple I am working on a cyclic prefix function. Input to the function are 512 samples from an IFFT and the function adds 32 samples to the 512 samples. So my problem is now that I have 512 samples coming in and 512+32 samples going out. The output is supposed to go to a DAC, so that sampling rate will be constant. What makes this a bit more complicated is that the prefix adding can be disabled. So if enabled it outputs 512+32 samples and disabled only the 512 samples. I was thinking about two different ways of doing that. One is to adjust the processing rate of the IFFT and the input frequency of the cyclic prefix block and keep the output frequency constant for the DAC. This would lead to a quite crooked frequencies for the IFFT and I have no experience whether that is actually feasible. The other idea is to have the IFFT deliver the 512 samples and then stop its processing for 32 samples. Is my first thought about the different clock frequencies actually feasible? Can anybody give me some thoughts about what is a common way of handling different processing speeds with FPGA implementations? The second thought seems more intuitive? Is that the way of doing things or is there a better way? Thanks for the help. Guenter p.s.: I am waiting on a FPGA book in the mail that hopefully helps me beef up my knowledge in that field. For the time being I was just eager to go on with my design and hear some expert opinions.Article: 69827
as said, i have to connect the CAN IP-Core with Leon Processor and implement the whole modul in a FPGA Board. i have downloaded Leon Core from www.gaisler.com and CAN IP-Core from www.opencores.com. So there was not much documentation for the CAN IP-Core. In my Opinion, the CAN IP-Core is quite similar to the SJA1000 Pelican, but not the same. in my CAN Core, from the Register 10 to 19, it refers to tx_data_0 to tx_data_9, and from Register 20 to 29 refers to rx_data_0 to rx_data_9. As said, i have connected the CAN Core to Leon as an APB-Slave and to send a message from Can Core, i have written a C-Code with following steps: 1) i write the data to tx_data_0 to tx_data_9 register. the tx_data_0 and tx_data_1 Register has the information of the Identifier, RTR and Data length. 2) then i set the command register of 0x01 to send the message. 3) i have disabled the interrupt register and error register and just want to sent a message first. 4) to observe the can bus i have the CANalyzer. Just till now, i have not received single message.Article: 69828
Hi,
Do any of u know of the existence of datasheets/ spec sheets for the
DS-BD-V2M1000 eval board(Xilinx Virtex 2 eval board). I searched on Google
and the Memec Design's web site. Nothing there!
If any of u know, please let me know.
--
end
Joji John ( nansung444@yahoo.com)
"Cogito; ergo sum"
" plain text reduces headaches"
http://www.angelfire.com/ma3/joji
http://geocities.com/nansung444
Article: 69829
Hi,
I am a kind of newbie too. But this much I know. IF ever u need to
interface two different clock domains u use an asnchronous FIFO. Now
consider a deep enough FIFO for ur application. Let whatever be written in,
it can be read out at different clock rate. Again I'm a newbie and there can
be better suggestions.
--
Joji John ( nansung444@yahoo.com)
"Cogito; ergo sum"
" plain text reduces headaches"
http://www.angelfire.com/ma3/joji
http://geocities.com/nansung444
"Guenter Dannoritzer" <dannoritzer@web.de> wrote in message
news:c8kihm$i15$07$1@news.t-online.com...
> Hello,
>
> I am a newbie in VHDL and have not much experience with FPGA
> implementation. To change that I am doing a self-study project that
> includes implementing some signal processing functions in VHDL and
> putting it on a Spartan II.
>
> To start simple I am working on a cyclic prefix function. Input to the
> function are 512 samples from an IFFT and the function adds 32 samples
> to the 512 samples. So my problem is now that I have 512 samples coming
> in and 512+32 samples going out. The output is supposed to go to a DAC,
> so that sampling rate will be constant. What makes this a bit more
> complicated is that the prefix adding can be disabled. So if enabled it
> outputs 512+32 samples and disabled only the 512 samples.
>
> I was thinking about two different ways of doing that. One is to adjust
> the processing rate of the IFFT and the input frequency of the cyclic
> prefix block and keep the output frequency constant for the DAC. This
> would lead to a quite crooked frequencies for the IFFT and I have no
> experience whether that is actually feasible.
>
> The other idea is to have the IFFT deliver the 512 samples and then stop
> its processing for 32 samples.
>
> Is my first thought about the different clock frequencies actually
feasible?
>
> Can anybody give me some thoughts about what is a common way of handling
> different processing speeds with FPGA implementations?
>
> The second thought seems more intuitive? Is that the way of doing things
> or is there a better way?
>
> Thanks for the help.
>
> Guenter
>
> p.s.: I am waiting on a FPGA book in the mail that hopefully helps me
> beef up my knowledge in that field. For the time being I was just eager
> to go on with my design and hear some expert opinions.
>
Article: 69830Hello, Would anyone have a copy of Chameleon Systems's white paper "IIR Filter Design Using the CS2112"? Could I impose on you to send me a copy? Fred fma@doe.carleton.caArticle: 69831
I would look at the power supply for the DCM. Is the Vccaux directly connected to a Vcco power rail if so possible problem there. Otherwise look at the jitter on input clocks at each level. Thirdly if you have a DCM chain hold the DCM in reset until the input clock is stable (locked). John Adair Enterpoint Ltd. - Home of Broaddown2 http://www.enterpoint.co.uk This message is the personal opinion of the sender and not that necessarily that of Enterpoint Ltd.. Readers should make their own evaluation of the facts. No responsibility for error or inaccuracy is accepted. "Sean Durkin" <smd@despammed.com> wrote in message news:2h5ve2F8pr4iU1@uni-berlin.de... > Hi *, > > I need some pointers from the gurus... > > I have two different designs, let's call them A and B. Both use 3 DCMs, > both have the same input clock (it's all running in the FPGA on the same > board). The DCMs in both designs are used to generate the same mupltiple > frequencies, and are connected identically (i.e. regarding the BUFGs for > the input and feedback and such). In design A, the DCMs lock, in B they > won't, even if I manually put DCMs and the corresponding BUFGs in the > same positions as in the design A via UCF constraints. > > So basically what I have is identical DCMs, hooked up identically, with > identical input clocks, but in one design they won't lock. > > Now if I load design A into the FPGA, wait for the DCMs to lock, and > then load the other design, the DCMs stay locked and everything work's fine. > > How can this be? Does the load on the output of a DCM affect it's > ability to lock somehow? What else can cause DCMs not to lock despite of > valid input frequency? > > cu, > SeanArticle: 69832
jseely@altera.com (Joel A. Seely) wrote in message news:<9bded7a8.0405200947.28b2d90c@posting.google.com>... >When you start using > the processor in applications that have an RTOS, it's a different > story. Each time you have to do a context switch, unless the RTOS is > really clever, you have to save out the whole set of registers > associated with the task that is getting swapped out and read in the > set of registers for the task that is getting swapped back in. Yes, but without the windows those would have been swapped out to the stack allready anyway so you loose nothing. Also note how much you gain: For example for a bifurcating recursion even a single level of register windows saves 50% of the register spills, regardless of how deep the recursion is. Two levels save 75%. And so on... For non-recursive scenarios the numbers are even better. (5 levels save almost all spills) BTW: This whole discussion is oT and belongs into comp.arch. Kolja SulimmaArticle: 69833
"Symon" <symon_brewer@hotmail.com> writes: > It may be pretty easy to do this. I've done a little research, it seems > there's a JTAG language called Serial Vector Format or SVF. Check out > XAPP503. It also appears that iMPACT can play something called XSVF format > files through the Xilinx JTAG cables. There's a utility included with > XAPP058 called SVF2XSVF. Mix together with some Perl scripts, piece of cake, > right? ;-) > Does this make sense? Am I on the right track? Anybody done anything > similar? Like to share your experiences? I've written my own software to program an fpga from an svf file. If you want to program a flash isp using jtag you will need (in addition to a svf parser) to parse the bsdl files for all the devices in the scan chain as well. You should also read the netlist (edif in most cases) or some other description of which pins are connected to the flash. Petter -- A: Because it messes up the order in which people normally read text. Q: Why is top-posting such a bad thing? A: Top-posting. Q: What is the most annoying thing on usenet and in e-mail?Article: 69834
In article <h8cra09qmgc17ulbvh1t4bk80dr1it2g39@4ax.com>, Jonathan Bromley <jonathan.bromley@doulos.com> wrote: >Tee hee. Interrupt latency is a joke number. I wrote a >piece about twelve years ago for one of the embedded-system >comics, pointing out how insignificant is the processor's >own interrupt latency - there are many things that are >orders of magnitude more important to interrupt performance. >Here as in many other things, the transputer was on the >right track. Sadly, limitations of design culture and >available technology doomed it to commercial failure. I remember doing a bit of due dilligance for a relative who was looking at a job at a company which was making similar claims (they were using a shadow-register setup). I basically did an amdahl's law workup and gave the advice of "this is why it is bogus", and the observation that, since the company HAD funding, it might be good for a year but nothing beyond that. >>and why are there so many transputer people in fpgaland? > >Perhaps because they know a good thing when they see one? More importantly, if we ever "solve" the tool problem for general purpose computation on FPGAs, we solve it for Transputers. -- Nicholas C. Weaver nweaver@cs.berkeley.eduArticle: 69835
Rick, You are correct. I just lashed out. I apologize (to the newsgroup). Now that we are the "gorilla" I need to be 5X more humble. We win with listening to customers and always placing them first. I can't say I won't over-react again, but I can say I will try to improve. Austin -snip- > > > I am just curious Austin, do you think this message helped either you or > Xilinx? >Article: 69836
John, Couldn't have said it better. Also, I would start a webcase with the hotline. Austin John Adair wrote: > I would look at the power supply for the DCM. Is the Vccaux directly > connected to a Vcco power rail if so possible problem there. Otherwise look > at the jitter on input clocks at each level. Thirdly if you have a DCM chain > hold the DCM in reset until the input clock is stable (locked). > > John Adair > Enterpoint Ltd. - Home of Broaddown2 > http://www.enterpoint.co.uk > > This message is the personal opinion of the sender and not that necessarily > that of Enterpoint Ltd.. Readers should make their own evaluation of the > facts. No responsibility for error or inaccuracy is accepted. > > > "Sean Durkin" <smd@despammed.com> wrote in message > news:2h5ve2F8pr4iU1@uni-berlin.de... > >>Hi *, >> >>I need some pointers from the gurus... >> >>I have two different designs, let's call them A and B. Both use 3 DCMs, >>both have the same input clock (it's all running in the FPGA on the same >>board). The DCMs in both designs are used to generate the same mupltiple >>frequencies, and are connected identically (i.e. regarding the BUFGs for >>the input and feedback and such). In design A, the DCMs lock, in B they >>won't, even if I manually put DCMs and the corresponding BUFGs in the >>same positions as in the design A via UCF constraints. >> >>So basically what I have is identical DCMs, hooked up identically, with >>identical input clocks, but in one design they won't lock. >> >>Now if I load design A into the FPGA, wait for the DCMs to lock, and >>then load the other design, the DCMs stay locked and everything work's > > fine. > >>How can this be? Does the load on the output of a DCM affect it's >>ability to lock somehow? What else can cause DCMs not to lock despite of >>valid input frequency? >> >>cu, >>Sean > > >Article: 69837
Hi, I am the proud new owner of a Virtex XCV50 sitting on a XESS protoboard. I know this is an old system but I want to learn about FPGA's and VHDL with it. Does anyone have a program that I can use to make the Ethernet interface work or perhaps the video inputs. I prefer to have some TCP/IP software so I can connect it to a network and test the ethernet. Any pointers are greatly appreciated. Thanx Dave WilliamsArticle: 69838
Sean Durkin wrote: >I have two different designs, let's call them A and B. Both use 3 DCMs, >both have the same input clock (it's all running in the FPGA on the same >board). The DCMs in both designs are used to generate the same mupltiple >frequencies, and are connected identically (i.e. regarding the BUFGs for >the input and feedback and such). In design A, the DCMs lock, in B they >won't, even if I manually put DCMs and the corresponding BUFGs in the >same positions as in the design A via UCF constraints. > >So basically what I have is identical DCMs, hooked up identically, with >identical input clocks, but in one design they won't lock. > >Now if I load design A into the FPGA, wait for the DCMs to lock, and >then load the other design, the DCMs stay locked and everything work's fine. > >How can this be? Does the load on the output of a DCM affect it's >ability to lock somehow? What else can cause DCMs not to lock despite of >valid input frequency? Output pins with heavy loads near the clock pins can add jitter to the input clock signal if they happen to switch near the clock edges. Are you resetting the DCM? A reset (3 clock cyles or longer) after configuration and stable clock may be needed to get the DCM to lock reliably. -- Phil Hays Phil_hays at posting domain should work for emailArticle: 69839
aspire@texas.net (quantum) wrote in news:5b041c26.0405210725.6f6cc9bc@posting.google.com: > Hi, > I am the proud new owner of a Virtex XCV50 sitting on a XESS > protoboard. > > I know this is an old system but I want to learn about FPGA's and VHDL > with it. > > Does anyone have a program that I can use to make the Ethernet > interface work or perhaps the video inputs. I prefer to have some > TCP/IP software so I can connect it to a network and test the > ethernet. > > Any pointers are greatly appreciated. > > Thanx > > Dave Williams > It's always good to go to the XESS website to start searches for things like this. Here is a page for sample projects from XESS and others: http://www.xess.com/ho03000.html. -- ---------------------------------------------------------------- Dr. Dave Van den Bout XESS Corp. PO Box 33091 Raleigh NC 27636 Phn: (919) 363-4695 Fax: (801) 749-6501 devb@xess.com http://www.xess.comArticle: 69840
"Petter Gustad" <newsmailcomp6@gustad.com> wrote in message news:874qq9dhoy.fsf@filestore.home.gustad.com... > > I've written my own software to program an fpga from an svf file. If > you want to program a flash isp using jtag you will need (in addition > to a svf parser) to parse the bsdl files for all the devices in the > scan chain as well. You should also read the netlist (edif in most > cases) or some other description of which pins are connected to the > flash. Hi Petter, What did you use for the physical connection between your PC and JTAG target? Or was it an embedded application? Thanks, Syms. p.s. Look, I've bottom posted, just for you! ;-)Article: 69841
Austin Lesea <austin@xilinx.com> wrote in message news:<c8jeee$cfc3@cliff.xsj.xilinx.com>... > Jesse, > > Processors, plural. > > I'm still right. > > Austin > My sincere apologies. I would drop this, but as its a public forum and I want the reading public to know the truth. Some further elaboration: Multiple embedded processorS on an FPGA (plural) have been technologically feasible, supported, and implemented by customers -- with Nios -- since its inception (I'm sure the same could be said of other offerings prior to that date, too), and we continue to support that. That has been extended in the most recent release of our product. As an example, the user can debug many (we have tested up to 8) processorS (plural) simultaneously via a single JTAG connection and a nice IDE environment. That's the real beauty of an FPGA, as we all know... you have logic you can put to any use, including the same use several times over to do interesting things. And if for some reason a "soft" processor does not equal a "hard" one, well, I suppose that is a matter of debate. They both take compiled C code and do useful tasks, so I think they're both proessorS. Regards, Jesse Kempa Altera Corp. jkempa at altera dot comArticle: 69842
Is there an open USB hub anywhere? I can find USB device cores, but not hubs. -jimArticle: 69843
You're really sad ? Take a look at the terribly broken setjmp/longjmp implementation for Nios I. Register windows work ok if you never switch stacks (say for threads or to have a separate exception stack). A correct implementation of context switching requires that you spill all the register windows on the task being switched out and restore to the previous depth the windows on the task being switched in. setjmp/longjmp together should behave as a context switch. If your interrupt processing model is -- all processing related to an interrupt happens in the interrupt service routine you might be happy with register windows (unless you are unfortunate enough to have the exception occur when the windows are full). On the other hand, if your modle is do only the things that must be done in the service routine, then enable a thread to do the rest, then you probably aren't too happy. I'm quite pleased that they dumped this feature and took the lean approach. Geoffrey Richard Pennington wrote: > Goran Bilski wrote: > >> It seems that Altera has created a MicroBlaze as well. >> They have finally realized that a FPGA based soft processor should have >> - 32 bit ISA >> - 32 registers >> - 3 operand instruction format >> - JTAG based HW debugging >> - HW divider >> >> The weird register window mechanism from NIOS (is it called NIOS1 >> now?) didn't work well in embedded processing markets. >> >> Göran Bilski > > > Actually, it works quite well if used correctly. It isn't used correctly > in the implementations I've seen (from Altera and from an OS vendor). > I modified the OS to change the register spill strategy: Rather than > spilling the entire register set, we only spill one register frame. > Restores are done normally. This results in a "run time optimization" of > the top of the register window forprograms. This works very well in > practice because after initialization and task startup, a task's > register window is at the top of the register file. For a 256 register > file that means you get 14 function calls before a register spill occurs. > > I'm a little sad that we'll lose the register windows in Nios2. > Performance, etc. will make up for it. ;-) > > -Rich >Article: 69844
"Symon" <symon_brewer@hotmail.com> writes: > "Petter Gustad" <newsmailcomp6@gustad.com> wrote in message > news:874qq9dhoy.fsf@filestore.home.gustad.com... > > > > I've written my own software to program an fpga from an svf file. If > > you want to program a flash isp using jtag you will need (in addition > > to a svf parser) to parse the bsdl files for all the devices in the > > scan chain as well. You should also read the netlist (edif in most > > cases) or some other description of which pins are connected to the > > flash. > > Hi Petter, > What did you use for the physical connection between your PC and JTAG > target? Or was it an embedded application? I've done several versions. One was the pci bus (i.e. isp on a pci card). The other was ethernet. I've been thinking of making the latter into a product since it's quite user friendly. You don't need a device driver on the PC side. You simply use one of the tftp client programs out there and transfer the data to the programmer. Petter -- A: Because it messes up the order in which people normally read text. Q: Why is top-posting such a bad thing? A: Top-posting. Q: What is the most annoying thing on usenet and in e-mail?Article: 69845
Geoffrey Brown <geobrown@cs.indiana.edu> writes: > You're really sad ? Take a look at the terribly broken setjmp/longjmp > implementation for Nios I. Register windows work ok if you > never switch stacks (say for threads or to have a separate exception > stack). A correct implementation of context switching requires that > you spill all the register windows on the task being switched out and > restore to the previous depth the windows on the task being switched in. > setjmp/longjmp together should behave as a context switch. The officially defined semantics of setjmp and longjmp do not require that they be usable for switching stacks; they only are defined to unwind a stack. I ran into exactly this problem when I ported the Telebit Netblazer operating system to the AMD 29000 back in 1991. The 29000 typically uses register windows, although it can also use the entire set of 128 local registers as "normal" non-windowed registers. I had to rewrite the setjmp and longjmp implementation exactly as you describe. However, I wouldn't claim that this is because the setjmp/longjmp implmenetation was broken. It was behaving exactly as specified. Rather, the problem is with using setjmp/longjmp for something other than unwinding the stack. I thing a case could be made that the next revision of the C standard should have new library functions for context switching.Article: 69846
On Fri, 21 May 2004 15:18:20 +0530, "john" <nansung444@yahoo.com> wrote:
>Hi,
> Do any of u know of the existence of datasheets/ spec sheets for the
>DS-BD-V2M1000 eval board(Xilinx Virtex 2 eval board). I searched on Google
>and the Memec Design's web site. Nothing there!
>If any of u know, please let me know.
Have you looked here?
http://tinyurl.com/23xo6
and here:
http://www.memec.com/Memec/iplanet/link1/Virtex-IIMB.pdf
Philip
Philip Freidin
Fliptronics
Article: 69847Thanx, I found these. -- Joji John ( nansung444@yahoo.com) "Cogito; ergo sum" " plain text reduces headaches" http://www.angelfire.com/ma3/joji http://geocities.com/nansung444 "Philip Freidin" <philip@fliptronics.com> wrote in message news:rt4ta0ls7a004ehgqtkr75d0f4rceouguo@4ax.com... > On Fri, 21 May 2004 15:18:20 +0530, "john" <nansung444@yahoo.com> wrote: > >Hi, > > Do any of u know of the existence of datasheets/ spec sheets for the > >DS-BD-V2M1000 eval board(Xilinx Virtex 2 eval board). I searched on Google > >and the Memec Design's web site. Nothing there! > >If any of u know, please let me know. > > Have you looked here? > > http://tinyurl.com/23xo6 > > and here: > > http://www.memec.com/Memec/iplanet/link1/Virtex-IIMB.pdf > > > Philip > > > Philip Freidin > FliptronicsArticle: 69848
"Tim" <tim@rockylogic.com.nooospam.com> wrote in message news:<c8jdui$9rg$1$8300dec7@news.demon.co.uk>... > Austin Lesea wrote: > > > lowest interrupt latency of any soft processor core (and > > even better than most hard processors) > Oh, I am asked to say something:) Ok I have no idea whose interupt latency is shortest. Probably the cpu that has the fastest clock rate or the one thats specially designed for int response handling. I suspect that the several ASIC MT cpus that have recently come along for the wireless set could well have the best int response esp 1 that runs 8 threads at 250MHz (or was it 400MHz) because the threads run all the time every 8th cycle. ANd these cpus don't have context to swap since they have N contexts in ram. Technically Transputers don't have interrupts, thats too low a level of looking at them, but they do service events with an incredibly quick response for a variety of reasons but that was at 25MHz and 15yrs ago. Now the R3 cpu also being an multithreaded (MT) cpu (and also now running baby code BTW in C model) could designate 1 of its 16 threads to poll some HW and take the event home. That would mean about 20-50 cycles of computation might pass before Pn noticed it had to do some work. If Pn can find away to stay active in the IX engine without branching (which causes process swap round robin style) then it could notice an event in <4cycles. I don't think I will add support for always stay active process. Now when the process thats does service an interupt does get it's turn, it will have no registers to swap but it may have to do some cache misses while workset becomes reloaded but thats transparent to MT. If it pans out at 250MHz in V2Pro it may or may not have fastest int response. It will however have the most throughput of any FPGA cpu bordering on 1.3clock Freq from the sim traces. It loves branches and transfers and swapping, its the nature of the MT beastie. > that must be red rag to a bull for john jackson and the other > transputer folk. > > and why are there so many transputer people in fpgaland? Well I don't remember anyone else here that identifies themself as such, most are probably busy elsewhere. And where is Alan C! Well the answer to that is real simple. Anything FPGAs do today esp DSP and coms and whatever was once done by Transputers. Look at Nallatech and a whole load of UK/European companies that were once Transputer TRAM module houses. Those that survived are all FPGA guys today and in the top tier of high perf engineering. Whats a good engineer to do when something runs out of gas, look for the next obvious replacemment. Also the FPGA and the Transputer more or less came out at the same time 84++, the Transputer peaked along time ago, the FPGA really started peaking only a few years ago, wasn't really much use till 4K or later (sorry).. That also brings me to the other point. Occam runs on both. Not C. Ofcource Occam had to resurrect itself in C syntax (HandelC) to be more attractive to the avg EE to be synthesizeable for FPGA. BTW I am not a fan of HandelC, just mention thats its roots go back to Occam. I will leave it there regards johnjakson_usa_comArticle: 69849
Jonathan Bromley <jonathan.bromley@doulos.com> wrote in message news:<h8cra09qmgc17ulbvh1t4bk80dr1it2g39@4ax.com>... > On Fri, 21 May 2004 00:09:34 +0100, "Tim" > <tim@rockylogic.com.nooospam.com> wrote: > > >Austin Lesea wrote: > > > >> lowest interrupt latency of any soft processor core (and > >> even better than most hard processors) > > > >that must be red rag to a bull for john jackson and the other > >transputer folk. > > Tee hee. Interrupt latency is a joke number. I wrote a > piece about twelve years ago for one of the embedded-system > comics, pointing out how insignificant is the processor's > own interrupt latency - there are many things that are > orders of magnitude more important to interrupt performance. > Here as in many other things, the transputer was on the > right track. Sadly, limitations of design culture and > available technology doomed it to commercial failure. > > Just for the record, here's Bromley's First and Second Law > of commercial failure in a technological product: > > First Law: > Probability of commercial failure is increased if the > product meets any of the following criteria: > 1) It employs concepts and techniques that will become > popular more than a decade later. > 2) Its design is based on technically, logically or > mathematically sound principles. > 3) Its creators are British. > Perhaps I am doomed to fail on all 3 counts. Anyway I may be a US citizen before this thing gets polished and can deny the last rule as everything important has to seem to be invented or reinvented in the US- (sadly). Since my math isn't so great maybe I can deny the 2nd rule too:). And 20yrs have passed since I left and the Transputer shipped so I can beat that one too perhaps. > Second Law: > The probability of commercial failure is unity if two > or more of the above criteria are met. > > >and why are there so many transputer people in fpgaland? > > Perhaps because they know a good thing when they see one? > yep > Getting more and more cynical as time rolls by... > -- > Jonathan Bromley, Consultant > > DOULOS - Developing Design Know-how > VHDL, Verilog, SystemC, Perl, Tcl/Tk, Verification, Project Services > > Doulos Ltd. Church Hatch, 22 Market Place, Ringwood, BH24 1AW, UK > Tel: +44 (0)1425 471223 mail:jonathan.bromley@doulos.com > Fax: +44 (0)1425 471573 Web: http://www.doulos.com > > The contents of this message may contain personal views which > are not the views of Doulos Ltd., unless specifically stated.
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