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Tomorrow is the big Nios II launch date, but info is already going up.... www.altera.com http://www.fpgajournal.com/articles/20040518_nios2.htm Full 32bit. 2X-4X faster than Nios I and starts at only 500 LE's. New IDE. New Compact Flash and other periferals.... Can't wait to get a hold of it. KenArticle: 69726
The biggest problems with coregen are that they don't let you see under the
hood, and there isn't really a way for you to put your own IP into it. For
memories and other primitives, you are better off just instantiating the
primitive out of the unisims library. I think unisims were new in XACT-6, so
you may vaguely remember them. They replaced the old primitive library. Where
coregen has value is in more complex macros like various DSP cores....that is if
you can live with what they give you (you can't get under the hood to see how
they work or make changes to them).
The terminology is a little bit wrong. The primitives are the basic components
that have a 1:1 mapping to things on the die. You can use primitives to build
macros, which I believe you are calling your own primitives. If you include
placement on the primitives in a macro, you can make it into an RPM (relatively
placed macro). The RLOCs are still there, although changed somewhat in format
from what you knew in xact 6. RLOCs are in xy form rather than RC form, but are
more or less the same idea. You can put RLOCs on primitives instantiated in an
HDL, VHDL works a little better for this because you can easily put RLOCs that
depend on a loop variable on a generated macro. It is still very awkward to do
that with Verilog even with the verilog2000 extensions. I use RPMs generated by
parameterized VHDL extensively. You can see floorplans for some of my designs
on the gallery page of my website. That said, you don't necessarily have to use
RLOCs on primitives. You can also floorplan (although it is on the flat design
in these cases) using the floorplanner tool or using text in a .ucf constraints
file. The floorplanner will look familiar if you used the one in XACT6. There
are some newer features (relative to XACT 6) like area groups that you may find
useful. One thing you may find frustrating is that in XACT6, if you gave it a
good placement you got a good route, and you'd get pretty much the same routing
solution everytime you ran it, even after incremental changes. The router in
the ISE6 tool doesn't work the same way. Instead, it starts off with a
seemingly random route and only moves routes if they violate timing or are in
the way of another route. It stops running as soon as all routes meet timing
without doing any kind of clean-up. This is perhaps fine for slow designs, but
if you are floorplanning you are probably trying to milk the maximum performance
you can get. With this routing strategy, you'll find that essentially all the
routes in the design are critical routes, and short connections are often routed
in a not so direct manner. It is apparently the price for faster time to
completion.
glen herrmannsfeldt wrote:
>
> The design is pretty specifically Xilinx, so I am not
> so sure about that, yet.
>
> If I can manually get to the library primitives, that should be
> enough. I haven't reached that point in the manual yet.
>
> Can I make my own primitives, like RPMs in Xact?
> That is more important.
>
> -- glen
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 69727
You may have to put LOC constraints on the BUFGs and CLKDLLs. The automatic placer doesn't do so hot a job figuring out
which BUFGs should be next to which CLKDLLs. The usual result is that error message.
>
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 69728Lots of responses already so I'll just add a few bits that have been missed ... "Paul Marciano" <pm940@yahoo.com> wrote in message news:d5bc3deb.0405181044.7821e99@posting.google.com... > 1. I need a device with at least nRegisterBits/2 CLBs. > 2. nRegisterBits/2 is probably grossly optimistic. Actually I've yet to run out of CLBs in anything I've done (not a lot of complicated stuff) however you can easily run out of "clock domains" (global clocks) routing resources (no way to connect two parts of your design), and I/O pins. So perhaps a better way to approach this is figure out how many I/O's you need. Get the free WebPack tools and select a devices that has that many i/o's. Start developing your verilog stuff and synthesize it after each major subsystem is done. If you run out of CLB's go to the next bigger, if there isn't one bigger in the same package, try the next larger package. Then the next "family." The cost -> complexity path is: 9500 CPLD -> CoolRunner CPLD -> Spartan 2 -> Spartan 2E -> Spartan 3 -> Spartan3E Since you can get Spartan 3's with a bazillion CLBs I know you won't get that far up the food chain. The latest Digikey catalog sells Spartan 2's with 50K "gates" for $22 qty 1, You can do a complete CPU + Video etc in one of those. Actually you should probably google for "Commodore One" where Jeri Ellsworth has implemented in FPGA replacements for the Commodore 64 special function chips. On a related note, does anyone have a decent S-video circuit that one could use an FPGA to implement? Lots of FPGA kits have VGA connectors (simple RGB + Sync output) but I'd like something I could use to make video on my television ... --ChuckArticle: 69729
Chuck McManis wrote: (snip) > On a related note, does anyone have a decent S-video circuit that one could > use an FPGA to implement? Lots of FPGA kits have VGA connectors (simple RGB > + Sync output) but I'd like something I could use to make video on my > television ... The old trick for generating composite video should still work for S-video, except that the chrominance and luminance are not combined. Look at how the IBM CGA did it, for example. The dot clock is 4x the color subcarrier (3579545Hz), such that the result comes out a specific color depending on the phase of the result. D/A converters on each, so that you can generate more than just on/off for each color. It might be that you can do a little better with a higher multiple of 3579545, but you will find the 4x crystals easier to find. (They still exist in any PC with an ISA bus.) -- glenArticle: 69730
Ray Andraka wrote: > The biggest problems with coregen are that they don't let you see under the > hood, and there isn't really a way for you to put your own IP into it. For > memories and other primitives, you are better off just instantiating the > primitive out of the unisims library. I think unisims were new in XACT-6, so > you may vaguely remember them. They replaced the old primitive library. Where > coregen has value is in more complex macros like various DSP cores....that is if > you can live with what they give you (you can't get under the hood to see how > they work or make changes to them). Those I don't need, so I should be safe. > The terminology is a little bit wrong. The primitives are the basic components > that have a 1:1 mapping to things on the die. You can use primitives to build > macros, which I believe you are calling your own primitives. Well, things like adders. Well, with XACT6 I had RPM's for a saturating adder (If the result would be less than zero the output would be zero). That was easy to do in XC4000, as there is one more input to the CLB's than needed for the adder logic. I could sense underflow from the carry chain and signal all the CLBs to output zero. The other one is MAX(a,b), where the carry chain was used to detect which was greater, and the CLB to select the appropriate input. As I understand it, the logic is different now so I will have to look through the manual and see how to do those. It seems that counters are generated by CoreGen, so I thought adders might also be. > If you include > placement on the primitives in a macro, you can make it into an RPM (relatively > placed macro). The RLOCs are still there, although changed somewhat in format > from what you knew in xact 6. I never needed RLOCs. The design was full of 16 bit adders and 16 bit max, which had to follow the carry chain. There weren't many places to put them. > RLOCs are in xy form rather than RC form, but are > more or less the same idea. You can put RLOCs on primitives instantiated in an > HDL, VHDL works a little better for this because you can easily put RLOCs that > depend on a loop variable on a generated macro. It is still very awkward to do > that with Verilog even with the verilog2000 extensions. I use RPMs generated by > parameterized VHDL extensively. I did mine in LCAedit, I think that is what it was called. > You can see floorplans for some of my designs > on the gallery page of my website. That said, you don't necessarily have to use > RLOCs on primitives. (snip) > The router in the ISE6 tool doesn't work the same way. > Instead, it starts off with a > seemingly random route and only moves routes if they violate timing or are in > the way of another route. It stops running as soon as all routes meet timing > without doing any kind of clean-up. This is perhaps fine for slow designs, but > if you are floorplanning you are probably trying to milk the maximum performance > you can get. With this routing strategy, you'll find that essentially all the > routes in the design are critical routes, and short connections are often routed > in a not so direct manner. It is apparently the price for faster time to > completion. In the design before, I was trying to maximize the number of unit cells multiplied by the clock frequency. Because of the way P&R did it, it turned out to be much faster with three units (in an XC4013) than four, even though four fit just fine. The first thing I will work on is to see how well the previous logic works in the new FPGAs. (The design is a linear systolic array processor.) thanks for the hints, -- glenArticle: 69731
Dear Sir or Madam, I have some phenomenon I do not know when synthesizing my VHDL description for my SRAM controller: The .vho-file from Quartus is used for a timing simulation. When I have a look at internal signals of my controller like 'l_oe_bar', 'l_cs_bar','l_we_bar' I see in timing simulation with Modelsim that they are right inverted to my description, for example are they resetted to '0' and not to my declared '1' in the VHDL description. The outputs of my controller are concurrently assigned like that: OE_bar <= l_oe_bar; CS_bar <= l_cs_bar; WE_bar <= l_we_bar; And yet they are inverted to the local signals. I do not know why there seems to be a double inversion. What does QuartusII do? I would appreciate your help. Kind regardsArticle: 69732
Hello, i think in the last release of Xilinx Webpack 6.1 or 6.2 the abilitiy has added to initialize a blockram from file by xst. But this feature is not documented by xilinx or 1 don't found it. Has anyone used this feature?Article: 69733
ALuPin wrote: > I have some phenomenon I do not know when synthesizing my VHDL > description for my > SRAM controller: > The .vho-file from Quartus is used for a timing simulation. When I > have a look at internal signals > of my controller like 'l_oe_bar', 'l_cs_bar','l_we_bar' > I see in timing simulation with Modelsim that they are right inverted > to my description, Without actually looking at your files, assuming you are working with FPGA's it is very common that inverters disappear. Active high or low makes no difference to a lookup table, the synthesis should generate equivalent logic, though the actual sign may change. -- glenArticle: 69734
It seems that Altera has created a MicroBlaze as well. They have finally realized that a FPGA based soft processor should have - 32 bit ISA - 32 registers - 3 operand instruction format - JTAG based HW debugging - HW divider The weird register window mechanism from NIOS (is it called NIOS1 now?) didn't work well in embedded processing markets. Göran Bilski Kenneth Land wrote: >Tomorrow is the big Nios II launch date, but info is already going up.... > >www.altera.com > >http://www.fpgajournal.com/articles/20040518_nios2.htm > > >Full 32bit. 2X-4X faster than Nios I and starts at only 500 LE's. New IDE. >New Compact Flash and other periferals.... Can't wait to get a hold of it. > >Ken > > > >Article: 69735
Goran Bilski wrote: > It seems that Altera has created a MicroBlaze as well. > They have finally realized that a FPGA based soft processor should have > - 32 bit ISA > - 32 registers > - 3 operand instruction format > - JTAG based HW debugging > - HW divider > > The weird register window mechanism from NIOS (is it called NIOS1 now?) > didn't work well in embedded processing markets. I did hear that NIOS II was quite close to the MIPs CPU in structure/mindset.... -jgArticle: 69736
There is a bug in ISE 6.x. You should manually LOC the IBUFG, BUFGs, and DLL. LOC the BUFGP on the same side as input clock and LOC DLL, FB BUFG and CLK90 BUFG on the opposite side. Good luck. Marc Guardiani <marc@guardiani.com> wrote in message news:<Wmyqc.38565$vz5.34463@nwrdny01.gnilink.net>... > Run the input clock to to clock pins. On one, use the CLKDLL. On the > other, use the IBUFG. (You didn't say you needed that other clock pin > for something else :-). > > Tony Dean wrote: > > > I want my master input clock, which is on a dedicated pin, to clock > > most of my logic through a BUFG. I also want it to drive a CLKDLL so I > > can use the CLK90 output. > > > > After much head-banging I assert the following: > > On a Spartan IIE, an IBUFG output cannot be routed to both a CLKDLL > > input AND a BUFG input simultaneously. > > > > Synplicity will synthesize this setup beautifully, but the Xilinx > > Placer won't accept it. > > > > Yes, I know I could use the CLK0 output through a BUFG instead of my > > original clock, but my input clock can change speeds abruptly, which > > will cause the CLKDLL to unlock and exhibit undefined behavior until > > relocked. This makes me nervous and I'd rather just use my original > > input, thank you. > > > > A double mocha to he or she who can disprove my assertion. > > > > -tdArticle: 69737
Hi *, I use several DCMs in my V2P7-design, and have the following problem: After the FPGA is configured, the input clock is outside of DCM specs (it's somewhere in the 1MHz-range). Of course, the DCMs can't achieve a lock with this. Awhile later (the exact time is unknown) the input clock is switched to 25MHz. In order for the DCMs to lock, I then have to issue an external reset. What I'd like is some way to do this automatically. Normally, I'd use the status(1)-bit from the DCM, which should indicate the input clock was lost while changing. But this bit is obviously only set when a lock was achieved before and the clock is lost after that. If the DCM never locks in the first place, the status-bit is never set. The main problem here is that I don't know exactly when the input clock will be changing, i.e. when I have to issue the reset. Any ideas? Is there some clever way to do this I'm not seeing? cu, SeanArticle: 69738
Hallo, i have a leon Processor and a CAN IP-core. i have connect CAN IP-core to Leon with APB Slave and the whole Model in bitstream File exported. The CAN IP-core has defined 32 Register, which also have in leon the address. Now in the C-Code i want to send a message from CAN IP-core. Do i only need to write the message in Transffer Register from CAN IP-core and just let the CommandRegister from CAN IP-core send the message? and if not, how to send a message and how should i write in the C-code? thanks in advance krebsArticle: 69739
"Jim Granville" <no.spam@designtools.co.nz> schreef in bericht news:mPEqc.2994$FN.310885@news02.tsnz.net... > Goran Bilski wrote: > > It seems that Altera has created a MicroBlaze as well. > > They have finally realized that a FPGA based soft processor should have > > - 32 bit ISA > > - 32 registers > > - 3 operand instruction format > > - JTAG based HW debugging > > - HW divider > > > > The weird register window mechanism from NIOS (is it called NIOS1 now?) > > didn't work well in embedded processing markets. > > I did hear that NIOS II was quite close to the MIPs CPU in > structure/mindset.... And I heared that the old NIOS was a SPARC structure.Article: 69740
On Fri, 14 May 2004 09:04:19 -0700, "Brad Smallridge" <bradsmallridge@dslextreme.com> wrote: >Still looking for some suggestions. hi Brad, yeah, it's the robot vision community you need to talk with. A few years ago I did a blob analysis module that needed only one pass over the pixels. It used a kind of runlength encoding, although in fact you can do the runlength stuff on-the-fly quite easily. My technique coped correctly with arbitrary blob topologies, BUT at the expense of building a fairly complicated tree as the data structure. It was VERY quick (I got a 30x speedup by recoding someone else's blob finder, and mine was more general!). The application was a bit messy - identifying fish on a conveyor belt, so that the de-heading machine could pick them up by the correct end. We used a line-scan camera, with conveyor motion providing the other direction of scan, but the technique is just as good on a 2-dimensional image. The basic algorithm is easy to map onto FPGA because it simply looks once at each pixel, but the problem is that it needs a very variable amount of working storage and FPGAs generally aren't very good at that sort of thing. It's easy only if you can plan in advance what features you want to extract - centre of gravity? centre of gravity of the hull (outermost enclosing blob, including all its holes and any blobs within those holes)? centre of gravity of convex hull (quite a bit harder)? bounding box? It's also VERY helpful if you can provide a nice clean margin to the picture, so that there's an unambiguous "background" area extending to the limits of the useful image. If any blobs overlap the image edges, you need to work out what that means and how to handle it. I'll try to look out the old papers I did on it, although I think the C code is long gone - it wasn't mine to keep. You can guess the vintage because it ran on one of the embedded AMD29K processors (29500?????)... Nice to know that people are still messing with that kind of stuff. -- Jonathan Bromley, Consultant DOULOS - Developing Design Know-how VHDL, Verilog, SystemC, Perl, Tcl/Tk, Verification, Project Services Doulos Ltd. Church Hatch, 22 Market Place, Ringwood, BH24 1AW, UK Tel: +44 (0)1425 471223 mail:jonathan.bromley@doulos.com Fax: +44 (0)1425 471573 Web: http://www.doulos.com The contents of this message may contain personal views which are not the views of Doulos Ltd., unless specifically stated.Article: 69741
I have had this too with a project. When you do a functional simulation, everything is as you want it. I thought this is a feature called "NOT gate push back", and can be turned off. It just a result of logic reduction. On the outside everything it is as it should be. "ALuPin" <ALuPin@web.de> schreef in bericht news:b8a9a7b0.0405182314.45f47d4a@posting.google.com... > Dear Sir or Madam, > > I have some phenomenon I do not know when synthesizing my VHDL > description for my > SRAM controller: > > The .vho-file from Quartus is used for a timing simulation. When I > have a look at internal signals > of my controller like 'l_oe_bar', 'l_cs_bar','l_we_bar' > I see in timing simulation with Modelsim that they are right inverted > to my description, for example are > they resetted to '0' and not to my declared '1' in the VHDL > description. > > The outputs of my controller are concurrently assigned like that: > > OE_bar <= l_oe_bar; > CS_bar <= l_cs_bar; > WE_bar <= l_we_bar; > > And yet they are inverted to the local signals. > > I do not know why there seems to be a double inversion. What does > QuartusII do? > > I would appreciate your help. > > Kind regardsArticle: 69742
jon@beniston.com (Jon Beniston) writes: > Aniket Naik <aniket@tifrpune.res.in> wrote in message news:<Pine.LNX.4.44.0405181824410.6377-100000@tifrpune.res.in>... > > Hi, > > > > I have instantiated a dual port block ram through coregen with a 128 bit > > write only port and a 32 bit read only port. > > > > I am using chipscope to debug the FPGA and when I view all signals > > connected to ram, all write port signals are correct, but the data read > > out from read port is sometimes correct, and other times it is garbage > > data. > > > > Could somebody suggest a solution to this problem. > > Is it a timing problem? (the frequency of operation is low around 10 Mhz) > > Possibly not the same problem, but I've seen issues recently with a > Core Gen RAM not being synthed properly by XST. I switched over to > Synplify and the problem disappeared.. My faith in XST is limited! > I didn't think that Coregen'ed stuff *was* synthesised - does the synth not see it as a black box? Then the downstream tools find the EDIF netlist to fill in the gap.. Cheers, Martin -- martin.j.thompson@trw.com TRW Conekt, Solihull, UK http://www.trw.com/conektArticle: 69743
If you are doing a synchronous design you normally shouldn't run out of clock
resources. What are you doing that uses so many clocks? I suspect your
clocking is also causing your routing woes. The virtex parts have abundant
routing resources; it is not that easy to use them up.
Chuck McManis wrote:
> Lots of responses already so I'll just add a few bits that have been missed
> ...
>
> "Paul Marciano" <pm940@yahoo.com> wrote in message
> news:d5bc3deb.0405181044.7821e99@posting.google.com...
> > 1. I need a device with at least nRegisterBits/2 CLBs.
> > 2. nRegisterBits/2 is probably grossly optimistic.
>
> Actually I've yet to run out of CLBs in anything I've done (not a lot of
> complicated stuff) however you can easily run out of "clock domains" (global
> clocks) routing resources (no way to connect two parts of your design), and
> I/O pins.
>
<snip>
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 69744
Glen,
First off, what is your entry method? An HDL?
You can use the adders and other small macros in coregen, but I wouldn't. If you
don't need placement, let synthesis infer these, but check on the results to make sure
you aren't getting two levels of logic. Synthesis has come a long way in the past 5
or so years. Used to be tht you had to do considerable 'pushing on a rope' to get the
adder structure right. Now, it has gotten much better at recognizing and inferring
the structure. Watch out for add followed by a mux though, tht one still occasionally
trips up the synthesizer.
You are correct, the structure has changed, and you don't get to use the carry chain
in isolation like you could with the 4000 stuff. The 4000 has the carry chain in
front of the LUT which let you use the carry chain as a compare and then use the LUT
as a mux. The virtex architecture has the carry chain after the LUT, and you need the
LUT to connect into the carry chain, so you cannot use the two separately. There are
some cute things you can do with the DI input to the carry mux, but the fact that the
carry mux select is controlled by the LUT is limiting when you try to do other than
straight forward arithmetic.
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 69745Hi! I am searching a synthesizable I2C Slave model in VHDL. Does somebody know where I can find it? Thanks Regards, MatijaArticle: 69746
On 19 May 2004 03:10:58 -0700, kewangke@web.de (krebs) wrote: >i have a leon Processor and a CAN IP-core. i have connect CAN IP-core >to Leon with APB Slave and the whole Model in bitstream File exported. >The CAN IP-core has defined 32 Register, which also have in leon the >address. Now in the C-Code i want to send a message from CAN IP-core. >Do i only need to write the message in Transffer Register from CAN >IP-core and just let the CommandRegister from CAN IP-core send the >message? and if not, how to send a message and how should i write in >the C-code? It entirely depends on the specific CAN core you are using. Surely it came with ample documentation to describe how to do this basic thing? If the core lacks this documentation, please tell us which core so that we may all avoid it in the future. If, however, it has such documentation, then perhaps you can share with us the part that you don't understand. Traditional CAN modules such as the SJA1000 allow you to create a message by writing its contents to registers, as you suggest. You must also remember to configure the identifier and other features of the message. Then you write some kind of "start" command to a control register. The message then probably goes into a FIFO buffer so that it can be sent automatically by the hardware at some future time. There is probably an interrupt output, or a status register, allowing you to determine when the message has been sent. Also, don't forget to check for the many possible error conditions that CAN checks so carefully. -- Jonathan Bromley, Consultant DOULOS - Developing Design Know-how VHDL, Verilog, SystemC, Perl, Tcl/Tk, Verification, Project Services Doulos Ltd. Church Hatch, 22 Market Place, Ringwood, BH24 1AW, UK Tel: +44 (0)1425 471223 mail:jonathan.bromley@doulos.com Fax: +44 (0)1425 471573 Web: http://www.doulos.com The contents of this message may contain personal views which are not the views of Doulos Ltd., unless specifically stated.Article: 69747
Matija wrote: > > Hi! > > I am searching a synthesizable I2C Slave model in VHDL. > Does somebody know where I can find it? Did you check opencores.org? That is always a good place to start. They have a lot of IO peripherals available. -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAXArticle: 69748
"Goran Bilski" <goran@xilinx.com> wrote in message news:c8f3f0$cfe1@cliff.xsj.xilinx.com... > It seems that Altera has created a MicroBlaze as well. > They have finally realized that a FPGA based soft processor should have > - 32 bit ISA > - 32 registers > - 3 operand instruction format > - JTAG based HW debugging > - HW divider > > The weird register window mechanism from NIOS (is it called NIOS1 now?) > didn't work well in embedded processing markets. > > Göran Bilski > > Aren't we lucky to have both X and A? It's kind of like Intel and AMD. We'd still have 386 SX's if AMD weren't tight on Intel's heals. It will be interesting to see where we wind up, but the jump from hardcore to softcore processors is quantum leap IMO. If the reality of NiosII comes even remotely close to the shiny brochure then it will be a very significant step forward. Having worked with the NiosI for about a year now, I wouldn't discount the NiosII hype too quickly. NiosI is pretty close to its hype and the main components of the II (IDE, smaller/faster, bootloader management, version control, single JTAG connection for entire process) address most of my issues. One thing I hope is that using cache on the II doesn't incur the Fmax penalty that it does on the I. Hopefully we'll know soon. Anybody know when the II upgrade kits will ship? KenArticle: 69749
Goran Bilski <goran@xilinx.com> wrote in message news:<c8f3f0$cfe1@cliff.xsj.xilinx.com>... > It seems that Altera has created a MicroBlaze as well. > They have finally realized that a FPGA based soft processor should have > - 32 bit ISA > - 32 registers > - 3 operand instruction format > - JTAG based HW debugging > - HW divider Lol.. Because Xilinx invented RISC didn't they? > The weird register window mechanism from NIOS (is it called NIOS1 now?) > didn't work well in embedded processing markets. Well, you can hardly call it weird (at least one mainstream arch, SPARC, uses it), and in the embedded space, Tensilica have no problems selling their arch, which also features register windows. If you really want to sling some mud, my favourite part is where they talk about "Avoiding processor obsolescence"... Er, hasn't this has just made NIOS obsolete? How long before they change their minds again? Fair play to them, I didn't really think too much of NIOS, but if they really can push 200MHz with this, then I am impressed. Cheers, JonB
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