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Messages from 69800

Article: 69800
Subject: Trying to build simple demo using XPS and XC2VP20
From: Michael Dales <mwd24@thompson.cl.cam.ac.uk>
Date: 20 May 2004 15:03:12 +0100
Links: << >>  << T >>  << A >>
Hi there,

We have a Xilinx HW-AFX-FF1152-300 Proto Board, populated with a 
Virtex-II Pro XC2VP20. We're running XPS 6.1 and Project Navigator 6.1.

I was working through the tutorial PDF Xilinx have for EDK 6.1 using the 
PowerPC as a first project, and unfortunately the XPS Base System Builder 
Wizard does not support the board we have, but I attempted to genereate a 
design for the AFX-FG456, which was supported, and then alter it to suit.

My first attempt involved following the tutorial, with three changes:

1) After the wizard has finished I change the part specification to the 
   XC2VP20 in XPS.

2) I manually modified the contents of the system.ucf file to contain the
   correct pin assignments for the package we had.

3) I altered the C file that comes with the tutorial to suit.

This would then successfully build, generating a netlist in XPS, exporting
it to PN for synthesis, and importing in back and updating the bitstream
with the compiled software. However, this design would fail to download
when we tried it with iMPACT.

Our first guess as to why this is (and if someone can correct me/confim
this I'd be most grateful) is because we'd not specified in XPS anything
for the second processor. In the Xilinx XBERT demo, for the XC2VP20 you
need to use system_2cpu.mhs when building that project, otherwise it won't
download. The only apparent difference between the two mhs files with XBERT
is that the 2cpu version specifies a wrapper for the second PPC, which is 
not connected to anything.

So, back to XPS, I added a second PPC wrapper and connected it up as done
in the XBERT demo (I actually ended up just copy and pasting and adjusting
slightly the second CPU wrapper from the XBERT demo into the system.mhs 
for my trial project). Using this I can generate a netlist in XPS, but
when I now export it to PN and try to generate the design, it fails with
the following error at the mapping stage:

Error:PACK:1195 ppc405_1/ppc405_1/PPC405_i has no output pin.

ppc405_1 is the wrapper for the second cpu (the first being ppc405_0).

I have no idea what this means. Can anyone point out to me the error of
my ways here? Thus far I've not managed to complete the tutorial, so feel
slightly foolish :)

Many thanks in advance,

-- 
Michael Dales
University of Cambridge Computer Laboratory
http://www.cl.cam.ac.uk/~mwd24/

Article: 69801
Subject: Re: Malfunctioning dual port block ram.
From: General Schvantzkoph <schvantzkoph@yahoo.com>
Date: Thu, 20 May 2004 10:47:28 -0400
Links: << >>  << T >>  << A >>
On Tue, 18 May 2004 18:39:36 +0600, Aniket Naik wrote:

> 
> Hi,
> 
> I have instantiated a dual port block ram through coregen with a 128 bit 
> write only port and a 32 bit read only port.
> 
> I am using chipscope to debug the FPGA and when I view all signals 
> connected to ram, all write port signals are correct, but the data read 
> out  from read port is sometimes correct, and other times  it is garbage 
> data.
> 
> Could somebody suggest a solution to this problem.
> Is it a timing problem? (the frequency of operation is low around 10 Mhz)
>  -- 
> Aniket Naik
> Computational Mathematics Laboratory,
> Tata Institute of Fundamental Research,
> India.

Which FPGA are you using? Some Spartan2 parts had some problems with
simultaneous read/writes. I think the 2Es are OK as are the Spartan3s and
Virtex2s.

Are the read and write ports using the same clock?

Are you attempting to simultaneously read and write from the same
address?, if so don't do that.


Article: 69802
Subject: Re: S3 cheap shot
From: "E.S." <emu@ecubics.com>
Date: Thu, 20 May 2004 09:51:59 -0600
Links: << >>  << T >>  << A >>
Austin Lesea wrote:

> Tim,
> 
> Low blow.
> 
> S3 shipped a lot of parts last quarter.  A whole lot of parts.

Sorry Austin,

Just asked, for the xc3s400-fg456 I can get now ces samples.
Probably I can get parts in 14 weeks, so I stay with spartanII.

> No one expected the product to gather that many orders that fast.  Even 
> the optomists among us were made to look like pessimistic fools.
> 
> If we would have only believed our own sales pitch that S3 was a better 
> deal than an ASIC in volume (which it is), we might have been at least 
> partially prepared.

So, xilinx did something right, and it is wrong again ?
;-)

> Austin
> 
> Tim wrote:
> 
>> "Austin Lesea" wrote
>>
>>> At lunch the other day we were reminiscing about how the Z8000 never
>>> took off because they changed their architecture and instruction set
>>> completely from the Z80 and immediately alienated all of their customers
>>> (who were still programming in assembly language in those days).
>> Not quite getting it into production may have troubled some customers...
>>
>>> Not like that anymore.
>> The Spartan-3 of its day ;-)



Article: 69803
Subject: Re: program flash memory through JTAG on FPGA
From: "E.S." <emu@ecubics.com>
Date: Thu, 20 May 2004 10:15:39 -0600
Links: << >>  << T >>  << A >>
Eric Crabill wrote:

> Hi,
> 
> I have no idea what it costs, the students were able
> to make use of the downloadable demo version, and they
> were even offered technical support when they ran into
> trouble...

But it costs more that the ChipScope, and that makes me wonder ;-)

Anyway, I was thinking all the time, that such a tool would be
nice to have from xilinx. They have all the chip definitions in house
already, they sell you the needed JTAG dongles anyway, and have to
update the drivers, so getting something like the picoblaze to program
flash, shouldn't be a big thing. (My guess is, it would be a walk in the 
park for Ken)

And as I have pretty much a PC for doing xilinx parts alone, so it
still works when I need it (no Word,outlook, no viruses,..) I really
try to cut the amount of different packages from diiferent vendors to
minimum.

Just my .2



Article: 69804
Subject: Never right, always room for improvement
From: Austin Lesea <austin@xilinx.com>
Date: Thu, 20 May 2004 09:25:10 -0700
Links: << >>  << T >>  << A >>
ES,

Yes.  Xilinx just can not do anything at all "right."

The most FPGAs shipped in the history of FPGAs (Virtex family), the only 
FPGA with embedded processors, the first FPGA ever with 10 Gbs 
transceivers, lowest interrupt latency of any soft processor core(and 
even better than most hard processors), 40% speed improvement in our 
tools, over 250K seats of software shipped,  XCell Magazine with a 
subscription larger than the premier electronics mag......

Such a bummer, I guess we must just keep striving to be better and better!

Austin


Article: 69805
Subject: Re: How to select an FPGA size (beginner)
From: "Symon" <symon_brewer@hotmail.com>
Date: Thu, 20 May 2004 09:25:49 -0700
Links: << >>  << T >>  << A >>
Just to reinforce what Ray says in his response, if you have designs that
have a lot of input clocks, I have found that some effort up front to retime
these clocks to one higher frequency masterclock (which is clock enabled for
each source clock domain) can often save you from a world of pain later on.
Especially if you're transferring data between domains. The DCMs are great
for making this masterclock.
Cheers, Syms.

"Chuck McManis" <devnull@mcmanis.com> wrote in message
news:IWUqc.51416$fS2.33280@newssvr29.news.prodigy.com...
>
> "...If you are doing a synchronous design ..." but these days people are
> doing SOC designs that might have a video clock, a CPU clock, a clock
> driving an ethernet PHY, and a perhaps some refresh logic for their DRAM
> controller. I'm not disagreeing with you, my point was that "gates" are
> generally not the thing you run out of first.
>



Article: 69806
Subject: Re: program flash memory through JTAG on FPGA
From: "Symon" <symon_brewer@hotmail.com>
Date: Thu, 20 May 2004 09:38:47 -0700
Links: << >>  << T >>  << A >>
It may be pretty easy to do this. I've done a little research, it seems
there's a JTAG language called Serial Vector Format or SVF. Check out
XAPP503. It also appears that iMPACT can play something called XSVF format
files through the Xilinx JTAG cables. There's a utility included with
XAPP058 called SVF2XSVF. Mix together with some Perl scripts, piece of cake,
right? ;-)
Does this make sense? Am I on the right track? Anybody done anything
similar? Like to share your experiences?
cheers, Syms
"E.S." <emu@ecubics.com> wrote in message
news:wN4rc.31$_J1.18@fe39.usenetserver.com...

> Anyway, I was thinking all the time, that such a tool would be
> nice to have from xilinx. They have all the chip definitions in house
> already, they sell you the needed JTAG dongles anyway, and have to
> update the drivers, so getting something like the picoblaze to program
> flash, shouldn't be a big thing. (My guess is, it would be a walk in the
> park for Ken)
>
> And as I have pretty much a PC for doing xilinx parts alone, so it
> still works when I need it (no Word,outlook, no viruses,..) I really
> try to cut the amount of different packages from diiferent vendors to
> minimum.
>
> Just my .2
>
>



Article: 69807
Subject: Altera LP4 Need Help With Device Drivers and Setting Up
From: Derek_SImmons@msn.com (Derek Simmons)
Date: 20 May 2004 09:54:19 -0700
Links: << >>  << T >>  << A >>
I have an Altera LP4 ISA interface board I'm trying to setup to use
with MAX+plus II 9.23. What device drivers do I need to install to use
this board? Will the LP6 Drivers work?

There are also some DIP switches on it. Does anybody know what the set
or control?

I have the pod and I'm going to try to program Altera EPM7256EGC192.
Does anybody know if there is any reason this combination of software
and hardware won't work?

Thanks,
Derek Simmons

Article: 69808
Subject: shift register by block RAM
From: kim.seung@sbcglobal.net (Seung)
Date: 20 May 2004 09:57:21 -0700
Links: << >>  << T >>  << A >>
Can anyone point to the location where the information can be found?
What is the maximum speed one can get from currently availale FPGAs? 
Single clock operation possible ?
Thanks,

Article: 69809
Subject: Re: Xilinx V2P: DCM and changing input clock
From: Austin Lesea <austin@xilinx.com>
Date: Thu, 20 May 2004 10:30:30 -0700
Links: << >>  << T >>  << A >>
Allan,

Good suggestion.

Timely too.

Thanks,

Austin

Allan Herriman wrote:
> On Wed, 19 May 2004 07:48:09 -0700, Austin Lesea <austin@xilinx.com>
> wrote:
> 
> 
>>Sean,
>>
>>Brute force!
>>
>>As long as the locked signal is low, periodically reset the DCM, and see 
>>if the locked signal remains low.
>>
>>It takes a little state machine, and it would have to run off the DCM 
>>CLKIN (which is OK, just assume it is running at 25 MHz to calculate how 
>>many counts you need to wait to make sure that LOCKED has gone high).
>>
>>Also use the CLKIN_STOPPED bit, and if you use the DFS part of the DCM, 
>>use the CLKFX_STOPPED status bit as well (if anything goes wrong, reset 
>>the DCM).
>>
>>(pseudo code below)
>>
>>while CLKIN_STOPPED = 1 (clock is running)
>>
>>     assert (reset for one clock)
>>     wait XX uSec
>>
>>     check DCM:  DCM not operating? (check approp. status)
>>                      assert reset (for one clock)
>>                      wait XX uSec
>>                 else do nothing
>>
>>     wait XX uSec (use one counter for all waits)
>>
>>     go to check DCM
> 
> 
> Hi Austin,
> 
> Is there any fundamental reason why this logic couldn't be built into
> the DCM and be enabled/disabled by a config bit?
> 
> The "wait XX usec" might be a problem, but this could by worked around
> in a number of ways (e.g. by using psclk as a timing reference, etc.)
> 
> I find that having to add this state machine to all DCMs just to get
> them to work reliably is a bit of a pain.
> 
> Regards,
> Allan.

Article: 69810
Subject: Re: Nios II Going Live...
From: jseely@altera.com (Joel A. Seely)
Date: 20 May 2004 10:47:27 -0700
Links: << >>  << T >>  << A >>
In deeply embedded systems (i.e. no RTOS), the use of the windowed
registers is extremely useful due to its speed.  When you start using
the processor in applications that have an RTOS, it's a different
story.  Each time you have to do a context switch, unless the RTOS is
really clever, you have to save out the whole set of registers
associated with the task that is getting swapped out and read in the
set of registers for the task that is getting swapped back in.

Initially soft-core microprocessors on FPGAs were used as simple
control processors by the HW engineers in place of state-machines.  So
only rarely did someone want to run an OS on them.  But as they have
gained more acceptance, engineers want the same tools that other
microprocessors provide.

Having a compiler option allowed you to choose between using the
windowed registers vs. a flat register.  With Nios II we optimized for
size and speed, and the architecture we chose did not use the register
windows.

-Joel-


Jim Granville <no.spam@designtools.co.nz> wrote in message news:<43Qqc.3057$FN.324468@news02.tsnz.net>...
> Goran Bilski wrote:
> 
> > It's creating weird situation in embedding processing where you reach 
> > the limit of the window.
> > There should only be different 3 numbers used as sizes, 0, 1 or infinity.
> > Any other number will creating barriers that will be reach and have 
> > impacts on the system.
> > On reaching the limit of the register window, you have a big chunk of 
> > data to save and load which isn't nice to have when you need to have a 
> > deterministic system.
> 
>   I'm lost - since the register count is finite at around 32 in most RISC
> designs, how does removing a feature improve the situation ?.
> 
>   I don't know the specific NIOS details, but Register window/Frame 
> Pointer/Register Bank select schemes have been around for years, and
> can greatly help code density and reaction speed if done properly.
>   I think sparc had a clever partial frame pointer, that allowed some
> registers to carry calling/return parameters, and some as local variables.
>   The compiler needs 'to be on its toes', but that's a SW
> housekeeping issue.
>   Another nice feature of register frame pointers, is if you are
> uncomfortable with them, you can just ignore it, and you have
> a 'vanilla RISC' core.
> 
> -jg

Article: 69811
Subject: Re: Nios II Going Live...
From: Jim Granville <no.spam@designtools.co.nz>
Date: Fri, 21 May 2004 09:03:12 +1200
Links: << >>  << T >>  << A >>
Joel A. Seely wrote:
> In deeply embedded systems (i.e. no RTOS), the use of the windowed
> registers is extremely useful due to its speed.  When you start using
> the processor in applications that have an RTOS, it's a different
> story.  Each time you have to do a context switch, unless the RTOS is
> really clever, you have to save out the whole set of registers
> associated with the task that is getting swapped out and read in the
> set of registers for the task that is getting swapped back in.

The problem here is because you accept/target a 'less than really 
clever' RTOS, you also compromise the available peak performance.

> 
> Initially soft-core microprocessors on FPGAs were used as simple
> control processors by the HW engineers in place of state-machines.  So
> only rarely did someone want to run an OS on them.  But as they have
> gained more acceptance, engineers want the same tools that other
> microprocessors provide.

...but the first group have not 'gone away' ?

> Having a compiler option allowed you to choose between using the
> windowed registers vs. a flat register.  With Nios II we optimized for
> size and speed, and the architecture we chose did not use the register
> windows.

  One advantage of a FPGA core is you CAN change it as tools evolve :)

One path that appeals for embedded design, is the hyperthread/switched 
CPU approach, that is now appearing in mainstream MPU (and so tools will 
follow, over time ).
  eg Ubicom divide their newest CPU into (IIRC) 64 time slots, and 
tasks/processes can have N,M etc of those slots assigned. Result is good 
granularity of horsepower allocation, and very hard real-time performance.
  With a FPGA, you could assign the hard real time stuff to one Core, 
with register pointer features ON, and running the small, time paranoid 
code.
  Time muxed on the other core, you can run the softer-time stuff, on a 
RTOS, with register pointer features OFF.
  In this approach, you are really multiplexing at the slowest memory 
BUS pivot, rather than context thrashing a single, fast core.
-jg


Article: 69812
Subject: Re: Never right, always room for improvement
From: kempaj@yahoo.com (Jesse Kempa)
Date: 20 May 2004 14:35:39 -0700
Links: << >>  << T >>  << A >>
Austin Lesea <austin@xilinx.com> wrote in message news:<c8im4g$cfc1@cliff.xsj.xilinx.com>...
> ES,
> 
> Yes.  Xilinx just can not do anything at all "right."
> 
> The most FPGAs shipped in the history of FPGAs (Virtex family), the only 
> FPGA with embedded processors, the first FPGA ever with 10 Gbs 
> transceivers, lowest interrupt latency of any soft processor core(and 
> even better than most hard processors), 40% speed improvement in our 
> tools, over 250K seats of software shipped,  XCell Magazine with a 
> subscription larger than the premier electronics mag......
> 
> Such a bummer, I guess we must just keep striving to be better and better!
> 
> Austin

Mr. Lesea, this is not a flame, but to correct an error in your
statement:
 
"the only FPGA with embedded processors" is far from the truth. The
following come to mind immediately (I'm sure I'm forgetting several):
- Nios & Excalibur (Introduced June, 2000, that was FOUR years ago,
and a year ahead of the competition; my how time flies!)
- QuickLogic
- The company you just acquired (I'll leave my theories out of this
post)

All are processors on FPGAs. These are commercial offerings, there are
numerous 3rd party & free cores out there too.

Your comments on ISR latency can be debated if you like, but I won't
get into it now; there is already a thread discussing the
architectural pros & cons that affect this.

Boy, all this stuff makes feel me like I did yesterday when a guy
dropped in on me while surfing.

Regards,

Jesse Kempa
Altera Corp.
jkempa at altera dot com

Article: 69813
Subject: Re: shift register by block RAM
From: Peter Alfke <peter@xilinx.com>
Date: Thu, 20 May 2004 15:30:13 -0700
Links: << >>  << T >>  << A >>
Your question is vague, but here is my answer:
BlockRAM used as shift register:

Simple textbook design at 200 MHz+
with some effort and P/S/P trickery: 300 MHz+
using Virtex-IIPro MGTs: 3000 MHz
can be pushed to 10 gigabits per second.

It all depends on your needs...
Peter Alfke, Xilinx Applications
==========================
Seung wrote:
> 
> Can anyone point to the location where the information can be found?
> What is the maximum speed one can get from currently availale FPGAs?
> Single clock operation possible ?
> Thanks,

Article: 69814
Subject: Re: program flash memory through JTAG on FPGA
From: Bassman59a@yahoo.com (Andy Peters)
Date: 20 May 2004 15:39:07 -0700
Links: << >>  << T >>  << A >>
Petter Gustad <newsmailcomp6@gustad.com> wrote in message news:<87ekpnr2pu.fsf@zener.home.gustad.com>...
> Bassman59a@yahoo.com (Andy Peters) writes:
> 
> > "rat" <rattt@col.edu.cn> wrote in message news:<c7ujmp$1phn$1@mail.cn99.com>...
> > > Hi,
> > >   In my design, there is a flash memory chip connecting to fpga chip, I want
> > > to program the flash memory through the JTAG port on the FPGA, where can I
> > > find some introduction?
> > 
> > I don't think it's possible to do this.  The FPGA JTAG ports are
> > dedicated to boundary scan, and in the case of CPLDs, are used for
> > device programming.  You can't access the JTAG controller directly in
> > FPGA logic.
> 
> Look at Jim's message. You can control all the IO's on the FPGA
> through the FPGA. Then you can apply patterns on the pins connected to
> the flash to program it. In general you can do this with most JTAG
> devices. I've programmed I2C proms through the JTAG port of on of our
> ASICs. The tricky part is to generate the JTAG patterns to do the
> programming.

Ah, neat!  I didn't know you could do that.  Learn something new every day...

-a

Article: 69815
Subject: Re: Never right, always room for improvement
From: "Tim" <tim@rockylogic.com.nooospam.com>
Date: Fri, 21 May 2004 00:09:34 +0100
Links: << >>  << T >>  << A >>
Austin Lesea wrote:

>    lowest interrupt latency of any soft processor core (and
> even better than most hard processors)

that must be red rag to a bull for john jackson and the other
transputer folk.

and why are there so many transputer people in fpgaland?



Article: 69816
Subject: Re: Nios II Going Live...
From: "Kenneth Land" <kland1@neuralog1.com1>
Date: Thu, 20 May 2004 18:11:41 -0500
Links: << >>  << T >>  << A >>

"Joel A. Seely" <jseely@altera.com> wrote in message
news:9bded7a8.0405200947.28b2d90c@posting.google.com...
> In deeply embedded systems (i.e. no RTOS), the use of the windowed
> registers is extremely useful due to its speed.  When you start using
> the processor in applications that have an RTOS, it's a different
> story.  Each time you have to do a context switch, unless the RTOS is
> really clever, you have to save out the whole set of registers
> associated with the task that is getting swapped out and read in the
> set of registers for the task that is getting swapped back in.
>
> Initially soft-core microprocessors on FPGAs were used as simple
> control processors by the HW engineers in place of state-machines.  So
> only rarely did someone want to run an OS on them.  But as they have
> gained more acceptance, engineers want the same tools that other
> microprocessors provide.
>
> Having a compiler option allowed you to choose between using the
> windowed registers vs. a flat register.  With Nios II we optimized for
> size and speed, and the architecture we chose did not use the register
> windows.
>
> -Joel-
>
>

Hi Joel,

(trying to tune out the trolls here)
I'm going to be porting what you call a "deeply embedded" interrrupt driven
application from NiosI to NiosII shortly.  Can you contrast the two in terms
of interrupt latency?

The app was originally developed on a dual coldfire system and I can say a
single Cyclone based NiosI handles things very nicely.  I'm looking forward
to the new IDE and even more performance.

Whatever the naysayer's say,  Motorola is not sending me a new higher
performance cpu to download to my *existing boards*.  This is great stuff!

TIA,
Ken




Article: 69817
Subject: Re: Never right, always room for improvement
From: Austin Lesea <austin@xilinx.com>
Date: Thu, 20 May 2004 16:20:05 -0700
Links: << >>  << T >>  << A >>
Jesse,

Processors, plural.

I'm still right.

Austin

Jesse Kempa wrote:
> Austin Lesea <austin@xilinx.com> wrote in message news:<c8im4g$cfc1@cliff.xsj.xilinx.com>...
> 
>>ES,
>>
>>Yes.  Xilinx just can not do anything at all "right."
>>
>>The most FPGAs shipped in the history of FPGAs (Virtex family), the only 
>>FPGA with embedded processors, the first FPGA ever with 10 Gbs 
>>transceivers, lowest interrupt latency of any soft processor core(and 
>>even better than most hard processors), 40% speed improvement in our 
>>tools, over 250K seats of software shipped,  XCell Magazine with a 
>>subscription larger than the premier electronics mag......
>>
>>Such a bummer, I guess we must just keep striving to be better and better!
>>
>>Austin
> 
> 
> Mr. Lesea, this is not a flame, but to correct an error in your
> statement:
>  
> "the only FPGA with embedded processors" is far from the truth. The
> following come to mind immediately (I'm sure I'm forgetting several):
> - Nios & Excalibur (Introduced June, 2000, that was FOUR years ago,
> and a year ahead of the competition; my how time flies!)
> - QuickLogic
> - The company you just acquired (I'll leave my theories out of this
> post)
> 
> All are processors on FPGAs. These are commercial offerings, there are
> numerous 3rd party & free cores out there too.
> 
> Your comments on ISR latency can be debated if you like, but I won't
> get into it now; there is already a thread discussing the
> architectural pros & cons that affect this.
> 
> Boy, all this stuff makes feel me like I did yesterday when a guy
> dropped in on me while surfing.
> 
> Regards,
> 
> Jesse Kempa
> Altera Corp.
> jkempa at altera dot com

Article: 69818
Subject: Re: program flash memory through JTAG on FPGA
From: kempaj@yahoo.com (Jesse Kempa)
Date: 20 May 2004 17:29:47 -0700
Links: << >>  << T >>  << A >>
"rat" <rattt@col.edu.cn> wrote in message news:<c7ujmp$1phn$1@mail.cn99.com>...
> Hi,
>   In my design, there is a flash memory chip connecting to fpga chip, I want
> to program the flash memory through the JTAG port on the FPGA, where can I
> find some introduction?
>   Thanks a lot!
> 
> Regards


If you're using an Altera FPGA (Stratix/Cyclone, etc.), and a common
flash interface (CFI)-compliant flash device, you might consider
giving Nios II (released this week) a try for your programming needs.
It includes a CFI flash interface component and flash programmer that
operates via JTAG as you describe. Built-in support exists for Altera
Nios dev boards, and there is an document describing how to customize
the flash-programmer for your own board.

If you're interested, check out chapter 13 of the Processor Reference
Manual and the Flash Programmer User guide here:
http://www.altera.com/literature/lit-nio2.jsp

Regards,

Jesse Kempa
Altera Corp.
jkempa at altera dot com

Article: 69819
Subject: Re: Never right, always room for improvement
From: rickman <spamgoeshere4@yahoo.com>
Date: Thu, 20 May 2004 21:41:20 -0400
Links: << >>  << T >>  << A >>
Austin Lesea wrote:
> 
> ES,
> 
> Yes.  Xilinx just can not do anything at all "right."
> 
> The most FPGAs shipped in the history of FPGAs (Virtex family), the only
> FPGA with embedded processors, the first FPGA ever with 10 Gbs
> transceivers, lowest interrupt latency of any soft processor core(and
> even better than most hard processors), 40% speed improvement in our
> tools, over 250K seats of software shipped,  XCell Magazine with a
> subscription larger than the premier electronics mag......
> 
> Such a bummer, I guess we must just keep striving to be better and better!

I am just curious Austin, do you think this message helped either you or
Xilinx?  

-- 

Rick "rickman" Collins

rick.collins@XYarius.com
Ignore the reply address. To email me use the above address with the XY
removed.

Arius - A Signal Processing Solutions Company
Specializing in DSP and FPGA design      URL http://www.arius.com
4 King Ave                               301-682-7772 Voice
Frederick, MD 21701-3110                 301-682-7666 FAX

Article: 69820
Subject: Re: Nios II Going Live...
From: Richard Pennington <rich@pennware.com>
Date: Fri, 21 May 2004 01:42:20 GMT
Links: << >>  << T >>  << A >>
Goran Bilski wrote:
> It seems that Altera has created a MicroBlaze as well.
> They have finally realized that a FPGA based soft processor should have
> - 32 bit ISA
> - 32 registers
> - 3 operand instruction format
> - JTAG based HW debugging
> - HW divider
> 
> The weird register window mechanism from NIOS (is it called NIOS1 now?) 
> didn't work well in embedded processing markets.
> 
> Göran Bilski

Actually, it works quite well if used correctly. It isn't used correctly 
in the implementations I've seen (from Altera and from an OS vendor).
I modified the OS to change the register spill strategy: Rather than 
spilling the entire register set, we only spill one register frame. 
Restores are done normally. This results in a "run time optimization" of
the top of the register window forprograms. This works very well in 
practice because after initialization and task startup, a task's 
register window is at the top of the register file. For a 256 register 
file that means you get 14 function calls before a register spill occurs.

I'm a little sad that we'll lose the register windows in Nios2. 
Performance, etc. will make up for it. ;-)

-Rich


Article: 69821
Subject: Re: Internal Signals and other questions with ModelSim XE/II Starter 5.7g VHDL Testbench
From: "Charles Bailey" <ceb_misc@ultrasw.com>
Date: Thu, 20 May 2004 20:45:56 -0700
Links: << >>  << T >>  << A >>

"Martin Maurer" <capiman@clibb.de> wrote in message
news:c87uts$tbn$05$1@news.t-online.com...
> Hello,
>
> i am trying to learn how to use ModelSim with a VHDL Testbench, but i
don't
> find any answers on a few of my answers.
> At the moment i start ModelSim always via "Simulate Post-Translate
VHDL"
> from Xilinx Project Navigator.
>
> 1) I can see all my stimuli, which are mainly the external in- and
outputs.
> They seems to toggle fine. But how can i display the internal signals
? Is
> the only solution to assign a port to an internal signal to see it in
> ModelSim. I already tried to simply define new signals, they are drawn
in
> ModelSim, but it seems they are not connected to the real signals. I
think i
> was able to add internal signals via "Signal" window, but next time i
> simulate the signal was lost again...
Under the File menu of the waveform window there are options for saving
the current display format, including the signals you have displayed,
and then restoring it again later.

> 2) I am currently can simulate my design once. When i external edit my
vhdl
> source or testbench i always must close ModelSim and restart it via
Xilinx
> Projects Manager. If i don't close it, i get an error message, that
> "ModelSim is already running". Is there a more convenient way ?
Yes.  I find ModelSim to be very convenient and friendly.
Define a "project" (read the help text).  Add your VHDL files to the
project.  After you edit one of the files, click on the Project tab.  A
question mark will appear by the file if has been changed since you last
compiled it.  Select the file and click the Compile button.  At the
ModelSim command prompt enter "restart -f".  The simulation will be
restarted and ModelSim will load the newly compiled versions of any
files that have changed.

> 3) I found a few nice commands like "view wave", "add wave *". Is
there a
> command for full zoom ?
Click anywhere in the waveform window and press "f".  There are also
menu buttons for doing this.
> Where can i say, that certain commands should be
> executed e.g. after drawing of a wave ?
You can put any sequence of commands you want into a "do" file.

> 4) Every time when i open ModelSim the wave window is only a small
window,
> positioned at right/lower corner of my screen. I already edited the
wave
> window "geometry", saved it to default name modelsim.tcl of my project
> directory. But on next restart same windows size and position as
before.
> Must i move this file to a certain position. Is there a command like
"use
> preferences" that i can execute like in question 3 ?
Size the windows the way you want them.  Click Tools -> Save
Preferences -> Save.

> 5) In my vhdl source file i use a "std_ulogic_vector", because i want
to use
> tristate pins, for bidirectional data transfer of data. In the
testbench the
> xilinx tool created a testbench with "std_logic_vector". It compiles
fine.
> When i change it to "std_ulogic_vector" in testbench, ModelSim brings
a
> compile error, that source and testbench does not fit together. I
already
> use 'Z' for assignments and it seems to work. Should i just ignore
this or
> must i pay attention when doing it this way ? ModelSim can handle
tristate
> logic ?
You should use std_logic_vector, not std_ulogic_vector, for
bidirectional buses.
You can connect std_logic to std_ulogic, but you can't connect
std_logic_vector to std_ulogic_vector without using a conversion
function.  The ieee.std_logic_1164 package comes with functions for
doing these conversions.  Look in the package.

> 6) Is there a FAQ for such questions ?
>
> So enough for now,
>
>                   Martin Maurer
>
>



Article: 69822
Subject: FREQUENCY DOUBOULER BY MAX PLUS......
From: ftls1@uaf.edu (ftls1@uaf.edu)
Date: 20 May 2004 20:59:00 -0700
Links: << >>  << T >>  << A >>
HI,ALL~

NOW I WANT TO DOUBLE A CLOCK OF 50HZ WITH UNCERTAIN LEADING EDGES,
ACTUALLY THIS IS A FEEDBACK SIGNAL FROM AN EXTERNAL INPUT,HOW CAN I
GET A PRECISE OUTPUT OF 100HZ CLOCK?

I'VE SEARCHED THE MAX PLUS II, I COULDN'T FIND APEX 20K SERIES
DEVICES, THAT MEANS I MUST USE THE PLL OR CLKLOCK FOR APEX 10K?
HOW TO USE THOSE DEVICES? COULD SOME GENTALMEN OR LADY GIVE ME A
EXAMPLE TO SHOW HOW TO DEFINE THE PINS PARAMETERS?

ONLY QUARTUS II HAS THE 20K SERIES DEVICES, IS IT TRUE?

NOW I JUST USE A 8-BIT-COUNTER TO GENERATE A 100 HZ SIGNAL BY A 5KHZ
CLOCK, HOWEVER, THIS IS NOT LOCKED TO THE 50HZ,THERE WOULD BE A PHASE
DELAY BETWEEN LEADING EDGES OF BOTH TWO.

BY THE WAY, DO YOU GUYS KNO ANY AVAILABLE 16-BIT-SYNCHRONIZER-COUNTER
IN MAX PLUS II? I WANT TO GET A 50-50 DUTY CYCLE SIGNAL BY
16-BIT-COUNTER, ANY GREY CODE OR OTHERS WOULD BE OKEY FOR ME.



ADV-THANKS-ANCE~

FTLS1@UAF.EDU

Article: 69823
Subject: Xilinx hypertransport lite reference design.
From: aniket@tifrpune.res.in (Aniket)
Date: 20 May 2004 23:15:37 -0700
Links: << >>  << T >>  << A >>
Hi all,

Has anybody used the hypertransport lite reference design provided by
Xilinx.

I cant seem to get it to work.
I unzipped the design and changed the synthesis tool to xst.

The VHDl design dosent synthesize and the verilog version synthesizes
but when the simulator is run it gives a message " Error: received
data does not match expected data".

Does anybody know the solution to this. Do any other settings need to
be made?


thanks,
Aniket

-- 
Aniket Naik
Computational Mathematics Laboratory,
Tata Institute of Fundamental Research,
India

Article: 69824
Subject: Re: Never right, always room for improvement
From: Jonathan Bromley <jonathan.bromley@doulos.com>
Date: Fri, 21 May 2004 08:44:23 +0100
Links: << >>  << T >>  << A >>
On Fri, 21 May 2004 00:09:34 +0100, "Tim"
<tim@rockylogic.com.nooospam.com> wrote:

>Austin Lesea wrote:
>
>>    lowest interrupt latency of any soft processor core (and
>> even better than most hard processors)
>
>that must be red rag to a bull for john jackson and the other
>transputer folk.

Tee hee.  Interrupt latency is a joke number.  I wrote a
piece about twelve years ago for one of the embedded-system 
comics, pointing out how insignificant is the processor's 
own interrupt latency - there are many things that are 
orders of magnitude more important to interrupt performance.
Here as in many other things, the transputer was on the
right track.  Sadly, limitations of design culture and
available technology doomed it to commercial failure.

Just for the record, here's Bromley's First and Second Law 
of commercial failure in a technological product:

First Law:
  Probability of commercial failure is increased if the
  product meets any of the following criteria:
  1) It employs concepts and techniques that will become
     popular more than a decade later.
  2) Its design is based on technically, logically or
     mathematically sound principles.
  3) Its creators are British.

Second Law:
  The probability of commercial failure is unity if two
  or more of the above criteria are met.

>and why are there so many transputer people in fpgaland?

Perhaps because they know a good thing when they see one?

Getting more and more cynical as time rolls by...
-- 
Jonathan Bromley, Consultant

DOULOS - Developing Design Know-how
VHDL, Verilog, SystemC, Perl, Tcl/Tk, Verification, Project Services

Doulos Ltd. Church Hatch, 22 Market Place, Ringwood, BH24 1AW, UK
Tel: +44 (0)1425 471223          mail:jonathan.bromley@doulos.com
Fax: +44 (0)1425 471573                Web: http://www.doulos.com

The contents of this message may contain personal views which 
are not the views of Doulos Ltd., unless specifically stated.



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