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Messages from 69875

Article: 69875
Subject: Re: Transputer on FPGA
From: johnjakson@yahoo.com (john jakson)
Date: 22 May 2004 21:15:10 -0700
Links: << >>  << T >>  << A >>
rickman <spamgoeshere4@yahoo.com> wrote in message news:<40AFC172.C49E27FA@yahoo.com>...
> "E.S." wrote:
> > 
> > Tim wrote:
> > 
> > > and why are there so many transputer people in fpgaland?
> > 
> > May I rephrase it, and make a question out ot it ?
> > Are the any transputer loke-a-likes WORKING on an FPGA ?
> 
> Interesting question.  I am giving some consideration to inserting my
> own cpu into an FPGA to be programmed in Forth.  I remember the
> Transputer architecture and instruction set as being well suited to
> implementing a stack language as well as being rather minimal.  But I
> can't find my copy of the instruction set reference manual.  Anyone know
> where I can find a copy? 
> 
> 


I just realised, you probably don't need to look at the Transputer
because it has no sp type stack that you'd need for Forth, Pascal, C
etc. It does have a HW stack for eval expressions just like a HP RPN
calc but it is only 3 reg deep and tied into the scheduler for
switching processes when its empty IIRC..

The reason of course is the same as HDL, do Verilog or VHDL allow you
to write code that is stack based or implies recursion, no. Occam
being parallel is more like a HDL, think HW and not seq stack scopes.
For same reason I have no sp either. Infact although Occam allows
functions IIRC it forbid recursion because the compiler had to know in
advance how to lay out memory as much as youd floorplan cells.
Functions can still work with out an sp but other memory management
techniques are called for.

A google for Transputer & Forth should draw a blank I'd guess but I
could be wrong.

Yes it does look like they did it, well I wonder what they did?

regards

johnjakson_usa_com

Article: 69876
Subject: Re: Transputer on FPGA
From: John Doty <jpd@whispertel.LoseTheH.net>
Date: Sat, 22 May 2004 22:39:45 -0600
Links: << >>  << T >>  << A >>
john jakson wrote:

> A google for Transputer & Forth should draw a blank I'd guess but I
> could be wrong.
> 
> Yes it does look like they did it, well I wonder what they did?

It could be done, but it wouldn't be efficient. You'd have to implement 
a separate software number stack.

-jpd


Article: 69877
Subject: Re: More fun with VHDL
From: george_mercury@hotmail.com (George)
Date: 22 May 2004 22:34:43 -0700
Links: << >>  << T >>  << A >>
I see that you are using a < comparator to generate pwm. Although this
works OK it takes quite a lot of logic to implement ( see the RTL
schematics and it will all become clear to you ). Some time ago i
needed a six chanel 8 bit pwm generator. I used the 95108, and with <
comparators it wouldn't fit. So I used annother method - compare
match. The basic idea is that you don't need to know if the pwm data
is less that set data, just if they are equal ( == comparator ), which
takes a lot less logic. I created a counter entitiy with clk input and
8 bit counter output. This counter is common to all six pwm
generators. Although you need a serial load generator, I am stil
including my code for a parallel load. But is should be easy for you
to modify it into a serial.

str is strobe signal for the latch
Din is 8 bit parallel data input
duty_cycle is the latched input data
Cin is the 8 bit counter input 8
Clk is the main clock, also used by the counter
pwm is the PWM output

-- data latch
p00: process(rst,str)
begin
	if rst = '1' then
		duty_cycle <= "00000000";
	elsif str'event and str = '1' then
		duty_cycle <= Din;
	end if;
end process;		


-- pwm comparator
p01: process(clk,rst)
begin
	if rst = '1' then
		pwm <= '0';
	elsif clk'event and clk = '1' then
		if Cin = "11111111" then
			pwm <= '1';
		elsif Cin = duty_cycle then
			pwm <= '0';
		end if;
	end if;
end process;


Best regards to you all,
George Mercury

Article: 69878
Subject: Re: Xilinx V2P: DCM and changing input clock
From: Allan Herriman <allan.herriman.hates.spam@ctam.com.au.invalid>
Date: Sun, 23 May 2004 16:24:18 +1000
Links: << >>  << T >>  << A >>
On Thu, 20 May 2004 10:30:30 -0700, Austin Lesea <austin@xilinx.com>
wrote:

>Allan,
>
>Good suggestion.
>
>Timely too.
>
>Thanks,
>
>Austin


Hi Austin,

Are you hinting that this feature may be added in future silicon?

Regards,
Allan.



>Allan Herriman wrote:
>> On Wed, 19 May 2004 07:48:09 -0700, Austin Lesea <austin@xilinx.com>
>> wrote:
>> 
>> 
>>>Sean,
>>>
>>>Brute force!
>>>
>>>As long as the locked signal is low, periodically reset the DCM, and see 
>>>if the locked signal remains low.
>>>
>>>It takes a little state machine, and it would have to run off the DCM 
>>>CLKIN (which is OK, just assume it is running at 25 MHz to calculate how 
>>>many counts you need to wait to make sure that LOCKED has gone high).
>>>
>>>Also use the CLKIN_STOPPED bit, and if you use the DFS part of the DCM, 
>>>use the CLKFX_STOPPED status bit as well (if anything goes wrong, reset 
>>>the DCM).
>>>
>>>(pseudo code below)
>>>
>>>while CLKIN_STOPPED = 1 (clock is running)
>>>
>>>     assert (reset for one clock)
>>>     wait XX uSec
>>>
>>>     check DCM:  DCM not operating? (check approp. status)
>>>                      assert reset (for one clock)
>>>                      wait XX uSec
>>>                 else do nothing
>>>
>>>     wait XX uSec (use one counter for all waits)
>>>
>>>     go to check DCM
>> 
>> 
>> Hi Austin,
>> 
>> Is there any fundamental reason why this logic couldn't be built into
>> the DCM and be enabled/disabled by a config bit?
>> 
>> The "wait XX usec" might be a problem, but this could by worked around
>> in a number of ways (e.g. by using psclk as a timing reference, etc.)
>> 
>> I find that having to add this state machine to all DCMs just to get
>> them to work reliably is a bit of a pain.
>> 
>> Regards,
>> Allan.

Article: 69879
Subject: Re: Altium FPGA board
From: "Leon Heller" <leon_heller@hotmail.com>
Date: Sun, 23 May 2004 08:42:37 +0100
Links: << >>  << T >>  << A >>
"Chuck McManis" <devnull@mcmanis.com> wrote in message
news:4ASrc.55752$1G4.10014@newssvr29.news.prodigy.com...
> I just got the Altium flyer in the mail today and they are offering a free
> Nanoboard (with the purchase of their overpriced CAD package :-) The
> Nanoboard actually looks pretty cool, has anyone used one?

I subscribe to the PEDA mailing list for users of Protel in its various
incarnations, just for schadenfreude - I don't use it. I vaguely remember
someone offering their 'free' Nanoboard for sale. 8-) Altium has just
announced a couple of new daughterboards for it.

Leon
-- 
Leon Heller, G1HSM
http://www.geocities.com/leon_heller



Article: 69880
Subject: Re: Transputer on FPGA
From: andrew29@littlepinkcloud.invalid
Date: Sun, 23 May 2004 08:53:56 -0000
Links: << >>  << T >>  << A >>
In comp.lang.forth John Doty <jpd@whispertel.losetheh.net> wrote:
> john jakson wrote:

>> A google for Transputer & Forth should draw a blank I'd guess but I
>> could be wrong.
>> 
>> Yes it does look like they did it, well I wonder what they did?

> It could be done, but it wouldn't be efficient. 

I did it, and it was pretty fast.  The top of the stack was cached in
the internal register stack and flushed to the workspace when full and
in a few other cases.

Andrew.

Article: 69881
Subject: Re: Transputer on FPGA
From: albert@spenarnc.xs4all.nl (Albert van der Horst)
Date: Sun, 23 May 2004 10:15:21 GMT
Links: << >>  << T >>  << A >>
In article <adb3971c.0405222015.4821eb9@posting.google.com>,
john jakson <johnjakson@yahoo.com> wrote:

<SNIP>
>I just realised, you probably don't need to look at the Transputer
>because it has no sp type stack that you'd need for Forth, Pascal, C
>etc. It does have a HW stack for eval expressions just like a HP RPN
>calc but it is only 3 reg deep and tied into the scheduler for
>switching processes when its empty IIRC..

It is not the stack (or a stack). These are registers at the lowest
level, almost a RISC way to write microcode explicitly.
The register at the next to lowest level are 16, and you can add two
registers and put it back in a third by 3 single byte instructions.
You can use a couple of those for stack pointers, without exhausting
resources, like in a Pentium.

<SNIP>
>
>A google for Transputer & Forth should draw a blank I'd guess but I
>could be wrong.

Of course you are wrong.
You should know by now, that there is a Forth for every processor
that is over 6 month old.

tforth is the precursor is iforth, and it is still available from DFW.
It is a solid piece of work, if I may say so myself.
There are more.

>Yes it does look like they did it, well I wonder what they did?
>
>regards
>
>johnjakson_usa_com
-- 
Albert van der Horst,Oranjestr 8,3511 RA UTRECHT,THE NETHERLANDS
        One man-hour to invent,
                One man-week to implement,
                        One lawyer-year to patent.

Article: 69882
Subject: Re: Transputer on FPGA
From: johnjakson@yahoo.com (john jakson)
Date: 23 May 2004 07:26:37 -0700
Links: << >>  << T >>  << A >>
andrew29@littlepinkcloud.invalid wrote in message news:<10b0pl4kcqiot99@news.supernews.com>...
> In comp.lang.forth John Doty <jpd@whispertel.losetheh.net> wrote:
> > john jakson wrote:
>  
> >> A google for Transputer & Forth should draw a blank I'd guess but I
> >> could be wrong.
> >> 
> >> Yes it does look like they did it, well I wonder what they did?
>  
> > It could be done, but it wouldn't be efficient. 
> 
> I did it, and it was pretty fast.  The top of the stack was cached in
> the internal register stack and flushed to the workspace when full and
> in a few other cases.
> 
> Andrew.

Well people will find away to do whatever crazy thing they have in mind:)

regards

johnjakson_usa_com

Article: 69883
Subject: Re: More fun with VHDL
From: Peter Wallace <pcw@karpy.com>
Date: Sun, 23 May 2004 10:29:15 -0700
Links: << >>  << T >>  << A >>
On Sat, 22 May 2004 11:59:07 -0700, Chuck McManis wrote:


> 1) I don't get "full" PWM. This is because the pwm process is forced to
> use either < or > If I want to support both 0% on (output stays low) and
> 100% on, (output stays high), I need an additional statement to cover
> that.
> 
> I can modify pwm as follows:
>   pwm: process is (pwm_count, serial_data) is begin
>     if (serial_data = "11111111") then
>         pwm_out <= '1';
>     elsif (pwm_count < serial_data) then
>         pwm_out <= '1';
>     else
>         pwm_out <= '0';
>     end if;
>   end process;
> 
> Assuming the original code inferred an 8 bit comparator, I'd guess the
> above code would then infer an 8 bit and gate whose output is OR'd into
> the output of the comparator (at least that is what I'd do). But it
> seems like I should be able to save the two macrocells this is going to
> eat by changing the logic of the inferred comparator to include an
> output of '1' when all inputs are 1.


It looks like that would cause a discontinuity from 254/256 duty to
256/256. I guess that would bother me more that not getting to 100% on.



> 
> 2) The second problem is that I would really like the pwm output to
> change exactly on the period boundary. Now I started this with a simple
> state machine where a new input set a latch to tell me to change, and
> then added that into the sensitivity list of the pwm function like so:
> 
>   ld: process (serial_load) is
>   begin
>       if rising_edge(serial_load) then
>           new_data <= '1';
>       end if;
>   end process;
> 
>   pwm: process is (pwm_count, pwm_data, new_data) is begin
>     if (new_data = '1') and (pwm_count = "11111111") then
>         pwm_data <= serial_data;
>         new_data <= '0';
>     elsif (pwm_data = "11111111") then
>         pwm_out <= '1';
>     elsif (pwm_count < pwm_data) then
>         pwm_out <= '1';
>     else
>         pwm_out <= '0';
>     end if;
>   end process;
> 
> 
> This is designed to create a simple state machine between the ld and pwm
> processes such that if there is new data, then that data is loaded when
> the count is full. However I'm getting errors trying to synthesize this.
> Basically XST doesn't like the way I'm assigning new_data in different
> processes (although as an engineer it makes sense to me, I'd like to
> infer and R/S flip flop and have pwm_count & new_data drive its "R"
> input and "serial load" drive its "S" input. Trying to use this:
>     ld: process (serial_load) is
>     begin
>         if serial_load = '1' then
>             new_data <= '1';
>         end if;
>     end process;
> 
> Leads to the case where holding serial load high through a full PWM cyle
> would cause both R/S to be asserted. So I tried to infer something like
> a modified T flip flop to set it on the clock edge. Thoughts anyone?
 
Since you probably have a high speed clock for the PWM, I would probably
just use that for everything, as long as your serial clock was enough
lower, then you would have a fully synchonous system which would avoid
a number or problems. 

As others have pointed out there are some simpler ways to generate PWM:

one is the  = comparator and SR flipflop

There is also a way for N bit PWM that uses a N+1 bit accumulator where the N+1
bit is used as the PWM output. 

This design has the advantage that it does not require a reference
counter and that the input can be changed asyncronously relative to the
PWM period and the output will be correct (its kind of an intergrating
PWM source)

The comparator method has the advantage that if you want to filter the
PWM (say to generate a audio signal) you can easily generate interleaved 
PWM by bit reversing any desired number of reference count MSBs


Peter Wallace

Article: 69884
Subject: Re: OT: Electronics learner kit?
From: electron man <noone@aol.com>
Date: Sun, 23 May 2004 17:46:24 GMT
Links: << >>  << T >>  << A >>



Ray;

this site is very good on the discussion of electronics and would be a good
intro tool to help with the project work.
it's explanations are very accurate:
http://www.allaboutcircuits.com/

this one seems to be the same:
http://www.ibiblio.org/obp/electricCircuits/index.htm

here's another one that's cool:
http://www.interq.or.jp/japan/se-inoue/e_menu.htm

-e-man


Ray Andraka wrote:

> I got this one:
> http://www.radioshack.com/product.asp?catalog%5Fname=CTLG&product%5Fid=28-280
> for my son.  It looks pretty comprehensive.
>
> Zspider wrote:
>
> > My daughter will be a high school junior next year.  Over the
> > summer she is wanting to play with electronics in preparation
> > for an electronics engineering degree.  I thought about brute-
> > forcing our way through simple Ohm's Law stuff and then I
> > thought I'd use a simple radio circuit to work with amplification
> > and filters, and then do some simple 7400 digital stuff, but
> > it will take me a lot of time to crank that all out from
> > scratch.  In the summer I don't have that kind of time.
> >
> > Where can I find a good electronics learning kit?
> >
> > Thank you, Michael
>
> --
> --Ray Andraka, P.E.
> President, the Andraka Consulting Group, Inc.
> 401/884-7930     Fax 401/884-7950
> email ray@andraka.com
> http://www.andraka.com
>
>  "They that give up essential liberty to obtain a little
>   temporary safety deserve neither liberty nor safety."
>                                           -Benjamin Franklin, 1759




Article: 69885
Subject: is RAMbus going to resurect itself as another DDR2 format?
From: electron man <noone@aol.com>
Date: Sun, 23 May 2004 17:48:02 GMT
Links: << >>  << T >>  << A >>
i wonder?


Article: 69886
Subject: strange behaviour of the design
From: sameer.gandhi@wipro.com (sameer)
Date: 23 May 2004 11:15:10 -0700
Links: << >>  << T >>  << A >>
hi geeks,

I have been using the xilinx foundation 5.2i and 4.2i. The design used
to work on board with both these versions earlier. But now with a few
additions to the code/design , the code some times works with 4.2i but
never with 5.2i.

I brought out (on the board) the internal signals ,but very strange
behaviour is seen, which is very absurd e.g. the signals required for
the state machine to go to the next state are generated, but the state
machine remains in the same state . Another example :- a signal has to
be set under certain conditions, this conditions are seen on the debug
pins, but still the signal is not set. Here there is no timing issue,
all the timigs are met .

I am really clue less as the synth/ warnings are also inconclusive. Is
it due to some fanout related issue (tool didnt issue any warning abt
it though..)

If anybody has faced similar problem ?

Article: 69887
Subject: Re: Altium FPGA board
From: Rene Tschaggelar <none@none.net>
Date: Sun, 23 May 2004 21:37:01 +0200
Links: << >>  << T >>  << A >>
Chuck McManis wrote:

> I just got the Altium flyer in the mail today and they are offering a free
> Nanoboard (with the purchase of their overpriced CAD package :-) The
> Nanoboard actually looks pretty cool, has anyone used one?

The Nexar package is not really that overpriced. It allows to develop
FPGAs with a 8051 kernel built in, with debugger, compiler, everything.
No, I didn't get Nexar and nanoboard yet. I'm glad to have left the 8051
architecture with just one pointer register behind me. I'm also not a 
friend of C compilers either and am therefore happy with an AVR and 
something else but C.
The low number of units I ship doesn't forbid to have an FPGA plus an
AVR on a board. That may change from a certain number of units upward, 
though.

Rene
-- 
Ing.Buero R.Tschaggelar - http://www.ibrtses.com
& commercial newsgroups - http://www.talkto.net

Article: 69888
Subject: Re: I2C Slave
From: Bassman59a@yahoo.com (Andy Peters)
Date: 23 May 2004 12:39:54 -0700
Links: << >>  << T >>  << A >>
"Matija" <matija.habek@fer.hr> wrote in message news:<c8fkrc$lc4$1@bagan.srce.hr>...

> I am searching a synthesizable I2C Slave model in VHDL.
> Does somebody know where I can find it?

I looked around for the same but written in Verilog.  Never found one
(I looked at the opencores master model but I don't trust it), so I
ended up writing one.

Part of the complication is what kind of slave you're trying to
implement.  For example, imagine you'd like to simply implement an I2C
slave RAM.  That differs from, say, implementing a clone of the
Philips PCF8574 8-bit I/O expander.

My design required that an external master read and write a handful of
registers in my FPGA.  It's one of those deals where you have to write
the address of the first register (an eight-bit number, for a total of
256 possible register), then you can essentially burst read or write
from there.

Basically, the I2C Slave Module itself has an eight-bit address
register output, an eight-bit output port (where data written by the
master appears), an eight-bit data input port (where data to be read
by the master must be driven) and a single bit "WriteDataValid"
strobe.

Logic outside that module implements the registers and address
decoding.  The address is used as a mux select; the mux inputs are all
of the register and the mux output always drives the I2C slave's
master-read data input.  The address is also decoded and when the
WriteDataValid strobe is active, the contents of the I2C slave's
master write output port are stored in an appropriate register.

It's also synchronous with a convenient clock.  It took about a day to
write, and I spent another day on a behavioral I2C master model and a
test bench.

No, I cannot give you the code, but I would imagine you've got enough
hints to complete your design.

-a

Article: 69889
Subject: Re: strange behaviour of the design
From: Marc Guardiani <marc@guardiani.com>
Date: Sun, 23 May 2004 20:10:32 GMT
Links: << >>  << T >>  << A >>
Yes, I've had similar problems. Compiled a CPLD with 4.2 and it worked. 
Didn't change a thing and compiled it with 5.x and it did not work. 
IMHO, the 5.x tools are worthless.

sameer wrote:
> hi geeks,
> 
> I have been using the xilinx foundation 5.2i and 4.2i. The design used
> to work on board with both these versions earlier. But now with a few
> additions to the code/design , the code some times works with 4.2i but
> never with 5.2i.
> 
> I brought out (on the board) the internal signals ,but very strange
> behaviour is seen, which is very absurd e.g. the signals required for
> the state machine to go to the next state are generated, but the state
> machine remains in the same state . Another example :- a signal has to
> be set under certain conditions, this conditions are seen on the debug
> pins, but still the signal is not set. Here there is no timing issue,
> all the timigs are met .
> 
> I am really clue less as the synth/ warnings are also inconclusive. Is
> it due to some fanout related issue (tool didnt issue any warning abt
> it though..)
> 
> If anybody has faced similar problem ?

Article: 69890
Subject: Re: strange behaviour of the design
From: Jim Granville <no.spam@designtools.co.nz>
Date: Mon, 24 May 2004 09:30:56 +1200
Links: << >>  << T >>  << A >>
sameer wrote:

> hi geeks,
> 
> I have been using the xilinx foundation 5.2i and 4.2i. The design used
> to work on board with both these versions earlier. But now with a few
> additions to the code/design , the code some times works with 4.2i but
> never with 5.2i.

Try the newest version of the SW ?
There have been reports of a back-step around 5.2, but I think ~V6.2 is 
current.
-jg


Article: 69891
Subject: Re: strange behaviour of the design
From: Bassman59a@yahoo.com (Andy Peters)
Date: 23 May 2004 15:27:40 -0700
Links: << >>  << T >>  << A >>
sameer.gandhi@wipro.com (sameer) wrote in message news:<f7e64c3a.0405231015.674ed9ee@posting.google.com>...
> hi geeks,
> 
> I have been using the xilinx foundation 5.2i and 4.2i. The design used
> to work on board with both these versions earlier. But now with a few
> additions to the code/design , the code some times works with 4.2i but
> never with 5.2i.
> 
> I brought out (on the board) the internal signals ,but very strange
> behaviour is seen, which is very absurd e.g. the signals required for
> the state machine to go to the next state are generated, but the state
> machine remains in the same state . Another example :- a signal has to
> be set under certain conditions, this conditions are seen on the debug
> pins, but still the signal is not set. Here there is no timing issue,
> all the timigs are met .
> 
> I am really clue less as the synth/ warnings are also inconclusive. Is
> it due to some fanout related issue (tool didnt issue any warning abt
> it though..)
> 
> If anybody has faced similar problem ?

Did you bother to simulate the design?

-a

Article: 69892
Subject: Re: More fun with VHDL
From: "Chuck McManis" <devnull@mcmanis.com>
Date: Sun, 23 May 2004 22:37:52 GMT
Links: << >>  << T >>  << A >>

"George" <george_mercury@hotmail.com> wrote in message
news:6d167a0a.0405222134.5947a13c@posting.google.com...
> ... So I used annother method - compare
> match.

Wow! The light bulb goes on! That's a great idea, a simple set of XOR gates
feeding an AND gate make for a match compare. I'll no doubt run into a bit
of trouble later when I'm trying to run the sequences "out" of phase, but I
can do that brute force with a simple adder.  Thanks George!

--Chuck



Article: 69893
Subject: Re: Altium FPGA board
From: "Chuck McManis" <devnull@mcmanis.com>
Date: Sun, 23 May 2004 22:45:05 GMT
Links: << >>  << T >>  << A >>
"Rene Tschaggelar" <none@none.net> wrote in message
news:40b0fd9d$0$721$5402220f@news.sunrise.ch...
> The Nexar package is not really that overpriced. It allows to develop
> FPGAs with a 8051 kernel built in, with debugger, compiler, everything.

I should have been more crisp, $8,000 is waaaaaaay overpriced for me. Even
the $1000 I spent on the Proteus package (www.labcenter-electronics.com)
seemed steep but it too has the embedded processor simulator (PIC, AVR, and
8051) and as I use PICs (some AVRs, but no 8051 yet) in my robotics I was
moderatly motivated by it.

A friend of mine hat the CircuitStudio package and was not complimentary so
I steered clear of that too.

> The low number of units I ship doesn't forbid to have an FPGA plus an
> AVR on a board. That may change from a certain number of units upward,
> though.

Bringing it back on topic...

Have you played with the FPSLIC stuff? AVR core plus FPGA? I've got the
development board as I was looking at some sort of custome baseboard
controller (SMBus, i2c, etc) and it looks great but Atmel doesn't seem
particularly committed to it ...

--Chuck



Article: 69894
Subject: Re: OT: Electronics learner kit?
From: robison_m@crane.navy.mil (Zspider)
Date: 23 May 2004 17:56:06 -0700
Links: << >>  << T >>  << A >>
Thanks, Ray and e-man, for the suggestions.  The Radio Shack
Electronics Learning Lab looks like a great place to start, 
and I will look over all the web sites you recommended.  I
found the Radio Shack Learning Lab available at two places
in Bloomington.  I'll pick it up next time I make it into
town.  I'm hoping that the whole thing will be a fun exper-
ience for her.  

Thanks again, Michael

Article: 69895
Subject: Re: Xilinx training
From: Mike Treseler <mike_treseler@comcast.net>
Date: Sun, 23 May 2004 19:33:23 -0700
Links: << >>  << T >>  << A >>
Jakub wrote:

> I am a junior FGPA designer and am planning on attending some training
> to improve my design skills and FPGA knowledge.  Can someone tell me
> if the courses offered by Xilinx are good courses?  I am looking into
> the FPGA design flow (not VHDL classes) with courses like fundamental
> of FPGA design, designing for performance etc etc...

The FPGA design flow begins
with design entry and simulation.
That's your bread and butter.
Consider developing expertise on
the front end first.

You need HDL expertise for simulation
even if you use schematics for design entry.

Class quality is most sensitive to the particular
instructor. Find out who it is and check references.

            -- Mike Treseler


Article: 69896
Subject: Re: NIOS Board Stratix Edition - FPGA won't configure
From: vbishtei@hotmail.com (vadim)
Date: 23 May 2004 19:56:12 -0700
Links: << >>  << T >>  << A >>
I was fully aware that the MAX CPLD was programming the Stratix
device. We tried
to find the pin that is connected to the MAX CPLD and program it to be
tied to VCC (reconfig_req_n). This failed. 
I was not aware there was a software setting inside Quartus to
Tri-State unused pins, which only found through this newsgroup (thing
like this should appear
on the front pages of the NIOS Board manual). 

Generally, from working and learning Altera devices and software a
pattern seems to emerge - bad and ambiguous documentation. Huge and
wordy documents
that don't state the "beef" but tend to repeat things without much
elaboration.
This reminded me of learning Cadence software...

Thanks to Subroto and this forum the issue got solved now... (new ones
sure will come)

Article: 69897
Subject: Re: FREQUENCY DOUBOULER BY MAX PLUS......
From: ftls1@uaf.edu (ftls1@uaf.edu)
Date: 23 May 2004 20:22:08 -0700
Links: << >>  << T >>  << A >>
I solved it by myself.
I just made a delay and use some counters, anyway, thanks.

ftls1@uaf.edu (ftls1@uaf.edu) wrote in message news:<44042ede.0405201959.269935b@posting.google.com>...
> HI,ALL~
> 
> NOW I WANT TO DOUBLE A CLOCK OF 50HZ WITH UNCERTAIN LEADING EDGES,
> ACTUALLY THIS IS A FEEDBACK SIGNAL FROM AN EXTERNAL INPUT,HOW CAN I
> GET A PRECISE OUTPUT OF 100HZ CLOCK?
> 
> I'VE SEARCHED THE MAX PLUS II, I COULDN'T FIND APEX 20K SERIES
> DEVICES, THAT MEANS I MUST USE THE PLL OR CLKLOCK FOR APEX 10K?
> HOW TO USE THOSE DEVICES? COULD SOME GENTALMEN OR LADY GIVE ME A
> EXAMPLE TO SHOW HOW TO DEFINE THE PINS PARAMETERS?
> 
> ONLY QUARTUS II HAS THE 20K SERIES DEVICES, IS IT TRUE?
> 
> NOW I JUST USE A 8-BIT-COUNTER TO GENERATE A 100 HZ SIGNAL BY A 5KHZ
> CLOCK, HOWEVER, THIS IS NOT LOCKED TO THE 50HZ,THERE WOULD BE A PHASE
> DELAY BETWEEN LEADING EDGES OF BOTH TWO.
> 
> BY THE WAY, DO YOU GUYS KNO ANY AVAILABLE 16-BIT-SYNCHRONIZER-COUNTER
> IN MAX PLUS II? I WANT TO GET A 50-50 DUTY CYCLE SIGNAL BY
> 16-BIT-COUNTER, ANY GREY CODE OR OTHERS WOULD BE OKEY FOR ME.
> 
> 
> 
> ADV-THANKS-ANCE~
> 
> FTLS1@UAF.EDU

Article: 69898
Subject: spartan 2 demo example
From: haimveig@walla.co.il (haim)
Date: 24 May 2004 01:22:30 -0700
Links: << >>  << T >>  << A >>
Hello,
i have the spartan 2 demo board (the xilinx is -xc2s100) someone told
me that there is an example of a counter for this board that using the
leds and lcds
i searched ut on the web and didn't find it.
can any one give me a link for download??
good day.

Article: 69899
Subject: HOWTO calculate the binary size of a .hexout/.flash/.germs file
From: "GreateWhite.DK" <mse@ect.dk>
Date: Mon, 24 May 2004 11:11:32 +0200
Links: << >>  << T >>  << A >>
Hi

How can subject be done???

Regards up front
GreateWhite.DK





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