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"john jakson" <johnjakson@yahoo.com> wrote in message
news:adb3971c.0405211754.52bb304c@posting.google.com...
> > 3) Its creators are British.
> >
>
> Perhaps I am doomed to fail on all 3 counts.
>
> Anyway I may be a US citizen before this thing gets polished and can
> deny the last rule as everything important has to seem to be invented
> or reinvented in the US- (sadly).
>
> Since my math isn't so great maybe I can deny the 2nd rule too:).
^^^^
John, looks like you're most of the way there ;-)
I still don't understand why Americans shorten mathematics
to 'math'.
Nial.
Article: 69951Hi, We have tried to read/write data from/to SRAM (AS7C4096) using a tri-state buffer to drive data bus but we are not being able to manage this task. Whenever we try to read data from the memory we obtain the value 0x0000 although the memory word has been loaded with a different pattern. Similarly, when we write data the final value in the memory word is 0x0000 regardless of the value we drive into the data bus. Has anybody any idea about this? What are we doing wrong? Thanks a lot O. Garnica UCMArticle: 69952
Hi, As you're pretty close to meeting the timing, your best bet may be to read up about the Floorplanner. You just(!) need to place your critical logic. Also, you may be able to persuade Synplify to work better, this has worked for me in the past, especially if the design is pipelined. Be careful with over-contraining, it can often make things worse. Read the CAF archive to find out why. Mr. Andraka gripes about this a fair bit! ;-) Other less practicable alternatives include freezing, using a faster speedgrade, and turning up the supply voltage a bit! The Xilinx tools let you specify the temperature and supply voltage, check out Speedprint. HTH, Syms.Article: 69953
Here are some hardware ideas to boost performance a few percent: Buy a higher speed-grade part (usually improves performance by 15% per speed grade) Kep the internal supply voltage at or slightly above nominal. That gives you another 5%. Somehow keep the chip from getting hot... Peter Alfke ====================== Shalin Sheth wrote: > > You may want to try to run map with the '-timing' option. > > For more ideas check out this Tech Tip from Xilinx: > http://www.xilinx.com/xlnx/xweb/xil_tx_display.jsp?sGlobalNavPick=&sSecondaryNavPick=&category=&iLanguageID=1&multPartNum=1&sTechX_ID=rw_tim_closure > > Shalin- > > Jon Beniston wrote: > >>My clock is 40MHz, but I have complicated FFT operations and other DSP > >>stuff. > >>The longest path is 25.8ns, though after I set the constraints at > >>23ns...Previously it > >>was 27.5ns at constraints of 25ns... > >> > >>What may I do now? How far can over constraining go? > > > > > > Keep going until the results don't get any better. > > > > > >>The source codes are > >>from > >>other people so I can't change a lot of it. > >> > >>Besides -opt_mode Speed in XST, what else controls can I use in ISE6.1? > > > > > > I think there is -opt_level (or something) that makes it work harder. > > > > Also, you can set the P&R optimisation level. > > > > Note: Estimated frequency after synthesis is not necessarily what you > > will get after P&R. > > > > > >>Does Synplify optimize for speed? > > > > > > Yes. > > > > > >>How does it compare with XST? > > > > > > I have found it to be better. The extra performance is often very > > heavily design dependant. More often than not, for me, it performs > > much better with large designs. > > > > Cheers, > > JonBArticle: 69954
Uncle Noah wrote: > In Microblaze there is no way to add your own custom instructions. It > is not an extensible processor but just provides the means to add > peripherals to a small SoC. Correct me if i am wrong. I just hope that > the tools (assembler, simulator, debugger) can be retargeted for the > new ISA. Or be able to use inline assembly with the new instructions. > The corresponding hardware should be built by some RTL description i > would give. Sorry, but I think that "custom instructions" are the worst idea. Than you have to update (with new versions/revisions) not only your design, but also the whole toolchain ? (assembler/linker/cc ?) And there is still tha chance, that the whole CPU slows down, because of your new instruction, so you even loose, not gaining anything :( Much simpler to access a "accelarator" memory mapped, or as a peripheral, or whatever interface you have for it.Article: 69955
Here is another suggestion: Normally transmit a clock that is 30% High, 70% Low, but at the synchronization moment, change one time to 70% High, 30%Low. In the receiver, use the DLL to generate 50% duty cycle (the DLL is always triggered on the rising clock edge). Then use the falling output edge from the DLL to clock the incoming clock level into a flip-flop. This flip-flop will be High for just one clock cycle. This idea is similar to the "missing clock pulse synchronization" mentioned before, but avoids its problems... BTW: You must dc-couple the clock for this suggestion ! Peter Alfke, Xilinx Applications. ===================================== John_H wrote: > > How about this weird idea: Don't send a pulse, send an edge. Your > attenuation might provide a little phase shift but it would be pretty easy > to alter the phase to match the clocks. Rather than a smeared pulse with > low high-level amplitudes, you get a full transition with a consistent 50% > point. > > "Tom Derham" <uceeted@ucl.ac.uk> wrote in message > news:xtvsc.1724$hu1.16883825@news-text.cableinet.net... > > I am using 3 Xilinx SpartanIIE boards, each loaded with a similar design > > running with a 100MHz master clock. This clock is derived from a single > > source and distributed to each board so they are synchronised. The boards > > are postioned about 50m apart. > > > > I need to synchronise events on the boards, but occasionally sending a > > single pulse (say 10ns long) from the output pin of one of the FPGAs to > the > > other boards, to allow them to synchronise internal timers. I need to > make > > sure that the pulse arrives at the other two boards at the same time so > that > > it is 'recognised' on the same rising edge of the reference clock in each > > case, so that the boards synchronise together. > > > > Clearly the attenuation of any 50m length of cable is such that I cannot > > connect them directly, but nor do I want the complexity of converting the > > pulse to optical fibre and back again. > > For the distribution of the reference clock I am using National CLC005/012 > > driver and equaliser chipset over UTP, using equal length wires so as to > not > > introduce propagation skew. For practical reasons I can't use the same > > cable for sending this event pulse, and ideally would like a simple, > elegant > > solution. > > I was just wondering if anyone had done anything similar before... if not, > I > > have a back-up plan using more of the National drivers, but I thought they > > might be a sledgehammer to crack a nut - and am unsure what levels of skew > > they may introduce themselves... jitter is not so important because the > > event is resynced at the receiving fpga, as long as the total difference > in > > edge is less than half of the reference clock cycle (so 5ns). > > > > Thank you in advance for any ideas.... > > > >Article: 69956
Hi, has anybody sucessfully compiled the kernel modules windrvr/xpc4drvr under kernel 2.6 ? The code seems to be not prepaired for kernels >2.5 linux_wrappers.c:43: /* only allow 2.0.x 2.2.y and 2.4.z */ Is there a newer verion available from xilinx rather than ftp://ftp.xilinx.com/pub/swhelp/ise6_updates/linuxdrivers.tar.gz ? thanks JoergArticle: 69957
Hi, I've done a bunch of work with FPGAs in courses that I took, but in all those cases I was using either Xilinx's FPGA demoboards or an Altera board designed by my university. For my lab now I'm designing a board that will have a Xilinx CPLD on it, and not much else. I'm sort of the token EE in my lab, and having just gotten my bachelor's last year, I've never really designed a board. My main question now...I want to be able to easily reprogram the CPLD, so to access the JTAG interface I could just put some header pins on the board and wire them up to the right device pins, correct? Also, it seems to me like the board would have to be powered up, i.e. plugged into the back plane, to be programmed. This might not be so convenient as the electronics box it will be going in is pretty far away from the PC that the design is being on. Am i mistaken in that the board needs to be powered up, or can the cable supply the power? I guess a solution would be to add another header to connect to a separate, portable, 3.3V power supply. Thanks, Matt CohenArticle: 69958
"E.S." <emu@ecubics.com> wrote in message news:4KLsc.19641$zs2.4918@fe39.usenetserver.com... > Uncle Noah wrote: > > > In Microblaze there is no way to add your own custom instructions. It > > is not an extensible processor but just provides the means to add > > peripherals to a small SoC. Correct me if i am wrong. I just hope that > > the tools (assembler, simulator, debugger) can be retargeted for the > > new ISA. Or be able to use inline assembly with the new instructions. > > The corresponding hardware should be built by some RTL description i > > would give. > > Sorry, but I think that "custom instructions" are the worst idea. > Than you have to update (with new versions/revisions) not only your > design, but also the whole toolchain ? (assembler/linker/cc ?) > > And there is still tha chance, that the whole CPU slows down, because > of your new instruction, so you even loose, not gaining anything :( > > Much simpler to access a "accelarator" memory mapped, or as a > peripheral, or whatever interface you have for it. > > Wouldn't you have a hard time setting your inputs, issuing the command, and retrieving your results in one clock cycle with an external peripheral? Custom intructions and external peripherals/functions are both very usefull and have their place. Ever heard the term "Sour Grapes" ? :) KenArticle: 69959
Hi. I'd like to build an 80s-style display controller, but I want to
output the image to a VGA monitor.
I've seen references to a 320x200 "doublescan" mode, and an XFree86
config file that specifies the timings as:
15.75MHz horizontal, 37.9kHz vertical. 85.3Hz.
H: 320 336 368 416 / V: 200 200 202 222
I believe the numbers mean:
320 pixel Video.
(336 - 320) = 16 pixel R.Border + F.Porch.
(368 - 336) = 32 pixel H.Sync.
(416 - 368) = 48 pixel B.Porch + L.Border.
200 line Video.
(200 - 200) = 0 line B.Border + F.Porch.
(202 - 200) = 2 line V.Sync.
(222 - 202) = 20 line B.Porch + T.Border
I have a couple of questions:
1. 416 x 202 x 85.3 = 1/2 15.75MHz specified, so I'd like to know how
the doublescan mode works.
Is it an interlace mode? If so how do you wiggle the VGA connector
pins to signal odd/even frames?
Or is it really a 320x400 mode, with every line output twice?
2. The vertical timing suggets a zero Bottom Border and Front Porch.
Is that right? Does the V.Sync come immediately after the last
video line?
3. Ideally what I would like is 320x200 @ 60Hz (or 320x400 @ 60Hz
if that's how doublescan works). Can anyone suggest the video
timings for that?
Thanks,
Paul.
Article: 69960Ken Land wrote: > Wouldn't you have a hard time setting your inputs, issuing the command, and > retrieving your results in one clock cycle with an external peripheral? > Custom intructions and external peripherals/functions are both very usefull > and have their place. I was thinking along the lines of something what wouldn't use just one instruction, but could run very well parallel to the cpu for few clocks. ANd, even use a faster or slower clock ... > Ever heard the term "Sour Grapes" ? Heard before, but why in this context ?Article: 69961
"Matt Cohen" <matthewlawrencecohen@yahoo.com> wrote in message news:81fdc5f7.0405251148.23def225@posting.google.com... > Hi, > I've done a bunch of work with FPGAs in courses that I took, but in > all those cases I was using either Xilinx's FPGA demoboards or an > Altera board designed by my university. For my lab now I'm designing > a board that will have a Xilinx CPLD on it, and not much else. I'm > sort of the token EE in my lab, and having just gotten my bachelor's > last year, I've never really designed a board. My main question > now...I want to be able to easily reprogram the CPLD, so to access the > JTAG interface I could just put some header pins on the board and wire > them up to the right device pins, correct? Also, it seems to me like > the board would have to be powered up, i.e. plugged into the back > plane, to be programmed. This might not be so convenient as the > electronics box it will be going in is pretty far away from the PC > that the design is being on. Am i mistaken in that the board needs to > be powered up, or can the cable supply the power? I guess a solution > would be to add another header to connect to a separate, portable, > 3.3V power supply. Thanks, Most programming adaptors for CPLDs and FPGAs, like those from Altera and Xilinx, get their power from the target board, so you will need a separate supply to your board. Just wire the header up to the pins on the device. LeonArticle: 69962
hi, I am now doing a readback on the virtex2 device(xc2v1000). I have read the application note 138,139. But it's for virtex. I suppose it's the same with virtex2. I have still some question about it, 1. Load the CFG_IN instruction into the JTAG IR, then go to SDR(shift data to register). I should first shift a sync word(aa995566)? 2. the frame size to readback. for xc2v1000, one frame length is 3392 bit. I think it's same like virtex. For only one frame readback, It read back first the pad frame(3392 bit), then it's the frame we want.(3392 bit). so I think the frame size is 3392*2/32 = 212(d4h). is it right? 3. How many times should I flush the command pipe? I think 2 times 32 bits of 0 are sent to flush the command pipe, because the JTAG register is 64 bit. is it right? 4. Is there a pad word in front of frame? I write the c code for readback. It's the command sequence , 1. 0xAA995566; Synchronization word 2. 0x30002001; write to FAR register 3. frame addr; from .ll file 4. 0x30008001; write to CMD register 5. 0x00000004; Active RCFG 6. 0x280060d4; Number of word to readback (d4h = 212) 7. 0x00000000; Flush command pipe with 32 bits of zeros. 8. 0x00000000; Flush command pipe with 32 bits of zeros. is that right? Thank you for reading. Any information about it is welcome. Thanks in advance. WeiArticle: 69963
mikegw wrote: > Anyone know what happed to this site? It has been off the air for a few > days now. > > Mike > > Try a mirror: http://opencores.nnytech.net/projects.cgi/web/opencores/mirrorsArticle: 69964
I have Verilog and VHDL code which has 2D array. They are synthesized correctly with Xilinx XST. But it won't compile with Altera MaxPlus II. HendraArticle: 69965
> > > Is this with the register window enable or with the mflat option? Register windows. > If you add the data into the sizes, the percentage will be even smaller. You can add in whatever you want. We wont be talking about code size though ;) > For a lot of the application, the data size is normally larger than the > code size. Yes, but for conventional embedded CPU apps, code is different (i.e. it goes in FLASH/ROM rather than RAM). > The only benefit of smaller application size (code and data) is that you > might get away with smaller memories. You say it like it doesn't matter. Maybe it doesn't with FPGA CPUs as you're obviously not concerned about price anyway ;) Cheers, JonBArticle: 69966
I am using Orcad version 9.2 to create orcad symbols. I am trying to follow a method described earlier in the same newsgroup. I am describing pointwise the steps am following: 1) I downloaded the pinout table from Xilnx website 2) I sort the pinout in excel based on bank number 3) I create a new part in a library in Orcad and place the number of pins I need using "place pin array" command 4) I select the pins whose name and pin number have to be changed and press "CTRL + E" and I get the browse spreadsheet editor in Orcad. After that I am not able to do anything other than copy the contents of the Browse spreadsheet editor. To insert the pin names I select the coloumn "Name" and I press ctrl + insert, but nothing happens For instance after I select the "Name" coloumn to be replaced by the contents I am trying to paste, the commands like "paste" , "copy" among others just goes unusable(the letters on those commands goes grey from black). Actually the paste is not active at all irrespective of whether I select any coloumn or not. Is this a version problem? I see Rotem Gazit had posted this message in 2001. Please let me know if you have experienced this difficulty before. thanks Krishna Kumar DSP Systems Engineer Signalogic Inc 9617 dallas TX-75243Article: 69967
> > Sorry, but I think that "custom instructions" are the worst idea. > Than you have to update (with new versions/revisions) not only your > design, but also the whole toolchain ? (assembler/linker/cc ?) I don't think it works like this. I think the instructions are already built in to the toolchain, you just have to define what they do. If this is the case, then it's not really that flexible as you are restricted as to what operands you can use. > Much simpler to access a "accelarator" memory mapped, or as a > peripheral, or whatever interface you have for it. It depends on what you are trying to do. For some tasks, such as performing a bit reverse or something trivial like that, it will work well, and the programming model is ideal. For other things, such as performing block encryption, it obviously isn't going to work. It all depends on what you are trying to I guess. At least it is nice to have the option there. Cheers, JonBArticle: 69968
Hendra, Max II has no RAM in the logic plane, so it only seems natural that a 2D array (which looks like RAM) would not be easily recognized. One should be able to use each LE as a FF in the array, but that is pretty inefficient, and would chew up all resources pretty fast. There is user flash memory available, and perhaps the synthesis tools require special directives to use it. What Xilinx parts "synthesized correctly?" Just curious. Sounds like a FPGA application, not a CPLD application. Austin Hendra Gunawan wrote: > I have Verilog and VHDL code which has 2D array. They are synthesized > correctly with Xilinx XST. But it won't compile with Altera MaxPlus II. > > Hendra > >Article: 69969
"Austin Lesea" <austin@xilinx.com> wrote in message news:c90kbj$ljb3@cliff.xsj.xilinx.com... > What Xilinx parts "synthesized correctly?" I just tried to inferred a RAM with 2D array reg [7:0]q[7:0]; //two dimensional array. In the synthesis report, it said "Found 64 bit register" or something like that! It worked in the Xilinx FPGA exactly the way I want it, which is an 8x8 RAM. HendraArticle: 69970
"E.S." <emu@ecubics.com> wrote in message news:GsOsc.20467$zs2.931@fe39.usenetserver.com... > Ken Land wrote: > > > Wouldn't you have a hard time setting your inputs, issuing the command, and > > retrieving your results in one clock cycle with an external peripheral? > > Custom intructions and external peripherals/functions are both very usefull > > and have their place. > > I was thinking along the lines of something what wouldn't use just one > instruction, but could run very well parallel to the cpu for few clocks. > ANd, even use a faster or slower clock ... > > > Ever heard the term "Sour Grapes" ? > > Heard before, but why in this context ? > > Uh.. Because you're saying you don't want something you can't have, even though it's of great value. (Custom Instructions with Nios (the grapes) vs. Microblaze (no grapes) - so you say "They are probably sour anyway") KenArticle: 69971
"Jon Beniston" <jon@beniston.com> wrote in message news:e87b9ce8.0405251505.5b6713a8@posting.google.com... <snip> > > You say it like it doesn't matter. Maybe it doesn't with FPGA CPUs as > you're obviously not concerned about price anyway ;) > > Cheers, > JonB Hard to imagine an embedded project without an fpga. Might as well have only one chip (fpga + softcore cpu) and save the board space since you're most likely going to require an fpga anyway. (board space == $$$, parts count == $$$) The reason you would want to use a softcore over hard is because it can be *exactly* customized to any application. Need 27 serial ports and timers? no problem. Need none? don't waste the pins or money. Need more processing power? add custom instructions/external parrallel logic or another softcore cpu (or 8!). I've seen hard core projects fail, but a soft core project can only fail from early abandonment. More/harder work can always find a solution, because the hardware can become anything you're willing to realize. KenArticle: 69972
> Jakub wrote: > > > I am a junior FGPA designer and am planning on attending some training > > to improve my design skills and FPGA knowledge. Can someone tell me > > if the courses offered by Xilinx are good courses? I am looking into > > the FPGA design flow (not VHDL classes) with courses like fundamental > > of FPGA design, designing for performance etc etc.. I attended both Fundamentals of FPGA Design and Designing for Performance. In my opinion, they are not that usefull. The classes are mostly focused on how to use the software, clicking here and there and see how it changes. There is no in depth tutorial on Xilinx FPGA architecture. I think they posted some of their course material on Xilinx ftp site. Look for "Fundamentals of FPGA Design", "Designing for Performance", and "Advanced FPGA Implementation" keywords. Just look over it and make decision on your own whether or not you really need to take the course. Note that I am not trying to discredit Xilinx or anything. I think Xilinx is a wonderfull company, their software is much better than Altera, the help menu is very good, and their website is very well organized. I am just dissapointed that I don't get the thing that I expected out of the class. I expected to learn Xilinx Hardware FPGA Architecture, but instead I have just been taught on how to use the software tool. HendraArticle: 69973
Thanks for your advice. I have no control over chip and board... The speed is 40MHz and it is fixed too. Kelvin "Peter Alfke" <peter@xilinx.com> wrote in message news:40B3870C.FE839F7E@xilinx.com... > Here are some hardware ideas to boost performance a few percent: > Buy a higher speed-grade part (usually improves performance by 15% per > speed grade) > Kep the internal supply voltage at or slightly above nominal. That gives > you another 5%. > Somehow keep the chip from getting hot... > > Peter Alfke > ====================== > > Shalin Sheth wrote: > > > > You may want to try to run map with the '-timing' option. > > > > For more ideas check out this Tech Tip from Xilinx: > > http://www.xilinx.com/xlnx/xweb/xil_tx_display.jsp?sGlobalNavPick=&sSecondaryNavPick=&category=&iLanguageID=1&multPartNum=1&sTechX_ID=rw_tim_closure > > > > Shalin- > > > > Jon Beniston wrote: > > >>My clock is 40MHz, but I have complicated FFT operations and other DSP > > >>stuff. > > >>The longest path is 25.8ns, though after I set the constraints at > > >>23ns...Previously it > > >>was 27.5ns at constraints of 25ns... > > >> > > >>What may I do now? How far can over constraining go? > > > > > > > > > Keep going until the results don't get any better. > > > > > > > > >>The source codes are > > >>from > > >>other people so I can't change a lot of it. > > >> > > >>Besides -opt_mode Speed in XST, what else controls can I use in ISE6.1? > > > > > > > > > I think there is -opt_level (or something) that makes it work harder. > > > > > > Also, you can set the P&R optimisation level. > > > > > > Note: Estimated frequency after synthesis is not necessarily what you > > > will get after P&R. > > > > > > > > >>Does Synplify optimize for speed? > > > > > > > > > Yes. > > > > > > > > >>How does it compare with XST? > > > > > > > > > I have found it to be better. The extra performance is often very > > > heavily design dependant. More often than not, for me, it performs > > > much better with large designs. > > > > > > Cheers, > > > JonBArticle: 69974
Thanks. The frequency is fixed and RTL is documented to operate at 40MHz. I will tamper with the tools for a while instead of havocing with the codes. Codes change will be my last resort... Kelvin "ALuPin" <ALuPin@web.de> wrote in message news:b8a9a7b0.0405250502.385b73b0@posting.google.com... > "Student" <student@nowhere.com> wrote in message news:<40b2f02e@news.starhub.net.sg>... > > Hi, there: > > > > My clock is 40MHz, but I have complicated FFT operations and other DSP > > stuff. > > The longest path is 25.8ns, though after I set the constraints at > > 23ns...Previously it > > was 27.5ns at constraints of 25ns... > > > > What may I do now? How far can over constraining go? The source codes are > > from > > other people so I can't change a lot of it. > > > > Besides -opt_mode Speed in XST, what else controls can I use in ISE6.1? > > > > Does Synplify optimize for speed? How does it compare with XST? > > > > Kelvin > > Hi Kelvin, > > if the source codes are from other people and you cannot change it > you should assume that is has been optimized for 40MHz, isn't it? ;o) > > You have to clarify for which clock frequency the original design has > been developed. > > So basically the best possibility is to think about pipelining your design. > By doing so you will not have to worry about constraining. > > Rgds
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