Custom Search
Site Home Archive Home FAQ Home How to search the Archive How to Navigate the Archive
Compare FPGA features and resources
Threads starting:
Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z
General warning: FIFOs with two independent clocks are tricky when it comes to detecting the Empty condition. That's why Gray-coded addresses are a must to avoid comparator glitches. In your case, the Baud rate is so extremely slow that you might convert the whole FIFO into a trivial synchronous 90 MHz design, by double-synchronizing (anti-metastable) the slow clock to the 90 MHz. Crossing clock boundaries can be dangerous to your mental health. I know! Peter Alfke ================================= john orlando wrote: > > Hello, > We have recently been using the free Xilinx UART macro with the > 16-byte FIFO (from app note XAPP223) in a design, instantiated in a > Virtex XC2V1000. We are using both the Rx and Tx macros (actually, 32 > of each for a total of 32 UARTs in the device). Our actual setup > looks like this: > > StrongArm SA-1100 <--> Virtex XC2V1000 <--> 32 serial devices > > where the UART FIFOs in the XC2V1000 are essentially memory-mapped > into the StrongArm's memory space to read and write to the serial > devices. > > Occassionally, we are seeing a MISSED byte being sent from a random > serial device. We have scoped the serial lines between the serial > devices and the XC2V1000 and know the serial data is showing up there. > We put a high-speed logic analyzer on the interface between the > SA-1100 and the XC2V1000, and know that the byte does not appear > there. > > After three weeks of investigating this issue, we are starting to > wonder if the lost byte may be due to the macro. Is there any > condition with the macro where performing a read from the UARTs Rx > FIFO to pull a byte out on the same clock edge where a stop-bit has > been received and recognized, and the received byte added to the Rx > FIFO, would cause the received byte to be lost? Specifically, it > seems as though we see N bytes in the UART's Rx FIFO to be read, we > perform N reads (actually, N+1 reads, because the N+1 read is what > indicates to us that DATA_PRESENT is not asserted, and that byte > should be thrown away...we do 16-bit reads: 8 bits data, and 8-bits of > status, with the DATA_PRESENT part of the status). We only see the > missing bytes when we eventually see DATA_PRESENT again, which > interrupts us (the interrupt is actually delayed 4-byte times in our > system), and we perform a read of the data in the Rx FIFO again. We > should be able to read 4 valid data bytes. However, the first byte we > read from the FIFO is actually the SECOND byte that should have been > in the FIFO, and the first byte is gone forever (the remaining third > and fourth byte are read just fine). > > Anyone out there ever seen this type of behavior with the macro > before? Our baud rates are running at 38.4 KBps, and our FPGA is > being clocked by the StrongArm at ~90 MHz, in case you're curious. > Any help would be appreciated....thanks in advance! > > Regards, > John O.Article: 63076
> =================================
> john orlando wrote:
>>Anyone out there ever seen this type of behavior with the macro
>>before? Our baud rates are running at 38.4 KBps, and our FPGA is
>>being clocked by the StrongArm at ~90 MHz, in case you're curious.
>>Any help would be appreciated....thanks in advance!
>>
>>Regards,
>>John O.
Peter Alfke wrote:
> In your case, the Baud rate is so extremely slow that you might convert
> the whole FIFO into a trivial synchronous 90 MHz design, by
> double-synchronizing (anti-metastable) the slow clock to the 90 MHz.
Yes. Synchronize the slow data to 90 MHz
and use a synchronous fifo.
For synth fifo code examples see
http://www.edif.org/lpmweb/more/vhdl.htm
-- Mike Treseler
Article: 63077Gazelle wrote: > > Good day gents, > I am wondering if VHDL (or Verilog) code > exists in order to make a frequency doubler in a normal > CPLD (without internal DDL/DPL/PLL infrastructure ) with a symmetric > duty cycle. > Below some code can be found which generates a by-2 multiplied > frequency - however the duty cycle > is very assymmetrical ... If you think about this, you are asking for 'clairvoyant logic' - it has to know where to put the extra edges, in order to give symmetric output. You CAN double Freq, to get an OP positive edge for each IP edge, but the OP falling edge has no IP info to relate to, so is device delay determined. So, you will need some analog interpolation scheme - that can be : - Accept fixed freq operation, and design appx delays as nominal 50% - RC integrator & comparitor, to give quadrature signals which can then be doubled to close to 50%. - narrow band tuned circuit, ringing at target 2f - Full PLL approach -jgArticle: 63078
Occasionally, zip tries to zip the zip file. Since the zip file is locked, it fails. When this happened to me, immediately trying again usually succeeded. Jock wrote: > When using Xilinx ISE 4.1 to archive my project I get the following message: > > ************************ > The zip process invoked as > zip -r -q [zip_path]\filename.zip > [netlist_path] > [project_path] > failed: > *********************** > > It doesn't give any reason why it's failed. Has anyone else seen this and > knows why? > >Article: 63079
"Jeroen" <dev@null.com> wrote in message news:<3fb220b6$0$58712$e4fe514c@news.xs4all.nl>... > Hi, > > I'm using a Altera Nios Cyclone dev.board (and the ref-32 design) and I want > to use the CF slot for a testapplication. I'm looking for some C code to > access the CF, so that I won't have to write it myself. Just code to issue > IDE commands and get the data from the CF. No filesystem etc. Does someone > know where I can find such code? > > Jeroen KROS Technologies offers a complete FAT32 filesystem and compact flash (hot-swap) package for the Cyclone and Stratix development boards. http://www.krostech.comArticle: 63080
Hi Im trying to locate a EPM3064ALC44 Altera device in the in the PLCC44 package.. Tried major suppliers in Australia.... no luck., Cheers, sumoskidmark@hotmail.comArticle: 63081
I hope I'm posting it in the right groups. I've been designing for a while, but with minimal JTAG knowledge. Q: Can I use JTAG interface to verify what I wrote into the SRAM, instead of the traditional read-back method? My setup and the reason for wanting to do it this way is : An FPGA interfaces to a sync SRAM (QDR with separate write/read port). The FPGA can write to the SRAM using the processor interface, but does not have the read-back capability, because the read port from the SRAM goes elsewhere (no read-back capability there, either). Why do it this way? So that the each of the write/read data bus is point-to-point, without stubs on the board (150+Mhz). I could therotically bring the read bus back into the FPGA, then send it out again, but I'm fairly pin-limited. There are several SRAM interfaces, so whatever I do for each SRAM gets multipled by N. So, what I'd like to do is load the SRAM in a conventional manner, then test it via the JTAG interface. The amount of time it takes to verify doesn't matter. The SRAM I'm thinking of using is Cypress, will be running it at 150+Mhz, and the device supports these JTAG instructions : EXTEST, IDCODE, SAMPLE Z, SAMPLE/PRELOAD, BYPASS (Preload isn't supported, actually). Looking at this, it looks like I need to use the FPGA to supply the read controls at a slower rate, to match JTAG speed, then use SAMPLE instruction. Or, am I way off base here? Would it get too messy and should I just provite the read-back path at the cost of higher pincount? Thank you in advance for any input/suggestion. To reply via email, change 'hard' to 'easy'.Article: 63082
Hi All, I am looking for documentation on estimation of FPGA device utilization from a high level design specification(idea). Can anybody tell me where I can find out this kind of document which gives idea about how to do rough estimate of gate count(ASIC) or device utilization from a high level design description. The design will of course be made in VHDL/Verilog.Article: 63083
Hi, I was wondering if any of you have any numbers in terms of configuration times ( micro seconds ?) using ICAP. Do you think using ICAP adds more overhead than it does good? In my application, I have DATA(Dynamic Part that needs to be reconfigured), and the Processing Engine(PE, which will be the static part) that works on the DATA. As ssoon as PE finishes working on DATA set 1, I will need to change the LUT contents on the DATA block. And I would like to generate this data internally using the hard core Power PC of Virtex II pro. I would appreciate your comments . TIA, Kode "tk" <tokwok@hotmail.com> wrote in message news:<bmmcu8$g0q$1@hkueee5.eee.hku.hk>... > Hi JuHwa, > > ICAP can also access the IPIF. But of course, you should avoid > moidfying the area defining the IPIF since it may introduce misbehavior > in the ICAP. > > To set a system up, you can use the EDK to design an embedded system > supporting Linux port. Basically, the system consists of a processor > (Microblaze, > or PPC450 in Virtex-II Pro), some IP core peripherals and PLB/OPB/DCR buses > to connect the processor core to other cores. You can refer to the ML300 > embedded > system reference deisgn to get an idea of it. > > To use the ICAP in a system mentioned before is straightforward. You merely > need to > attach the "ipif_slv_sram" in XAPP 662 reference design to PLB/OPB. > > Hope this helps, > > tk > > > t depends on the device you use. If you are using > Virtex-II Pro, you can > "PanJuHwa" <panjuhwa_fpga@yahoo.com> > ???????:89e30c0c.0310150853.415294f4@posting.google.com... > > Hi, > > > > I am very interested in exploring the use of ICAP for > > self-reconfiguration of the Virtex2 fpga. XAPP 662 describes the > > in-system reconfiguration of RocketIO attributes, and I have been > > trying to understand the process of self-reconfiguration through this > > application note as well as the reference design that comes with it. > > > > It seems that we need to configure the FPGA with a bitstream > > generated from hdl that includes an PLB bus arbitrator and controller, > > as well as ICAP IPIF to the PLB. Does this mean the ICAP, possessing > > access the configuration memory, would actually have access to parts > > of the configuration memory that defines the arbitrator and ICAP IPIF > > as well? Or are is the information used to configure the arbitrator > > and IPIF somewhere else? Say for instance the fpga is to be configured > > with a jpeg encoder. Would the configuration memory accessed by the > > ICAP be solely occupied by the jpeg encoder configuration, or by the > > ipif etc as well? If in the latter case, then ICAP should never modify > > areas defining the IPIF, is this correct? > > > > I would appreciate too if someone who has done this before can > > provide some guidelines on how I can set the system up to use the > > ICAP. Thanks in advance!:) > > > > Ju HwaArticle: 63084
Howdy folks. I've got a recent BS in computer sytems engineering, which is a like EE with some compsci mixed in. I've used CPLDs, and really want to get a good start in FPGAs so I can build my career in the 'embedded' direction. How does one start out in fpga development given that funds are limited ? thanks - moiArticle: 63085
Joe Fox wrote: > Hi Im trying to locate a EPM3064ALC44 Altera device in the in the > PLCC44 package.. Tried major suppliers in Australia.... no luck., Use the TC case, a TQFP44. Rene -- Ing.Buero R.Tschaggelar - http://www.ibrtses.com & commercial newsgroups - http://www.talkto.netArticle: 63086
Xilinx have a reasonably good app note on this very cap / FPGA / clock thing. search their web site. Simon P.S. As a PCB designer of 10 years or more.. I still don't put vias inside pads.. neither do our RF guys working at 1.5 GHz! You are asking for thermal problems doing that. now if you use laser vias or other micro vias or welded joints ... you don't have to worry ... but a standard FR4 PCB with 0.5mm or 0.8mm vias you have to worry. At 1.5 GHz all their designs use 3 0.8mm vias just touching the pad. never misses :-).. just requires a program called ADS from HP. "Martin Euredjian" <0_0_0_0_@pacbell.net> wrote in message news:WbKsb.30040$192.26857@newssvr27.news.prodigy.com... > "Martin Thompson" wrote: > > > Indeed it would, I think I must have dropped a factor of 10 somewhere, > > sorry about that! > > 'been there, done that, paid for it dearly... :-( > > > > How about we say that 1-2cm is close enough (for the HF decouplers?) > > That would seem to be the case. > > > > > For my last design truly labored over this and took the approach of > > > writing a custom power distribution system simulation tool in order to > > > get a handle on what was going on. > ... > > Agreed - I did much the same thing here. > > What's scary is that no matter how much you research the subject it's hard > to achieve convergence. It seems that everyone has a different --and > perfectly valid-- reason why it should be done differently. As is the case > with many things in engineering you have no choice but to abandon the search > for the truth, pick an approach you're comfortable with, and move on. > > > capacitance? We put two 3.3V/GND 4thou separation pairs in the board, > > which got us a few nF of very low inductance capacitance, which comes > > in handy at the top end. > > Did that, exactly. > > > I came to the conclusion that above 100-150MHz you couldn't do a lot > > with capacitors anyway. > > Probably true for discrete capacitors. I remember looking into these BGA > packaged cap arrays that seemed to do quite well at high frequencies. > > > > ESR). If you run the curves, you want some ESR to mitigate peaky > > > resonance effects. > > > > > > > You could always fit some small resistors in series :-) > > Funny enough, I did think about this. The more I looked at the calculations > and the curves the more I realized that you do want more series resistance > with your decouplers. Sort of counter-intuitive in looking at the problem > superficially, but makes perfect sense in the context of a power > distribution system. Well, I didn't want to be the first fool to try to > double-stack 0402 chip caps with 0402 chip resistors. I'll leave that > excercise for those who might be substantially better funded than I am > (enough to redo a board)! :-) > > > > Apologies again for my arithmetic! > > See what happens when you don't use an RPN calculator! > > > -- > ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ > Martin Euredjian > > To send private email: > 0_0_0_0_@pacbell.net > where > "0_0_0_0_" = "martineu" > > > > > >Article: 63087
Hi, I'm trying to design a controller for a Hitachi color STN display, but I'm running in to all kinds of problems here. I think most of it comes from the fact that I really don't know anything about how LCD displays work, so I was hoping someone in this group could enlighten me a little. From what I've gathered from the displays datasheet, it seems the display is controlled by two different clock signals, one for vertical and one for horizontal lines. Once these clock signals are set correctly, it should just be a matter of clocking the pixel data in right? There seems to be three bits for each color component, red, blue and green, and by my calculation this gives 8 different colors. However the display is listed as beeing able to show up to 65,000 different colors. How exactly is this possible? I have thought about various dithering schemes, but i think most of them implies very dramatical losses in refresh speeds, resolution and image quality. What is the normal way of producing colors on a CSTN display? Regards, AndersArticle: 63088
I believe the platform flash is only available as samples at the moment.. Simon "Atif" <atif@kics.edu.pk> wrote in message news:6a0a3f23.0311112158.1e4d5de5@posting.google.com... > I want to purchase fifty Xilinx Platform Flash XCF01S online. It is > not available at Avnet and NuHorizons and I am unable to find any > other sales representative to purchase it. > Can anyone please guide me from where can I purchase it? The order may > be shipped to Pakistan or America. > > Regards > Atif > Research AssociateArticle: 63089
> The SRAM I'm thinking of using is Cypress, will be running it at > 150+Mhz, and the device supports these JTAG instructions : EXTEST, > IDCODE, SAMPLE Z, SAMPLE/PRELOAD, BYPASS (Preload isn't supported, > actually). Are the SRAM read control signals connected to the FPGA? If not, I think you will need to use INTEST instruction, but looks like the SRAM does not support it. Jim Wu jimwu88NOOOSPAM@yahoo.com (remove capital letters) http://www.geocities.com/jimwu88/chipsArticle: 63090
I want to design a pci board which will expand one pci slot through a pci-bridge and pci-local bus and get two slot. I wonder if there is any driver problem? say i plug a audio card into the expanded slot? thanks HuiArticle: 63091
Hi, I made the following declaration in my toplevel-file: attribute preserve_signal : boolean; attribute preserve_signal of l_data_to_send : signal is true; attribute opt : string; attribute opt of l_data_to_send : signal is "keep"; This is the VHDL declaration to preserve nodes when performing the synthesis. But when starting the simulation I get the error message: "Ignored node in vector source file. Can't find corresponding node name l_data_to_send in design. What does go wrong? Thanks a lot. Best regards Andres Vazquez "Christos" <chris_saturnNOSPAM@hotmail.com> wrote in message news:<boto95$6qb$1@sunnews.cern.ch>... > Hi, > > Subroto Datta has already answered this to me, not so long ago. (Date: > 2003-10-09) > Search google groups for 'Quartus II simulation question' > Very clear answer. > > Hope it helps, > Christos > > Quartus II simulation question > "Vazquez" <andres.vazquez@gmx.de> wrote in message > news:eee19a7a.0311120747.55f699fb@posting.google.com... > > Hello, > > > > I made a simulation by the means of a vwf-file. > > > > If I want to see the simulation results of signals which are neither > > inputs nor output what do I have to do? > > > > Is there a difference between registered signals and combinatorical > > signals? > > > > Thanks a lot. > > > > Best regards > > > > A.VazquezArticle: 63092
"Simon Peacock" wrote: > Xilinx have a reasonably good app note on this very cap / FPGA / clock > thing. search their web site. XAPP158. Yup. One of the first references I looked at back two years ago. Pretty much spot on. If you want to have a better understanding you have to dive deeper into the subject, of course. For example, XAPP158 does not deal with PDS (power distribution system) design issues that affect signals going from chip to chip in a high-speed design. Noise in mixed-signal designs, etc., etc. Of course, that's not what the app note is about. -- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ Martin Euredjian To send private email: 0_0_0_0_@pacbell.net where "0_0_0_0_" = "martineu"Article: 63093
Hello,
I have a problem with Stratix's PLLs.
I want to feed input of Enhanced PLL from Fast PLL and Enhanced PLL form
Enhanced PLL.
CLK input -> Fast PLL -> Enhanced PLL -> PLL output
-> other logic
or
CLK input -> Enhanced PLL -> Enhanced PLL -> PLL output
-> other logic
Is this two configuration possible to achieve in EP1S25 device?
Quartus 3 signalize errors when I am trying to do that:
"Error: inclk0 port of PLL
interface_block_hes:INB|hes_plla:u2|altpll:altpll_component|pll must be
driven by a non-inverted input pin or, in a fast PLL, the output of a PLL".
Regards,
Krzysiek
Article: 63094Anders Hellerup Madsen wrote: > Hi, > > I'm trying to design a controller for a Hitachi color STN display, but > I'm running in to all kinds of problems here. I think most of it comes > from the fact that I really don't know anything about how LCD displays > work, so I was hoping someone in this group could enlighten me a little. > > From what I've gathered from the displays datasheet, it seems the > display is controlled by two different clock signals, one for vertical > and one for horizontal lines. Once these clock signals are set > correctly, it should just be a matter of clocking the pixel data in right? > kinda, you would normally have something like a clk to clock in the pixels, a sync for each line and a sync for each frame. > There seems to be three bits for each color component, red, blue and > green, and by my calculation this gives 8 different colors. However the > display is listed as beeing able to show up to 65,000 different colors. > How exactly is this possible? shouldn't that be, ... 8*8*8 = 512 colors > > I have thought about various dithering schemes, but i think most of them > implies very dramatical losses in refresh speeds, resolution and image > quality. What is the normal way of producing colors on a CSTN display? > > Regards, Anders > if you stick to some form of toggling between different intensities of each color to get apparent intensities in between, shouldn't only the resulting refresh rate go down? -LasseArticle: 63095
In article <3fb407d3$0$13522$ba620e4c@reader1.news.skynet.be>, Marc Van Riet <marcvanriet@yahoo.com> wrote: > Been reading this thread. I wonder if instead of using an FPGA, > DSP, general purpose processor or niche product it would be possible > to use a graphics processor like the ones developed for 3D graphics > boards. It's conceivable -- you can do a lot with them nowadays -- see www.gpgpu.org. Depends on details of the problem; from the description I'd be surprised if it fit in 128MBytes. And the GPUs are only single- precision at the best; the fastest use a custom FP representation which might have only 16 bits in the mantissa. TomArticle: 63096
>I want to design a pci board which will expand one pci slot through a >pci-bridge and pci-local bus and get two slot. I wonder if there is >any driver problem? say i plug a audio card into the expanded slot? Depends upon your softwae. I'd expect it to work for most OSes. It might not for an OS designed to run on small systems, say an OS for embedded systems. It might take a special configuration flag for the software to include support for the PCI Bridge. -- The suespammers.org mail server is located in California. So are all my other mailboxes. Please do not send unsolicited bulk e-mail or unsolicited commercial e-mail to my suespammers.org address or any of my other addresses. These are my opinions, not necessarily my employer's. I hate spam.Article: 63097
Foundation 3.1 was release about 3 years before Windows XP, so I would not expect it to work. You will need to get a newer version of the software. Try ISE WebPACK 6.1i or if you need to use larger devices ISE Foundation 6.1i. Steve Сергей Зорин wrote: >Hello. >I have instslled JRE 1.3. All works. However only under WIN98. >And me is necessary that all worked under WIN XP. >Can I it make? And how? > >Beforehand thank. > > > >Article: 63098
Is it possible to infer a dual port block RAM
when the ports have different memory dimensions?
Say port A has address and data width of 8 and 8,
while port B has address and data with of 9 and 4,
for instance.
Instead of using a 2 dimensional array, one could
define one long array then do appropriate
bit selection off the 1D array for addressing:
reg [0:2047] memory; // 256x8 or 512x4.
Port A Addressing (pseudo code):
memory[addr_a * 8 : addr_a * 8 + 7]
// Invalid Verilog, I know.
Port B Addressing:
memory[addr_b * 9 : addr_b * 9 + 3]
Or another, more Verilog friendly way, would be to
use a 2D array with the data as the least common denominator:
reg [3:0] memory [0:512]; // 512x4
Port A Addressing:
{memory[{addr_a, 1b'0}], memory[{addr_a, 1b'1}]}
Port B Addressing:
memory[addr_b]
Has anyone had success inferring asymmetric dual-port
block ram?
-Tom
--
Tom Hawkins
Launchbird Design Systems, Inc.
952-200-3790
http://www.launchbird.com/
Article: 63099Muthu wrote: >"Anil Khanna" <anil_khanna@mentor.com> wrote in message news:<3f906bdc$1@solnews.wv.mentorg.com>... > > >>Its all in the options. >> >>Right Click "Post-PAR Static Timing" and choose your report options. >> >>For analyzing specific paths - launch the "Timing Analyzer". >> >>Its much better in 6.1! >> >>"Muthu" <muthu_nano@yahoo.co.in> wrote in message >>news:28c66cd3.0310122152.8de177d@posting.google.com... >> >> >>>Hi, >>> >>>I am using ISE5.1i...XST synthesis tool. >>> >>>At the end of synthesis, XST generates defualt timing report for 1 or >>>2 paths. >>> >>>How can i generate a timing report after synthesis for more than 100 >>>paths? >>> >>>ie., as like .twr after Place and route. >>> >>>And How can i measure the time dealy between 2 specific points... >>>Points could be FF,mux or any logic >>> >>>Thanks in advance. >>> >>>Regards, >>>Muthu >>> >>> > >Post PAR can only be run with the Map results Right. But i need to >take the report from XST itself? > XST only does a summary. You will have to run map and trce to get 100+ paths. Steve
Site Home Archive Home FAQ Home How to search the Archive How to Navigate the Archive
Compare FPGA features and resources
Threads starting:
Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z