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Messages from 62900

Article: 62900
Subject: Re: How to create a look up table for a RAM application
From: Hul Tytus <htytus@shell1.iglou.com>
Date: 10 Nov 2003 18:20:03 -0500
Links: << >>  << T >>  << A >>
Assuming the max number of endpoints is known, make another RAM 
7 x (max number of endpoints). Use this ram to store the actual endpoint 
numbers and change the 7 bit endpoint field in the primary ram to a 
bit count in accordance with the max number of endpoints.

For example, if only 4 endpoints, then change the 7 bit field to a 2 
bit field and, at enumeration, store the numbers in the smaller ram.

Hul

Vazquez <andres.vazquez@gmx.de> wrote:
: Dear Sir or Madame,
: 
: I have a data packet which has a 13 bit field for an USB
: application(7bit + 4bit + 1bit + 1bit).
: 
: 
: Because of lack of memory I do create a RAM which
: has a data input width of only 10 bit. The write address of
: the RAM is [4..0], i.e. 32 words ? 10 bit.
: The words which are written into the RAM 
: are searched for later (CAM-like function).
: 
: The problem: I have to reduce 13 bit to 10 bit without losing the
: significance of the 13 bit. But it is not possible to leave out for
: example
: two bits of the 7bit (usb address) because the enumeration by the host
: is not
: predictable.
: 
: How could I solve this problem?
: 
: Thank you very much.
: 
: Best regards
: 
: Andres Vazquez
: G&D System Development

-- 
- for email, put the word "keep" in subject line -

Article: 62901
Subject: Re: Implementing a very fast counterin VirtexII
From: Peter Alfke <peter@xilinx.com>
Date: Mon, 10 Nov 2003 15:45:18 -0800
Links: << >>  << T >>  << A >>
I would suggest detecting FFFF and generating a wait state or two when
you reach that value. The probability is one in 64K, so it should hardly
have any impact on performance.

Peter Alfke
==================
Erez Birenzwig wrote:
> 
> To be more precise the implementation requires the calculation of:
> a = a + 1
> 
> When a is a 64bit vector, every clock cycle at 200MHz, using a virtexII-6
> FPGA.
> 
> Erez.
> 
> "Peter Alfke" <peter@xilinx.com> wrote in message
> news:3FB01875.A2C23F2F@xilinx.com...
> > "Counter" can mean many things.
> > If you need a synchronous counter that gives you the updated value
> > before the next count pulse comes in, that is a demanding design and may
> > have timing problems at 200 MHz.
> >
> > If, at the other extreme, you just need a counter that can resolve 200 (
> > or 500+ ) MHz, and you can wait some nanoseconds before you read the
> > final count value, that is trivial. In the extreme case you would just
> > concatenate 2-bit Johnson counters (at least at the input end), one
> > slice clocking the next. And there are many variations on this theme.
> > I built a 400 MHz frequency counter 5 years ago with XC4002XL...Playing
> > around, aiming at 1 GHz now.
> >
> > Peter Alfke, Xilinx Applications
> >
> >
> > Erez Birenzwig wrote:
> > >
> > > Hi,
> > >
> > >   I'm trying to write some code for a 64 bit counter for a VirtexII.
> > >
> > >   The problem I'm facing is that it has to run at least at 200MHz, and
> > > therefore
> > > a simple "a = a + 1" doesn't work (Xilinx rate the 64b counter to
> 114MHz).
> > >
> > >   I've tried a split approach with four smaller counters and a selector
> > > depending on the carry out of the previous stages but it only got me to
> > > about
> > > 180MHz.
> > >
> > >   Did anyone ever had a similar problem and solved it ?
> > >   Unfortunately I'm not familiar with a pipelined implementation, I'll
> be
> > > happy
> > > to learn one.
> > >
> > >   Many thanks,
> > >   Erez.

Article: 62902
Subject: Re: Reverse engineering an EDIF file?
From: Allan Herriman <allan.herriman.hates.spam@ctam.com.au.invalid>
Date: Tue, 11 Nov 2003 10:45:47 +1100
Links: << >>  << T >>  << A >>
On Mon, 10 Nov 2003 23:10:39 +0100, Rastislav Struharik
<rasti@eunet.yu> wrote:

>Hello,
>
>I would like to know does anyone knows, is it possible to reverse
>engineer an edif netlist file? I am currently developing an FPGA core.
>I would like to supply an evaluation version of the core, that would
>have all the functionality of the final core, but would operate only
>for a limited period of time. My fear is that there is a way to modify
>the evaluation version edif netlist (find and remove modules that set
>a time limit to the operation of the evaluation version), and thus
>obtain completely functional core. Can something like this be done, or
>am I being paranoid?
>Every help and clarification on this subject is most welcome.

I think you should distribute your design in a binary format, since
it's fairly easy to reverse engineer EDIF:

Use any text editor for editing.

Use Aldec or Riviera for simulating.  (Both tools handle a combined
VHDL / Verilog / EDIF flow).

Use a recent version of Synplify to convert to (almost readable)
schematics.

Regards,
Allan.1

Article: 62903
Subject: Re: 0.13u device with 5V I/O
From: Eric Crabill <eric.crabill@xilinx.com>
Date: Mon, 10 Nov 2003 15:50:11 -0800
Links: << >>  << T >>  << A >>

Hi,

> Ahem.  I think your company's lawyers would have something
> to say if anyone but you, and maybe Altera, tried anything
> of the sort.

What about Lattice, Actel, Atmel, and Quicklogic?  If I missed
anyone, my apologies in advance...

Also keep in mind that patents expire, and clever people find
other ways to build things that don't infringe.  Take a look:

http://eet.com/special/special_issues/1998/timespeople98/sasaki.html

> "Basically, the board only said three things," Sasaki remembered.
> "Go faster than Xilinx.  Don't touch any of their patents..."

Page 15 of http://www.walcek.com/dyna/DY6000.pdf is evidence of
how serious they were about following the board's directives.
Yes, it is programmable logic, but there's no LUT to be found!

Eric

Article: 62904
Subject: Re: Implementing a very fast counterin VirtexII
From: "Erez Birenzwig" <erez_birenzwig@hotmail.com>
Date: Tue, 11 Nov 2003 13:34:14 +1300
Links: << >>  << T >>  << A >>
Then when you read the counter every clock cycle once every 64K counts
you'll
get a wrong result. I don't think it's good enough.. Remember the FMUL bug ?

Anyway I got a good answer from another list :

1) Build a fast 2-bit counter
2) Build a slow 62-bit counter, with enable
3) Use enable = q[1]&q[0]
4) latch the slow counter using the enable as well

You get a full 4 cycles for the carry to ripple through the upper 62
bits.  Be careful in timing analysis.  Some systems let you specify that
the carry chain is a multi-cycle path.  Other's force you to ignore
these paths with falsepath commands.

(Thanks Bill for the help).

Erez.


"Peter Alfke" <peter@xilinx.com> wrote in message
news:3FB0230F.3FC83434@xilinx.com...
> I would suggest detecting FFFF and generating a wait state or two when
> you reach that value. The probability is one in 64K, so it should hardly
> have any impact on performance.
>
> Peter Alfke
> ==================
> Erez Birenzwig wrote:
> >
> > To be more precise the implementation requires the calculation of:
> > a = a + 1
> >
> > When a is a 64bit vector, every clock cycle at 200MHz, using a
virtexII-6
> > FPGA.
> >
> > Erez.
> >
> > "Peter Alfke" <peter@xilinx.com> wrote in message
> > news:3FB01875.A2C23F2F@xilinx.com...
> > > "Counter" can mean many things.
> > > If you need a synchronous counter that gives you the updated value
> > > before the next count pulse comes in, that is a demanding design and
may
> > > have timing problems at 200 MHz.
> > >
> > > If, at the other extreme, you just need a counter that can resolve 200
(
> > > or 500+ ) MHz, and you can wait some nanoseconds before you read the
> > > final count value, that is trivial. In the extreme case you would just
> > > concatenate 2-bit Johnson counters (at least at the input end), one
> > > slice clocking the next. And there are many variations on this theme.
> > > I built a 400 MHz frequency counter 5 years ago with
XC4002XL...Playing
> > > around, aiming at 1 GHz now.
> > >
> > > Peter Alfke, Xilinx Applications
> > >
> > >
> > > Erez Birenzwig wrote:
> > > >
> > > > Hi,
> > > >
> > > >   I'm trying to write some code for a 64 bit counter for a VirtexII.
> > > >
> > > >   The problem I'm facing is that it has to run at least at 200MHz,
and
> > > > therefore
> > > > a simple "a = a + 1" doesn't work (Xilinx rate the 64b counter to
> > 114MHz).
> > > >
> > > >   I've tried a split approach with four smaller counters and a
selector
> > > > depending on the carry out of the previous stages but it only got me
to
> > > > about
> > > > 180MHz.
> > > >
> > > >   Did anyone ever had a similar problem and solved it ?
> > > >   Unfortunately I'm not familiar with a pipelined implementation,
I'll
> > be
> > > > happy
> > > > to learn one.
> > > >
> > > >   Many thanks,
> > > >   Erez.



Article: 62905
Subject: Layout examples
From: "Jason Berringer" <look_at_bottom_of@email.com>
Date: Mon, 10 Nov 2003 20:14:14 -0500
Links: << >>  << T >>  << A >>
Hello all,

I was wondering if anyone (maybe some of the guru's or Xilinx folk, have
some pictures (jpegs) of some layout examples of various packages and parts.
I have read many app notes about bypass caps, etc. and everything in them
explains how many caps, and values for a good decoupling system, however the
one thing that they all say is get them as close to the pin as possible
(which could mean a lot of different things). For example I'm using the
PQ208 package for the XC2S100 device and I mount all of my bypass caps on
the underside of the PCB, primarily due to the fact that I like to provide a
clean exit route from the IC on the top of the board. The trouble then is
that the more caps you have the more vias you need, the more perforated your
planes become. I hope that you see where I'm going with this.

I would like to see if possible some proven layouts showing where the caps
are mounted and there possition relative to the power pins (and see how
close they are). I've seen a lot of layouts where there are a few caps in
the center of the IC on the underside of the board, but this does not lend
itself nicely to the idea of being as  close as possible to the pins. I have
also seen the Xilinx app note on BGA routing which is very helpful, but
again no capacitor placement is shown.

Can someone post some pictures or email them to me if they feel so inclined
of some design proven layouts. I would greatly appreciate it and I'm sure
that others would as well. Maybe Xilinx could add a few pics to their app
notes in future. As I stated I'm currently using a PQ208 package and since
my desing are progressing I am considering a move to a BGA package. Since
it's a bit risky for the first design I want to see some examples, as well
as examples from other packages available.

Any help would be greatly appreciated.

Thanks,

Jason

jberringerattrace-logicdotcom



Article: 62906
Subject: Re: Announcement
From: Eric Smith <eric-no-spam-for-me@brouhaha.com>
Date: 10 Nov 2003 17:25:00 -0800
Links: << >>  << T >>  << A >>
jon@beniston.com (Jon Beniston) writes:
> I wrote my own clone earlier this year (just haven't got around to
> releasing it yet). I spent quite a bit of time studying the patent
> issues, and believe that
> you should be able to implement the basic V4 instruction set (This
> doens't include Thumb). The only real hurdle is then likey to be
> patent 5,386,563 which deals with the exception processing mechanism.
> However, I believe this patent to be invalid, as there is a
> significant amount of prior art (Search for "ARM's dubious patents" in
> comp.arch).

If you only need binary compatibility with user-mode ARM software, you
can implement a different exception handling mechanism and avoid the
patented technique entirely.

Article: 62907
Subject: Re: Implementing a very fast counterin VirtexII
From: "fe" <notvalid@nowhere.com>
Date: Mon, 10 Nov 2003 21:12:25 -0500
Links: << >>  << T >>  << A >>
"Erez Birenzwig" <erez_birenzwig@hotmail.com> wrote in message
news:9eUrb.2$%o4.221@news.xtra.co.nz...
> Hi,
>
>   I'm trying to write some code for a 64 bit counter for a VirtexII.
>
>   The problem I'm facing is that it has to run at least at 200MHz, and
> therefore
> a simple "a = a + 1" doesn't work (Xilinx rate the 64b counter to 114MHz).
>
>   I've tried a split approach with four smaller counters and a selector
> depending on the carry out of the previous stages but it only got me to
> about
> 180MHz.
>
>   Did anyone ever had a similar problem and solved it ?
>   Unfortunately I'm not familiar with a pipelined implementation, I'll be
> happy
> to learn one.
>


example 64bit pipelined counter with two 32bit counter.
(Please view in fixed-width font, e.g. Courier)
-- (+) : adder (count)
-- [ ] : dff
--
--     +-----------+
--     |           |
-- 1--(+)-+-[31:0]-+---------[31:0]-----+
--        |                             |
--        +-[carry]-+                   |
--                  |                   |
--                  |  +------------+   |
--                  |  |            |   |
--                  +-(+)---[63:32]-+---+---cnt(63:0)

  ps_cnt_pipeline : process(i_rst_an, i_clk) is
    constant C_CNT_WIDTH2 : positive := G_CNT_WIDTH / 2;
    variable v_cnt1_d : unsigned(C_CNT_WIDTH2 downto 0);
    variable v_cnt1_q1 : unsigned(C_CNT_WIDTH2-1 downto 0);
    variable v_cnt1_q2 : unsigned(C_CNT_WIDTH2-1 downto 0);
    variable v_carry_q1 : unsigned(0 downto 0);
    variable v_cnt2_q2 : unsigned(G_CNT_WIDTH-C_CNT_WIDTH2-1 downto 0);
  begin
    if i_rst_an = '0' then
      v_carry_q1 := (others => '0');
      v_cnt1_q1 := (others => '0');
      v_cnt1_q2 := (others => '0');
      v_cnt2_q2 := (others => '0');
    elsif rising_edge(i_clk) then
      v_cnt1_d := ('0' & v_cnt1_q1) + 1;
      v_cnt1_q2 := v_cnt1_q1;
      v_cnt2_q2 := v_cnt2_q2 + v_carry_q1;
      v_carry_q1(0) := v_cnt1_d(C_CNT_WIDTH2);
      v_cnt1_q1 := v_cnt1_d(C_CNT_WIDTH2-1 downto 0);
    end if;
    o_cnt_q <= std_logic_vector(v_cnt2_q2 & v_cnt1_q2);
  end process;

regards,
fe


>   Many thanks,
>   Erez.
>




Article: 62908
Subject: Re: ISE 5.2 to 6.1
From: Marc Guardiani <marc@guardiani.com>
Date: Tue, 11 Nov 2003 03:32:43 GMT
Links: << >>  << T >>  << A >>
KD wrote:

> Hopefully, someone will stumble on a solution, or Xilinx will fix it in a
> service pack. If not, we'll be stuck on 5.2 ;(

I'd be happy to be stuck with 5.2 as I seem to be stuck with 4.2. Trying 
to port a 4.2 design to 5.1, 5.2, and 6.1 results in failure. The 
failure occurs attempting to synthesize the simple top level schematic.

Marc


Article: 62909
Subject: fitting Xilinx CPLD - I/O Pin Termination
From: "Valentin Tihomirov" <valentin@abelectron.com>
Date: Tue, 11 Nov 2003 05:35:10 +0200
Links: << >>  << T >>  << A >>
It is not the same as Programmable GND Pins on Unused I/O. I can choose
between Keeper and Float. There is no information about this property.



Article: 62910
Subject: Re: Implementing a very fast counterin VirtexII
From: Goran Bilski <goran@xilinx.com>
Date: Tue, 11 Nov 2003 07:58:19 +0100
Links: << >>  << T >>  << A >>
How do you use the counter?
Do you read current counter values or are you only interested when it 
reached zero?

Gran

Erez Birenzwig wrote:

>Hi,
>
>  I'm trying to write some code for a 64 bit counter for a VirtexII.
>
>  The problem I'm facing is that it has to run at least at 200MHz, and
>therefore
>a simple "a = a + 1" doesn't work (Xilinx rate the 64b counter to 114MHz).
>
>  I've tried a split approach with four smaller counters and a selector
>depending on the carry out of the previous stages but it only got me to
>about
>180MHz.
>
>  Did anyone ever had a similar problem and solved it ?
>  Unfortunately I'm not familiar with a pipelined implementation, I'll be
>happy
>to learn one.
>
>  Many thanks,
>  Erez.
>
>
>
>  
>


Article: 62911
Subject: Re: VirtexII-Pro: Why is ICAP slower than SelectMAP?
From: Sean Durkin <23@iis.42.de>
Date: Tue, 11 Nov 2003 09:07:47 +0100
Links: << >>  << T >>  << A >>
PO Laprise wrote:
> So if you send the internal signals that currently connect to the ICAP 
> off-chip and back to the SelectMAP pins instead, you can get a speed boost?
That might work, if you have that many I/O-pins to spare in your 
design... But still it's sort of an "ugly" solution. :)

-- 
Sean Durkin
Fraunhofer Institute for Integrated Circuits (IIS)
Am Wolfsmantel 33, 91058 Erlangen, Germany

mailto:23@iis.42.de
([23 , 42] <=> [durkinsn , fraunhofer])


Article: 62912
Subject: Are modules that are not floorplanned still functional?
From: merlin_jiang@hotmail.com (Jiang)
Date: 11 Nov 2003 00:28:19 -0800
Links: << >>  << T >>  << A >>
Hello, FPGA friends,

I'm trying to implement a simple clock bypassing on my Virtex-II 6000 with an
FF1152 board. My ISE is version 5.2.03i. In the beginning I could do a trivial
bypassing using Virtex 2000E with a BG560 board:

input clk;
output out_clk;
wire out_clk;

out_clk=clk;

But on my Virtex-II 6000 it didn't work. It's fine since that I could try
FDDRRSE to accomplish the same task. My code evolved as:

input clk;
output out_clk;
wire out_clk;

FDDRRSE fddrrse_0 (
.Q (out_clk), 
.C0 (clk), 
.C1 (~clk), 
.CE (1'b1), 
.D0 (1'b1), 
.D1 (1'b0), 
.R (1'b0), 
.S (1'b0)
);

After browsing the old messages of this news group, I didn't know why the above
code failed again. The output port just stuck at logic 0, and it looked like
that fddrrse_0 was power-up and did nothing. Then I tried to use Xilinx
floorplanner to see what FDDRRSE was. Here I found it not
being floorplanned. Well, maybe it was too trivial to be floorplanned. Hence
I used Xilinx FPGA editor to see what the connections were like. However,
besides my fddrrse_0, I didn't find any nets other than the I/O port between
the inferred input and output buffers and some VCCs. And it looked like
clk --> clk_IBUFG --> out_clk was the whole route.

I believe I might have missed something there such that neither could I
bypass clock signals correctly nor could I understand what Xilinx floorplanner
and FPGA editor told me.

Please give me some suggestion to understand even some parts of this problem.
Thank you :-)

Regards,
Merlin

Article: 62913
Subject: Re: Implementing a very fast counterin VirtexII
From: Uwe Bonnes <bon@elektron.ikp.physik.tu-darmstadt.de>
Date: Tue, 11 Nov 2003 08:58:53 +0000 (UTC)
Links: << >>  << T >>  << A >>
Erez Birenzwig <erez_birenzwig@hotmail.com> wrote:

:> > > >
:> > > >   Many thanks,
:> > > >   Erez.

Argh.

Why do so many people fullquote? Is it so hard to delete non-needed parts of
the posting they refer to? 

Fullquoting spoils the archives and make them harder to use. So people don't
search the archive but instead ask the same questions all over. That makes
the newsgroup hard to use.

Bye

-- 
Uwe Bonnes                bon@elektron.ikp.physik.tu-darmstadt.de

Institut fuer Kernphysik  Schlossgartenstrasse 9  64289 Darmstadt
--------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------

Article: 62914
Subject: Transforming vector position to binary value
From: andres.vazquez@gmx.de (Vazquez)
Date: 11 Nov 2003 01:02:00 -0800
Links: << >>  << T >>  << A >>
Hi @all,

I have a vector with 32 bit [31 downto 0].


After some calculations the vector could look like that:

a)0000 0000 0000 0000 0000 0000 1000 0000  
 or
b)0000 0000 1000 0000 0000 0100 0000 0000


How can I transform the position(s) of the one(s) in the
vector to a corresponding binary value?

for example in a) '1' at position 7 of the vector =>
binary value would be: b111

Is there some simple and fast possibility to make this transformation?

Thanks a lot.

Best regards

Article: 62915
Subject: Re: Transforming vector position to binary value
From: "Jonathan Bromley" <jonathan.bromley@doulos.com>
Date: Tue, 11 Nov 2003 09:23:39 -0000
Links: << >>  << T >>  << A >>
"Vazquez" <andres.vazquez@gmx.de> wrote in message
news:eee19a7a.0311110102.5b8b5e35@posting.google.com...
> I have a vector with 32 bit [31 downto 0].
> After some calculations the vector could look like that:
>
> a)0000 0000 0000 0000 0000 0000 1000 0000
>  or
> b)0000 0000 1000 0000 0000 0100 0000 0000
>
> How can I transform the position(s) of the one(s) in the
> vector to a corresponding binary value?
> for example in a) '1' at position 7 of the vector =>
> binary value would be: b111
>
> Is there some simple and fast possibility to make this transformation?

How do you create a "binary value" representing the word that
has more than one bit set?

My favourite onehot-to-binary recoder is:

  variable onehot: std_logic_vector(LOTS downto 0);
  variable binary: std_logic_vector(FEWER downto 0);
  ...
  binary := (others => '0');
  for i in onehot'range loop
    binary := binary or std_logic_vector(to_unsigned(i));
  end loop;

Verilog version available at extra cost :-)

This optimises well (to a collection of wide OR gates) in
every synthesis tool I've tried.  But it will fail horribly
if more than one bit of the input "onehot" word is set.
What do you expect to happen, in case (b)?
--

Jonathan Bromley, Consultant

DOULOS - Developing Design Know-how
VHDL * Verilog * SystemC * Perl * Tcl/Tk * Verification * Project Services

Doulos Ltd. Church Hatch, 22 Market Place, Ringwood, Hampshire, BH24 1AW, UK
Tel: +44 (0)1425 471223                    mail: jonathan.bromley@doulos.com
Fax: +44 (0)1425 471573                           Web: http://www.doulos.com

The contents of this message may contain personal views which
are not the views of Doulos Ltd., unless specifically stated.




Article: 62916
(removed)


Article: 62917
(removed)


Article: 62918
Subject: Multiple clock domains in a FPGA (using DLL's)
From: takkaya@hotmail.com (takkaya)
Date: 11 Nov 2003 01:58:43 -0800
Links: << >>  << T >>  << A >>
I am targeting a Spartan IIE (400E) device with four global clock
buffers (BUFG) and four DLL's.

But I need five clock domains 25MHz(clkin, DLL1), 50MHz (clk2x, DLL1) 
and 30MHz (clkdv, DLL2), 60MHz (clkin, DLL2), 120MHz (clk2x, DLL2) in
my design.

I know that it is not allowed to use more than 2 BUFG per DLL. 

I would like to use the DLL's to have a zero propagation delay and low
clock skew between output clock signals distributed throughout the
device. The primary global nets are driven by global buffers (25, 50,
60 and 120 MHz).

The 30 MHz clock domain (internal) is not so critical, so maybe I can
use a secondary global nets?

How can I drive the secondary global nets with an output of the DLL
e.g. the 30 MHz?

Thanks in advance.

Article: 62919
Subject: Re: Transforming vector position to binary value
From: "Valentin Tihomirov" <valentin@abelectron.com>
Date: Tue, 11 Nov 2003 13:06:31 +0200
Links: << >>  << T >>  << A >>
If i understand you correctly, you request for a feature called priority
encoding. It also resolves cases with two or more 1s using priority.



Article: 62920
Subject: Code for accessing CF cards on Cyclone dev.board
From: "Jeroen" <dev@null.com>
Date: Tue, 11 Nov 2003 13:00:26 +0100
Links: << >>  << T >>  << A >>
Hi,

I'm using a Altera Nios Cyclone dev.board (and the ref-32 design) and I want
to use the CF slot for a testapplication. I'm looking for some C code to
access the CF, so that I won't have to write it myself. Just code to issue
IDE commands and get the data from the CF. No filesystem etc. Does someone
know where I can find such code?

Jeroen



Article: 62921
Subject: Logic implementation in SRAM/OTP FPGAs
From: lenz19@gmx.de (lenz)
Date: 11 Nov 2003 04:39:43 -0800
Links: << >>  << T >>  << A >>
Hello,

I have a question concerning the logic implementation techniques of
SRAM FPGAs and OTP FPGAs.

Logic in Xilinx FPGAs is implemented in LUTs. Logic in Quicklogic
FPGAs is implemented in a multiplexer structure.

Why does these two programming technologies use different techniques
to implement logic ?

Thanks in advance,
Mark Lenz

Article: 62922
Subject: Re: BGA packages in high vibration environments
From: "David Kinsell" <kinsell@poboxyz.com>
Date: Tue, 11 Nov 2003 13:03:26 GMT
Links: << >>  << T >>  << A >>

"Ron Huizen" <rhuizen@bittware.com> wrote in message news:vpfh7f3e2gc2a3@corp.supernews.com...
> Rick,
>
> I'd certainly be interested in more info on the fiber microscope you
> mentioned.  Debugging designs with lots of big BGAs is tough enough without
> wondering whether it's an assembly issue or not, and traditional xray
> techniques are good for showing shorts, but no so good for opens ...
>
> -----
> Ron Huizen
> BittWare

There's also JTAG tools that can read and write arbitrary values to
I/O pins.  Roughly $1K for benchtop systems, $10K for a production
tester.  If the BGA is hooked to other chips with JTAG, you can make
a rather complete test.

And of course there's traditional bed-of-nails, not used much due to
cost of implementing on proto hardware.

Dave Kinsell



Article: 62923
Subject: Re: Transforming vector position to binary value
From: "Jonathan Bromley" <jonathan.bromley@doulos.com>
Date: Tue, 11 Nov 2003 13:22:15 -0000
Links: << >>  << T >>  << A >>
"Jonathan Bromley" <jonathan.bromley@doulos.com> wrote

[Before checking his response!]

in message news:boq9r6$t2l$1$8302bc10@news.demon.co.uk...

[...]

> My favourite onehot-to-binary recoder is:
[...]
>   binary := (others => '0');
>   for i in onehot'range loop
>     binary := binary or std_logic_vector(to_unsigned(i));
>   end loop;

Whoops.  That should have been...

  binary := (others => '0');
  for i in onehot'range loop
    if onehot(i) = '1' then
      binary := binary or std_logic_vector(to_unsigned(i));
    end if;
  end loop;

It's usually a good idea to make the output somewhat
dependent on the input  ;-)   Sorry.

--

Jonathan Bromley, Consultant

DOULOS - Developing Design Know-how
VHDL * Verilog * SystemC * Perl * Tcl/Tk * Verification * Project Services

Doulos Ltd. Church Hatch, 22 Market Place, Ringwood, Hampshire, BH24 1AW, UK
Tel: +44 (0)1425 471223                    mail: jonathan.bromley@doulos.com
Fax: +44 (0)1425 471573                           Web: http://www.doulos.com

The contents of this message may contain personal views which
are not the views of Doulos Ltd., unless specifically stated.




Article: 62924
Subject: XILINX Foundation Series 3_1i Problem with installation...
From: " " <zlogic@udm.ru>
Date: Tue, 11 Nov 2003 17:31:02 +0400
Links: << >>  << T >>  << A >>
Hi, ALL.

Problem with installation subj.
In time installation  the program java.exe is under abnormal condition
finished.
It happens in WIN 98 and in WIN XP. Processor - CELERON 1700.
What to do, help me, please.

Serg Zorin.





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