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Hello!
I'm performing a VHDL design for a Xilinx Spartan2-FPGA that implements a
synchronous FIFO.
Actually, at the moment, I'm just using the Application Note Design offered
on the Xilinx Wepage (XAPP175).
So far, so good, I've got a testbench to be run in Modelsim.
But every time it tells me the following things:
___________________________________________________________________
# Reading D:/Programme/Modeltech_xe/tcl/vsim/pref.tcl
# do fifo_c_tb.fdo
# ** Warning: (vlib-34) Library already exists at "work".
# Model Technology ModelSim XE II vcom 5.6e Compiler 2002.10 Oct 22 2002
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package std_logic_arith
# -- Loading package std_logic_unsigned
# -- Compiling entity fifoctlr_cc
# Model Technology ModelSim XE II vcom 5.6e Compiler 2002.10 Oct 22 2002
# -- Loading package standard
# -- Compiling architecture fifoctlr_cc_hdl of fifoctlr_cc
# -- Loading package std_logic_1164
# -- Loading package std_logic_arith
# -- Loading package std_logic_unsigned
# -- Loading entity fifoctlr_cc
# WARNING[1]: fifo_c.vhd(97): No default binding for component: "bufgp". (No
entity named "bufgp" was found)
# WARNING[1]: fifo_c.vhd(110): No default binding for component:
"ramb4_s8_s8". (No entity named "ramb4_s8_s8" was found)
# Model Technology ModelSim XE II vcom 5.6e Compiler 2002.10 Oct 22 2002
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package std_logic_arith
# -- Loading package std_logic_unsigned
# -- Compiling entity fifo_c_tb
# Model Technology ModelSim XE II vcom 5.6e Compiler 2002.10 Oct 22 2002
# -- Loading package standard
# -- Compiling architecture test of fifo_c_tb
# -- Loading package std_logic_1164
# -- Loading package std_logic_arith
# -- Loading package std_logic_unsigned
# -- Loading entity fifo_c_tb
# -- Loading entity fifoctlr_cc
# WARNING[1]: fifo_c_tb.vhd(46): Types do not match for port write_data_in
# WARNING[1]: fifo_c_tb.vhd(46): A use of this default binding for this
component instantiation will result in an elaboration error.
# WARNING[1]: fifo_c_tb.vhd(46): Types do not match for port read_data_out
# WARNING[1]: fifo_c_tb.vhd(46): A use of this default binding for this
component instantiation will result in an elaboration error.
# WARNING[1]: fifo_c_tb.vhd(46): Types do not match for port fifocount_out
# WARNING[1]: fifo_c_tb.vhd(46): A use of this default binding for this
component instantiation will result in an elaboration error.
# vsim -L xilinxcorelib -lib work -t 1ps testbench
# ** Warning: A ModelSim starter license was detected and will be used, even
though you have installed ModelSim XE. You should obtain an XE license in
order to access ModelSim XE's full capabilities.# Loading
D:/Programme/Modeltech_xe/win32xoem/../std.standard
# ** Error: (vsim-3173) Entity 'work.testbench' has no architecture.
# Error loading design
# Error: Error loading design
# Pausing macro execution
# MACRO ./fifo_c_tb.fdo PAUSED at line 9
__________________________________________________________________
The two components RAMB4_S1 and BUFGP should be in a library - so i don't
understand why it's not found.
I don't understand, why the ports don't match - they are really the same
type (most of them std_ulogic(_vector)).
And at the end, why does it say "Entity 'work.testbench' has no
architecture" ?
My idea is that i need a configuration file. But i'm doing everything out of
Xilinx ISE Webpack, there i never need a configuration file, or do i? I'm
quite out of understanding at the moment...:(.
My TestBench-Code (at least parts of it) was:
___________________________________________
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.conv_integer;
use ieee.std_logic_arith.conv_std_logic_vector;
entity fifo_c_tb is
end fifo_c_tb;
architecture test of fifo_c_tb is
component fifoctlr_cc
port (clock_in: in std_ulogic;
read_enable_in: in std_ulogic;
write_enable_in: in std_ulogic;
write_data_in: in std_ulogic_vector(15 downto 0);
fifo_gsr_in: in std_ulogic;
read_data_out: out std_ulogic_vector(15 downto 0);
full_out: out std_ulogic;
empty_out: out std_ulogic;
fifocount_out: out std_ulogic_vector(7 downto 0));
end component;
constant clk_delay_c : time := 50 ns;
signal clock_s: std_ulogic;
signal read_enable_s: std_ulogic;
signal write_enable_s: std_ulogic;
signal write_data_s: std_ulogic_vector(15 downto 0);
signal fifo_gsr_s: std_ulogic;
signal read_data_s: std_ulogic_vector(15 downto 0);
signal full_s: std_ulogic;
signal empty_s: std_ulogic;
signal fifocount_s: std_ulogic_vector(7 downto 0);
begin
u1: fifoctlr_cc
port map(
clock_in => clock_s,
read_enable_in => read_enable_s,
write_enable_in => write_enable_s,
write_data_in => write_data_s,
fifo_gsr_in => fifo_gsr_s,
read_data_out => read_data_s,
full_out => full_s,
empty_out => empty_s,
fifocount_out => fifocount_s
);
-- *** Test Bench - User Defined Section ***
clock: process
begin
[...]
__________________________________________________
please help me!!
Thank you, Simone
-------------------------------------------------------------------
Simone Winkler
Mechatronik-Studentin / Universität Linz
simone.winkler@students.jku.at
ICQ: 20212150
Article: 62151arkaitz wrote: > Thanks a lot John!! > > The problem what you've told me. I didn't have connected the to the IOPB. I'm very glad to hear that - I probably should have thought of it earlier! Given that this topic comes up pretty often (and I get a lot of private email about it too) Xilinx might consider documenting more explicitly the process for executing code from external memory on Microblaze... Cheers, JohnArticle: 62152
This happens because Modelsim is not finding the appropriate library declaring bufg... at the top of your vhdl file when you include the libraries add something like -- synopsys translate_off library UNISIM; use UNISIM.VCOMPONENTS.ALL; -- synopsys translate_on Garry Allen not that i have ever been tricked by this problem in the past. No not at allArticle: 62153
Couple of things: 1) This question belongs in comp.lang.vhdl, probably. 2) Find the Xilinx primitives (deep in your xilinx directory) and include them in the simulation file list. ModelSim is probably so upset about not finding them (missing RAM makes for a poor FIFO) that it's dumping the whole thing. HTH, SH "Simone Winkler" <simone.winkler@gmx.at> wrote in message news:<1066686601.590067@news.liwest.at>... > Hello! > > I'm performing a VHDL design for a Xilinx Spartan2-FPGA that implements a > synchronous FIFO. > Actually, at the moment, I'm just using the Application Note Design offered > on the Xilinx Wepage (XAPP175). > So far, so good, I've got a testbench to be run in Modelsim. > But every time it tells me the following things: > > ___________________________________________________________________ > > # Reading D:/Programme/Modeltech_xe/tcl/vsim/pref.tcl > # do fifo_c_tb.fdo > # ** Warning: (vlib-34) Library already exists at "work". > # Model Technology ModelSim XE II vcom 5.6e Compiler 2002.10 Oct 22 2002 > # -- Loading package standard > # -- Loading package std_logic_1164 > # -- Loading package std_logic_arith > # -- Loading package std_logic_unsigned > # -- Compiling entity fifoctlr_cc > # Model Technology ModelSim XE II vcom 5.6e Compiler 2002.10 Oct 22 2002 > # -- Loading package standard > # -- Compiling architecture fifoctlr_cc_hdl of fifoctlr_cc > # -- Loading package std_logic_1164 > # -- Loading package std_logic_arith > # -- Loading package std_logic_unsigned > # -- Loading entity fifoctlr_cc > # WARNING[1]: fifo_c.vhd(97): No default binding for component: "bufgp". (No > entity named "bufgp" was found) > # WARNING[1]: fifo_c.vhd(110): No default binding for component: > "ramb4_s8_s8". (No entity named "ramb4_s8_s8" was found) > # Model Technology ModelSim XE II vcom 5.6e Compiler 2002.10 Oct 22 2002 > # -- Loading package standard > # -- Loading package std_logic_1164 > # -- Loading package std_logic_arith > # -- Loading package std_logic_unsigned > # -- Compiling entity fifo_c_tb > # Model Technology ModelSim XE II vcom 5.6e Compiler 2002.10 Oct 22 2002 > # -- Loading package standard > # -- Compiling architecture test of fifo_c_tb > # -- Loading package std_logic_1164 > # -- Loading package std_logic_arith > # -- Loading package std_logic_unsigned > # -- Loading entity fifo_c_tb > # -- Loading entity fifoctlr_cc > # WARNING[1]: fifo_c_tb.vhd(46): Types do not match for port write_data_in > # WARNING[1]: fifo_c_tb.vhd(46): A use of this default binding for this > component instantiation will result in an elaboration error. > # WARNING[1]: fifo_c_tb.vhd(46): Types do not match for port read_data_out > # WARNING[1]: fifo_c_tb.vhd(46): A use of this default binding for this > component instantiation will result in an elaboration error. > # WARNING[1]: fifo_c_tb.vhd(46): Types do not match for port fifocount_out > # WARNING[1]: fifo_c_tb.vhd(46): A use of this default binding for this > component instantiation will result in an elaboration error. > # vsim -L xilinxcorelib -lib work -t 1ps testbench > # ** Warning: A ModelSim starter license was detected and will be used, even > though you have installed ModelSim XE. You should obtain an XE license in > order to access ModelSim XE's full capabilities.# Loading > D:/Programme/Modeltech_xe/win32xoem/../std.standard > # ** Error: (vsim-3173) Entity 'work.testbench' has no architecture. > # Error loading design > # Error: Error loading design > # Pausing macro execution > # MACRO ./fifo_c_tb.fdo PAUSED at line 9 > __________________________________________________________________ > > > The two components RAMB4_S1 and BUFGP should be in a library - so i don't > understand why it's not found. > I don't understand, why the ports don't match - they are really the same > type (most of them std_ulogic(_vector)). > And at the end, why does it say "Entity 'work.testbench' has no > architecture" ? > My idea is that i need a configuration file. But i'm doing everything out of > Xilinx ISE Webpack, there i never need a configuration file, or do i? I'm > quite out of understanding at the moment...:(. > > > > My TestBench-Code (at least parts of it) was: > ___________________________________________ > > library ieee; > use ieee.std_logic_1164.all; > use ieee.std_logic_unsigned.conv_integer; > use ieee.std_logic_arith.conv_std_logic_vector; > > entity fifo_c_tb is > end fifo_c_tb; > > architecture test of fifo_c_tb is > component fifoctlr_cc > port (clock_in: in std_ulogic; > read_enable_in: in std_ulogic; > write_enable_in: in std_ulogic; > write_data_in: in std_ulogic_vector(15 downto 0); > fifo_gsr_in: in std_ulogic; > read_data_out: out std_ulogic_vector(15 downto 0); > full_out: out std_ulogic; > empty_out: out std_ulogic; > fifocount_out: out std_ulogic_vector(7 downto 0)); > end component; > > constant clk_delay_c : time := 50 ns; > > signal clock_s: std_ulogic; > signal read_enable_s: std_ulogic; > signal write_enable_s: std_ulogic; > signal write_data_s: std_ulogic_vector(15 downto 0); > signal fifo_gsr_s: std_ulogic; > signal read_data_s: std_ulogic_vector(15 downto 0); > signal full_s: std_ulogic; > signal empty_s: std_ulogic; > signal fifocount_s: std_ulogic_vector(7 downto 0); > > begin > u1: fifoctlr_cc > port map( > clock_in => clock_s, > read_enable_in => read_enable_s, > write_enable_in => write_enable_s, > write_data_in => write_data_s, > fifo_gsr_in => fifo_gsr_s, > read_data_out => read_data_s, > full_out => full_s, > empty_out => empty_s, > fifocount_out => fifocount_s > ); > > > -- *** Test Bench - User Defined Section *** > clock: process > begin > [...] > __________________________________________________ > > please help me!! > > Thank you, Simone > > ------------------------------------------------------------------- > Simone Winkler > Mechatronik-Studentin / Universität Linz > simone.winkler@students.jku.at > ICQ: 20212150Article: 62154
before you start the simulation, you should compile the X's library for the simulator (use the 'compxlib' command). There's several documents on X's website mentioned how to do this. "Simone Winkler" <simone.winkler@gmx.at> ??????:1066686601.590067@news.liwest.at...Article: 62155
On Mon, 20 Oct 2003, Rene Tschaggelar wrote: > > The G8 membership might distort the picture a bit. > South of say Bolognia there is not much Technology anymore. > A few Tomatoes and Olives plus lots of companies using the cheap > labour for simple jobs. > > Rene > even if I agree on the overall picture, in south-italy there are R&D and manufacturing plants of companies like ST-microelectronics, Ericson and a few others. I think that there is a potential market for FPGA. Tullio GrassiArticle: 62156
H. Peter Anvin <hpa@zytor.com> wrote in message news:<bn18l8$od1$1@cesium.transmeta.com>... > Followup to: <belkb.1647$2O3.332@newssvr14.news.prodigy.com> > By author: JoeG <JoeG@spam.net> > In newsgroup: comp.arch.fpga > > > > I'm glad I didn't have access to the Inet during my college days, as my > > efforts in class/homework would not have been as rewarding and industrious. > > > > I *am* glad that I had access to the Internet at my university; it was > both a great study tool and provided the opportunity for branching out > in areas I would otherwise never have expected -- this is how I got > involved with Linux, back when noone had heard of it. > > Like anything else it can be abused. Students asking people to do > their homework for them figured back then... these days they tend to > do it from anonymous yahoo accounts, however, which means that it's > not just ignorance, but that they know they're cheating. > > -hpa Like many oldtimers I also never had a PC till way after starting work. I am hoping that when I send my kids off to school in a few years that they never see a darn pc at all, maybe they might have an accredited Mathematics & Science teacher instead, but I don't expect too much these days compared to my own fortunate education. By the way does anybody graduate from college these days without having a PC forced on them and if so could they get a job based on more limited (selective) computer exp ie a nice old mainframe or workstations in modern talk? johnjaksonATusaDOTcomArticle: 62157
Rene Tschaggelar <none@none.none> wrote in message news:<2e2341ee57ca2c93136ba7178992b4a1@news.teranews.com>... > Lorenzo Lutti wrote: > > "Ljubisa Bajic" <eternal_nan@yahoo.com> ha scritto nel messaggio > > news:9b0afb2c.0310190955.aa5708d@posting.google.com... > > > > > >>It is incredible that in response to an inquiry about > >>technical workshops you found it appropriate to insult > >>some countries (in fact whole regions!; even > >>continents!!), > > > > > > Insult?! I have simply said that some multinationals consider Italy > > (from a *business* point of view) just like countries that are > > objectively far less industrialized than us. Italy is in the G8, Libia > > and Poland aren't even in the G20. When I say we "deserve" better, I > > mean that we could have a lot more technological resources to invest in > > FPGA world. This is a fact, not an offense. > > > > I didn't mean to insult anyone! If I did so, I apologize to whoever > > could have been offended. Probably the guilt is my bad english, I'm not > > able to express all my thoughts exactly. :) > > > > The G8 membership might distort the picture a bit. > South of say Bolognia there is not much Technology anymore. > A few Tomatoes and Olives plus lots of companies using the cheap > labour for simple jobs. > > Rene Italy isn't completely out of the picture, I mean ST is in top 10 of world semi comps which used to be Thomson + SGS + Mostek + Inmos etc, still mostly Franco Italian UK, last I heard was still run by SGS guy (Pastorio ??). And they even have design centers in Sicily last time I heard. Still if Xilinx doesn't show, the Altera guy said they would. I am a bit surprised to hear UK isn't on the map, that can't be right. johnjaksonATusaDOTcomArticle: 62158
Hello Antti, Thanks for answering to my queries. I wonder if you could help me with this. Here is my problems. The C-code, I got, is written for parallel interfacing with ISP1581. I wonder, if I have to modify my code to use it as GPIO pins in Microblaze. I still haven't got clear understanding of configuring Microblaze. I have been using EDK 3.2 and ISE 5.2. And I also need to setup temporary SRAM and its controller on FPGA so that the data communication could be established between PC and SRAM through USB. If you have any suggestion or experience relating this, please pass it on. Thanks, Om antti@case2000.com (Antti Lukats) wrote in message news:<80a3aea5.0310192220.1a854dc7@posting.google.com>... > gupt0009@flinders.edu.au (Om) wrote in message news:<b87a9948.0310191846.8a4d786@posting.google.com>... > > I have been implementing a high speed controller for USB 2.0 > > communication on Xilinx VirtexII FPGA, which interfaces to USB bus > > through Philips ISP1581 device. I don't know how to go about it as I'm > > a very new to USB stuffs. > > > > I have got a choice of using MicroBlaze softcore microprocessor, but > > currently, I'm encountering lots of trouble downloading it onto the > > FPGA using already written C-code for ISP1581 device. > > where is the problem? > have you connected it successfully to microlaze PLB bus? > > > So, I would be grateful if you could be able to give me some > > suggestions or directions on how to go about it. I wonder, if USB 2.0 > > core is available for ISP1581 device. > > there is no need for USB core for ISP1581 as IS1581 is the core! > you only need interfaces to ISP1581 to access from microblaze and posssible > use DMAArticle: 62159
Protel or Altium as they are now called.. have a long and very good users group. It is referenced by Altium but I doubt there are many VHDL users there as Protel is a PCB CAD package which has only lately started doing VHDL. You can Try tho.. but you have to have an official licensed version of DXP ;-) Simon dxp at forums dot altium dot com "Dieter Keldenich" <dieterkeldenich@epost.de> wrote in message news:3f945728$0$19101$9b4e6d93@newsread2.arcor-online.net... > Hi Rene, > > I do not find any Altium- or DXP-group here on my news server. Also on > www.altium.com, I only find an info, that there will come up a forum soon. > Where can I find the altium group? > > thanks in advance > Dieter > > > "Rene Tschaggelar" <none@none.none> schrieb im Newsbeitrag > news:a91788f472d3dfa287e0664cd79fe203@news.teranews.com... > > jakab tanko wrote: > > > "Rene Tschaggelar" <none@none.none> wrote in message > > > news:65d1183ec9a699ea0d4f9acbd7c3a815@news.teranews.com... > > > > > >>Dieter Keldenich wrote: > > >>> > > >>>does anybody have experience in using Altium DXP for designing Xilinx > > >> FPGA? > > >>Is it possible to compile Xilinx libraries (unisim/coregenlib/simprim) > > >>for > > >>using them in DXP? > > >>>DXP is not supported by Xilinx, what are the risks in using it? > > >> > > > > > > I evaluated DXP but unfortunately it expired before I got to the > FPGA/VHDL > > > part, from > > > what I hear from others it is a decent tool, again , I don't have > specifics. > > > > > > > > >>You should ask this question on the altium forums, > > >>available at the altium website. > > > > > > > > > I think this si a valid question in this newsgroup, instead of lecturing > > > people > > > maybe you should try to help them! It would fit more with the spirit of > this > > > newsgroup! > > > > Sorry about that. > > Well, I didn't come this far with DXP yet. > > Obviously this poster was not aware of the Altium groups. > > They are a definite must for every DXP user anyway. > > Perhaps a more knowledgeable DXP user knows an answer here. > > > > Rene > > -- > > Ing.Buero R.Tschaggelar - http://www.ibrtses.com > > & commercial newsgroups - http://www.talkto.net > > > > >Article: 62160
Sorry for my carelessness--the device is xc2vp40-6-1152,and the two LUTs share the same reset signal. Let me introduce my design clearly: The function is a multiplier of 15*3,both multiplicators are 2's complement, say a[14:0] and b[2:0];b can be 0,+1,+2,-1 or -2(for ethernet,4D/PAM5).So the function is actually a mux,the output o[n] needs 5 inputs:a[n],a[n-1] and b[2:0].So I think use a 4-input(a[n],a[n-1],b[1:0]--change encoding) LUT and a D-latch(reset active when b is 3'h0) may save area in FPGA design.Are there some other good methods? In fact I do use FPGA Editor to generate a macro(since "clever" method did not work),but it brings out other questions -_-! First I generate a macro with only one LUT,but placer failed with a warning like "can not place function",I think maybe ISE considers the macro as a whole slice which contains only one LUT,so the design is too large to put in the device(remember there is 5k such functions here).But why the warning message appears at place stage and not map stage?And I think this problem is something like the RPM,right?But I could not find the reason why it is like this and how to avoid. Secondly I generate another macro fully using the whole slice(but my design uses only 3 of the 4--an eclectic solution).This time the warnings dissapear but it takes a very long time and routing process seems never convergent,so I stop it. Do you have any suggestion?Thanks a lot! Best Regards, Ric Ma ASIC Department @Attansic Inc.Article: 62161
In laboratory I have few boards with Altera Flex600. Boards are connected with PC using ByteBlaster. On PC I have Win98 OS. On the all PC is the same software. Problem is that on some computers after configuring ALTERA device after some time (sometimes very short) project in Altera is deleteted. How to solve that problems without disconnecting ByteBlaster after programming? Jaroslaw GuzinskiArticle: 62162
Hi, I currently trying to get Quartus running on Mandrake 9.2 and needless to say: it fails. Installation was no problem but I can't get it running. It just gives me the message "Abort" and that's it. Not even a core dump. I've ran quartus with GDB and then it gives a segmentation fault in libkernel32.so Output from GDB: Starting program: /usr/local/quartus/linux/quartus (no debugging symbols found)...(no debugging symbols found)... (no debugging symbols found)...(no debugging symbols found)... (no debugging symbols found)...(no debugging symbols found)... (no debugging symbols found)...[New Thread 16384 (LWP 28457)] [New Thread 32769 (LWP 28496)] [New Thread 16386 (LWP 28497)] [New Thread 32771 (LWP 28498)] [New Thread 49156 (LWP 28499)] [New Thread 65541 (LWP 28500)] [New Thread 81926 (LWP 28501)] Program received signal SIGSEGV, Segmentation fault. [Switching to Thread 16384 (LWP 28457)] 0x41af5a05 in string_hash () from /usr/local/quartus/mw/lib-linux_optimized/libkernel32.so I've also tried the old 'compatible' glibc library (compat-glibc-6.2-2.1.3.2.src.rpm) but that isn't working either. Currently downloading the service pack but that will take a long time... Anyone any idea's? kind regards, Jan linux user wrote: > October 18, 2003 > The procedure is posted at: > <http://linuxan.tripod.com> > If you experience any problem, (I may I missed something) post a message here.Article: 62163
Hi,
Right, solved it.
I needed to hack a script because I got a error on an if expression.
In qenv.csh (in $QUARTUS_ROOT/adm) I needed to change the following:
if (-f /etc/issue) then
set redhat_ver=`cat /etc/issue | grep release | sed -e 's/Red Hat Linux release
//g' -e 's/(.*//g'`
if ($redhat_ver != "7.1") then
...
Here was the problem: redhar_ver got the value "Mandrake Linux release 9.1" and
therefor there was this wrong if expression. I've removed the whole "if (-f
/etc/issue)" then construct and replaced it by "setenv MWMM allwm".
And now it works... Maybe Altera should write a cleaner script that first checks
if it's a Red Hat distribution...
kind regards,
Jan
Jan De Ceuster wrote:
> Hi,
>
> I currently trying to get Quartus running on Mandrake 9.2 and needless
> to say: it fails. Installation was no problem but I can't get it
> running. It just gives me the message "Abort" and that's it. Not even a
> core dump. I've ran quartus with GDB and then it gives a segmentation
> fault in libkernel32.so
>
> Output from GDB:
> Starting program: /usr/local/quartus/linux/quartus
> (no debugging symbols found)...(no debugging symbols found)...
> (no debugging symbols found)...(no debugging symbols found)...
> (no debugging symbols found)...(no debugging symbols found)...
> (no debugging symbols found)...[New Thread 16384 (LWP 28457)]
> [New Thread 32769 (LWP 28496)]
> [New Thread 16386 (LWP 28497)]
> [New Thread 32771 (LWP 28498)]
> [New Thread 49156 (LWP 28499)]
> [New Thread 65541 (LWP 28500)]
> [New Thread 81926 (LWP 28501)]
>
> Program received signal SIGSEGV, Segmentation fault.
> [Switching to Thread 16384 (LWP 28457)]
> 0x41af5a05 in string_hash () from
> /usr/local/quartus/mw/lib-linux_optimized/libkernel32.so
>
>
> I've also tried the old 'compatible' glibc library
> (compat-glibc-6.2-2.1.3.2.src.rpm) but that isn't working either.
>
> Currently downloading the service pack but that will take a long time...
>
> Anyone any idea's?
>
> kind regards,
> Jan
>
>
>
> linux user wrote:
>
>> October 18, 2003
>> The procedure is posted at:
>> <http://linuxan.tripod.com>
>> If you experience any problem, (I may I missed something) post a
>> message here.
>
>
Article: 62164Xilinx guys : wouldn't it be cool to integrate such a resynchronizer circuit in each IOB ?Article: 62165
all you need to do is add the static keyword to the ram declaration
A
gerardo_sr@yahoo.com (Gerardo Sosa) wrote in message news:<f4ee0441.0310161428.71d317a0@posting.google.com>...
> Thanks Steve, but I don't think that this be the error, because the
> error put the cursor in the line:
> ram unsigned 8 RAM1[4] = {0,1,2,3} with {block="BlockRAM"};
>
>
> Anyway I probed:
>
> unsigned i=0;
>
> and
>
> unsigned i;
> i=0;
>
> But, both either don't work.
>
> Regards
>
> Gerardo
Article: 62166Guy Eschemann wrote: > Xilinx guys : wouldn't it be cool to integrate such a resynchronizer > circuit in each IOB ? Yea. It's called a flipflop. There is already one there. -- Phil HaysArticle: 62167
Hi Dieter- I use DXP for PCB work and like it very much. I like the way it organizes projects and find it interesting that it can handle FPGAs, but don't see that as very practical since the two that it supports (Xilinx and Altera) both offer synthesis tools with their free toolsets. I can't say which is a better synthesizer, but I'd expect the FPGA manufacturers would have the upper hand on that. You can, however, draw schematics with Protel and compile them. This would be a much better solution if you wanted to go the schematic route. (since the schematic capture program (ECS) included with Xilinx tools is about as convenient to work with as little pieces of paper cutout like the symbols and using twigs to make connectivity) You can use the standard symbols with DXP, and I would expect something to deal with Cores, but haven't delved into it much. Hope this helps at least a little. Jake "Dieter Keldenich" <dieterkeldenich@epost.de> wrote in message news:<3f91919a$0$19083$9b4e6d93@newsread2.arcor-online.net>... > Hi, > > does anybody have experience in using Altium DXP for designing Xilinx FPGA? > Is it possible to compile Xilinx libraries (unisim/coregenlib/simprim) for > using them in DXP? > DXP is not supported by Xilinx, what are the risks in using it? > > kind regards > Dieter KeldenichArticle: 62168
> >I don't think it matters. He just saying that FPGAs provide such an > >abundance of functional units that memory performance (however you > >call it -- the ability for a given system to provide data to the > >function units) is limiting. He's got a 10,000 pound gorilla and he's > >trying to feed it bananas with a teaspoon. > > It matters ALOT. Latency and large memory, you're fucked. > Overlapping latency is not so bad. Streaming access from multiple > banks? If it's predictible enough, you can be running those pins at > 266 MHz DDR at full rate all the time. Hmm. Best case comparisons. Let's see: For an XC2P125 thats about 1200 I/O streaming 533 Mbps each resulting in a total of 640 Gbps of data assuming that you need no address lines or address cycles. Internally you have 556 BRAMs with 72 Databits each running at 266MHz thats almost 11 Tgps, random access, 10008 address lines provided additionally. That's an order of magnitude better internal bandwidth PLUS random access. I agree with the original poster that it is difficult to find real world applications that can use the potential computational power of an fpga. Would be nice if there where only Smith-Waterman like algorithms out there. For reconfigurable computing an order of magnitude larger internal memory would help alot and would not cos that much more. (Think HSRA) But I do not think that RC people are the customers that the current FPGAs are optimized for. Kolja SulimmaArticle: 62169
Rick, I'd certainly be interested in more info on the fiber microscope you mentioned. Debugging designs with lots of big BGAs is tough enough without wondering whether it's an assembly issue or not, and traditional xray techniques are good for showing shorts, but no so good for opens ... ----- Ron Huizen BittWare "rickman" <spamgoeshere4@yahoo.com> wrote in message news:3F93E3DC.6753DCD4@yahoo.com... > Thomas Stanka wrote: > > > > Xpost 2 cae and caf, no Fup. > > > > Hallo, > > > > "Geoffrey Mortimer" <me@privacy.net> wrote: > > > Anyone have any experience of BGA's (especially fine pitch types) in high > > > vibration environments? Is there a more appropriate newsgroup for this > > > topic? > > > > Actually that's a very hot topic as BGA seems to get usual in the > > world of FPGAs and ASICs. I know that our mechanical engineers > > allready research on this topic, as we are very likely to have some > > fine pitch BGA in a high vibration environment in future. > > I would guess, that you should ask in some mechanical newsgroups as > > well. > > A big problem using FBGA is the test, wether you connected all balls > > proberly [1], as you have no chance of easy visual inspection. > > > > bye Thomas > > I recently saw a product that allows visual inspection of the solder > balls on a mounted BGA. It is a fiber optic microscope and has tiny > fiber probes that can run between the balls. I'll look for the info if > anyone is interested. > > -- > > Rick "rickman" Collins > > rick.collins@XYarius.com > Ignore the reply address. To email me use the above address with the XY > removed. > > Arius - A Signal Processing Solutions Company > Specializing in DSP and FPGA design URL http://www.arius.com > 4 King Ave 301-682-7772 Voice > Frederick, MD 21701-3110 301-682-7666 FAXArticle: 62170
Am I correct in thinking that a design lab that was simuated and implemented onto a demo board with Xilinx Foundation 3.1, can have its bitstream used with another version such as Xilinx Foundation 4.2i? Using the same demo board (with same Spartan FPGA XCS10 on digilab board XLA5) that was used for initial design with Foundation 3.1 - I want to demonstrate this design again on the same board, this time using Foundation 4.2i... I am assuming I can just copy the dot bit file from my initital implementation, and paste it in the later 4.2i version of Foundation and send it straight down to the board again without having do any importations of schematics or code from the earlier version. Any advice on this issue would be most welcome.. Thanks ZArticle: 62171
Hi, I don't know whether it is possible to get this kind of information. I would like to know what is the structure of the 18x18 embedded multiplier block in Virtex II Pro more like.... Is it more like a ripple-carry structure or carry-save multiplier structure or others ? thanks a millionArticle: 62172
In article <b890a7a.0310210440.ae989cf@posting.google.com>, Kolja Sulimma <news@sulimma.de> wrote: >For reconfigurable computing an order of magnitude larger internal >memory would help alot and would not cos that much more. (Think HSRA) >But I do not think that RC people are the customers that the current >FPGAs are optimized for. Actually, mixed Dram/Logic (what gets your the ~10x greater memory density for the HSRA) has effectively failed. It required too much process fiddling, which nobody wants to do these days. Also, then you have the joy of the DRAM page access time anyway, so you save on the pin crossings, but the rest of the latency is still there, and still measured in several clock cycles. As for the streaming access example, its still an order of magnitude greater than a CPUs, where you only have 128 pins at 533 Mbps/pin. But if it is random access from a single block (e.g. pointer chasing), why not jsut get an Athlon 64 and write it in software? -- Nicholas C. Weaver nweaver@cs.berkeley.eduArticle: 62173
Hi, My apologies if this is not the most appropriate group for this query. I am starting to have great difficulty sourcing some 74 logic parts from my design in SMD (at least in small volumes). As I now have the chance to make a new PCB revision I am wondeing if I couldn't do away with the logic all together and use a PLD (CPLD). So for those who know the learning curve well, I have never used PLD's before, but have used PIC's (asm) and was wondering if it is realistic for me to grasp enough of PLD design (not necessarily VHDL) to implement some simple logic functions within a month or so? Or is this likely to take far longer? I was playing with the Altera Quartus II software and it seems that by using existing blocks this could be fairly straight forward. What do you think and what would be a good entry level device? Any comments would be greatly appreciated.!Article: 62174
QII and the Altera MAX parts are a quick learn , if you are a 74 designer you should be implementing lots of stuff in a month. Various varieties of the MAX parts are 3V and 5V .. etc. I may suggest that for $99 arrow sells an Altera MAX development board , includes QII and board with a max part with buttons and lights and osc, very easy to learn how to implement lots of neato logic things and then quickly try them on a real board. On 21 Oct 2003 07:23:25 -0700, jiz_king@hotmail.com (Carl) wrote: >Hi, > >My apologies if this is not the most appropriate group for this query. > >I am starting to have great difficulty sourcing some 74 logic parts >from my design in SMD (at least in small volumes). As I now have the >chance to make a new PCB revision I am wondeing if I couldn't do away >with the logic all together and use a PLD (CPLD). > >So for those who know the learning curve well, > >I have never used PLD's before, but have used PIC's (asm) and was >wondering if it is realistic for me to grasp enough of PLD design (not >necessarily VHDL) to implement some simple logic functions within a >month or so? > >Or is this likely to take far longer? > >I was playing with the Altera Quartus II software and it seems that by >using existing blocks this could be fairly straight forward. > >What do you think and what would be a good entry level device? > >Any comments would be greatly appreciated.!
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