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Dieter Keldenich wrote: >Hi, > >does anybody have experience in using Altium DXP for designing Xilinx FPGA? >Is it possible to compile Xilinx libraries (unisim/coregenlib/simprim) for >using them in DXP? >DXP is not supported by Xilinx, what are the risks in using it? > > I have not upgraded to DXP, but use the previous software, Protel 99SE. It was supposed to have Xilinx support, but I found a raft of stuff that didn't work. The schematic part of the Xilinx ISE tools drives me crazy, however, and so I have been experimenting with linking Protel99 to ISE, and finally got it to work. Protel's EDIF format is totally fouled up, and their XNF output is close, but has some subtle bugs that I was never able to figure out. But, the undocumented VHDL output is almost perfect. To use the Xilinx schematic library parts, you have to manually add a library declaration and a use statement for that library to the VHDL file. That looks like : library unisim; use unisim.vcomponents.all; The only other quirk is that Protel repeats the "component" declaration of a schematic sheet that is used more than once in the same schematic. I can now edit in these small changes in a few seconds. If you want to do Xilinx FPGAs in Verilog or VHDL, just forget Protel, the Xilinx tools are going to be much more current, and I'd trust their optimization a lot more than anyone else's. Note that Xilinx's own software dropped all support for all 5 V chips about 3 years ago! That's why I'm still using ISE 4.1i, because all my work is with 5 V chips at the moment. JonArticle: 62201
>>And now it works... Maybe Altera should write a cleaner script that >>first checks if it's a Red Hat distribution... > > > Yes. But it would have been even better if they checked for the > *features* they need rather than checking the distribution. Indeed and I even had to manualy add some directories to the librarypath to get everything up and running. It just doesn't look profecional to me. 2 days work (at most) for a decent engineer and the scripts would have been perfect. I'm a bit dissapointed... kind regards, JanArticle: 62202
Thank you everyone for your advice, I think I have been inspired sufficiently to get a dev kit to play with. This is a very mature product that still works really well; judging from your responses however, I feel it would be an important step for me to be able to ditch thinking in 74 numbers and it's something I really should have done before (Plus a big wad a brownie points never hurts). One more quick question though.. My design also has the following elements, which of these couldn't get squeezed into a CPLD? 4046 PLL's (Phase comparator 2) various Comparators Thanks again everyone. Carl.Article: 62203
> Hello Antti, > Thanks for answering to my queries. I wonder if you could help me with > this. Here is my problems. > > The C-code, I got, is written for parallel interfacing with ISP1581. I > wonder, if I have to modify my code to use it as GPIO pins in > Microblaze. I still haven't got clear understanding of configuring > Microblaze. I have been using EDK 3.2 and ISE 5.2. And I also need to > setup temporary SRAM and its controller on FPGA so that the data > communication could be established between PC and SRAM through USB. If > you have any suggestion or experience relating this, please pass it on. as quick start you can connect ISP1581 to GPIO pins and emulated a the data control address bus. you just have to write some c routines that access the isp1581 registers, by toggling gpio pins) thats easisest for start and quick test. for real application it would be preferred to write a xilin PLB IP core that talks to isp1581, but software wise it want change anything. You may leave it for later as it usually isnt without problems :( custome PLB peripherals often dont work at the beginning... same with shared RAM or whatever you decide to use, two options you create a peripheral core, or you use ISE as toplevel, this is also not without caveats, works but only if you do many many step in row and all precise correct. then you can write portion of the design in verilog/vhdl and use microblaze SOC as schematic component in ISE anttiArticle: 62204
On Tue, 21 Oct 2003, ted wrote: > Jaroslaw Guzinski <jarguz@sunrise.pg.gda.pl> wrote in message news:<Pine.GSO.4.58.0310210953060.27819@sunrise.pg.gda.pl>... > > In laboratory I have few boards with Altera Flex600. Boards are connected > > with PC using ByteBlaster. On PC I have Win98 OS. On the all PC is the > > same software. > > Problem is that on some computers after configuring ALTERA device after > > some time (sometimes very short) project in Altera is deleteted. > > How to solve that problems without disconnecting ByteBlaster after > > programming? > > > > > We had a similar problem some time ago. We suspected the PC pokes the > printer port every so often (something to do with polling > peripherals??), causing the nStatus line to reset. > > We much reduced the problem by removing the LPT1 entry in the PCs > device list, so that the PC doesn't know there is a printer port. YOu > could also try adding a toggle switch on the nStatus line betweeh the > ByteBlaster and the target. > Thanks, I will try to remove LPT port from device list. In our Byte Blaster I have that switch but it is a little "unelegant" solution. Jaroslaw GuzinskiArticle: 62205
Hello all, I'm thinking about a project to reimplement old processor designs (Symbolics Lisp-machines or a Control-Data cyber 17x, 18x in a chip) using modern programmable hardware, e.g. FPGA's. The complete hardware documentation for these platform is available. My knowledge in this task in not up-to-date, as I've not been working on hardware design for almost ten years (onyl software!). I would like to get some suggestions about a FPGA Development environment and programming system to use for this task. Any other suggestions or links to similar projects are very welcome. If there are other people interested in such kind of project, please contact me directly. This is not a commercial project! AndreasArticle: 62206
I'm using block rams to create FIFOs in Virtex II device.And mapper
report problem with using clock, that drives these block rams:
WARNING:LIT:175 - Clock buffer is designated to drive clock loads. BUFGMUX
symbol "clock_reset_clk80_bufg" (output signal=clk) has a mix of
clock and
non-clock loads. Some of the non-clock loads are (maximum of 5 listed):
Pin CLKA of txfifo1_bram3
Pin CLKB of txfifo1_bram3
Pin CLKA of txfifo1_bram2
Pin CLKB of txfifo1_bram2
Pin CLKA of txfifo1_bram1
I'm a little suprised, because I thought that these ARE clock loads.
Should I worry about that?
Any other comments?
--
Robert Pudlik
Article: 62207I forgot: I'm using ISE5.2 with the latest service pack, and XST for synthesis. RobertP wrote: > I'm using block rams to create FIFOs in Virtex II device.And mapper > report problem with using clock, that drives these block rams: > > > WARNING:LIT:175 - Clock buffer is designated to drive clock loads. BUFGMUX > symbol "clock_reset_clk80_bufg" (output signal=clk) has a mix of > clock and > non-clock loads. Some of the non-clock loads are (maximum of 5 listed): > Pin CLKA of txfifo1_bram3 > Pin CLKB of txfifo1_bram3 > Pin CLKA of txfifo1_bram2 > Pin CLKB of txfifo1_bram2 > Pin CLKA of txfifo1_bram1 > > > > I'm a little suprised, because I thought that these ARE clock loads. > Should I worry about that? > Any other comments? > > -- > Robert Pudlik >Article: 62208
Hi: I'm working on partial reconfiguration of VII devices, and until now I haven't found information about the internal configuration addressing of VII and the respective formulas to calculate MJA and MNA. I guess they are similar to the ones for VirtexE (as both have BRAMs interspersed between CLBs). Its urgent!!!! PLS P.S I have already read app 151, app290, VII user guide, etc YanaArticle: 62209
"Subroto Datta" <sdatta@altera.com> wrote in message news:yEllb.6749$aZ.1431@newssvr17.news.prodigy.com... > This looks like a bug. Panic, please email me the qar file for your project, > and I will take a look. In the meantime try replacing the lpm_ff with a dff > primitive and see if it makes a difference. I tried to use dff primitives for all the three std_8bit_dffs (lpm_dff) that fed the troublesome net in question, but that didn't change anything. I also tried to remove all the lmf_dffs and the net stubs closest to them, and insert new ones, but that didn't help either. (Not that I tought it would...but you never know...) What's so strange is that I have another design that is more or less equal to this, only without the four 8 bit key inputs and four 8 bit xors, but the section of the design that causes me trouble is totally alike between the two designs!Article: 62210
> Sounds like you shorted several outputs together. Yes, somehow I must have done that. Or...Quartus did anyway. > Given the error messages, you should check if your instantiations of > std_8bit_dff0:inst8|lpm_ff:lpm_ff_component|dffs[6] etc. are correct. How can I check this? (Have you looked at the image I posted in my OP?) > It looks like you assigned several of them the same output node. But how? Not physically. That clearly shows on the image.Article: 62211
Hi there, I would like advice on VDHL source code beautifiers. Cheers, Jon.Article: 62212
Hi, I would like to simulate a NIOS system with modelsim but I have very strange results : it seems that the external SRAM (for the Nios Apex dev board) is incorectly adressed by the NIOS processor. I'm using quartus 2.2 and sopc builder 2.8 (NIOS 3.0) Here is what I'm doing : - the system is minimal (a 32 bit nios, an UART, an on chip memory, the external SRAM and two user interfaces). - To simulate my program, I'm generating the SRAM_lanexx.dat files from the srec file obtained after compilation. - The on chip memory contains a GERM monitor - The uart is configured to simulate a G0000 RX. This allows to branch directly to my program. - the SRAM is configured as a 32bit data width What I observe : the GERM runs correctly and the G0000 is correctly received. At the moment the processor fetch the adress 0 (observed with the i_adress port of the nios) everything is wrong. Adresses (i_adress) are going odd : 0000,0002,0004,0006 , etc ... but the wrong instructions are fetched. Indeed, instructions are 16 bit wide (2 bytes) but the memory is 32 bits and it seems that the avalon-tristate bridge is unable to correctly adress the memory. The i_adress is directly transmitted to the SRAM and the wrong bytes are selected. So when fetching adress 0002, it gets the 16 upper bits of the third word (SRAM_adress=0002) instead of the 16 upper bits of the first word (SRAM_adress 0000). The signal byte_en to the SRAM are also always to 0.... So, why does it work like that ? It wasn't the case with previous sopc_builder. What do I have to change ? - the way the SRAM is interfaced with the system ? - the way the program is stored on memory (but I will loose space ..) - use a 16 bit wide SRAM ? (but I would like to keep 32 bits to keep my design bandwidth ...) - regenerate a new project ? Did I missed something with this sopc_builder version? Is it a sopc_builder bug ? Thanks a lot for you help. StephaneArticle: 62213
www.hightech-td.comArticle: 62214
On 22 Oct 2003 01:02:24 -0700, jiz_king@hotmail.com (Carl) wrote: >Thank you everyone for your advice, > >I think I have been inspired sufficiently to get a dev kit to play >with. This is a very mature product that still works really well; >judging from your responses however, I feel it would be an important >step for me to be able to ditch thinking in 74 numbers and it's >something I really should have done before (Plus a big wad a brownie >points never hurts). > >One more quick question though.. > >My design also has the following elements, which of these couldn't get >squeezed into a CPLD? >4046 PLL's (Phase comparator 2) In theory, you can do this in a CPLD. In practice, the performance may be poor with respect to the original. Note that the 4046 PC2 isn't a particularly good phase comparator to start with (with respect to better designs such as the 74HC9046). The '9046 has a current source & sink output that cannot be done (directly) in a CPLD. The '4046 has a tristate output that's just like a regular tristate output on a CPLD. >various Comparators Maybe, maybe not. Some CPLDs have schmitt trigger inputs. Some FPGAs have differential inputs (e.g. LVDS) that behave like a comparator. Don't expect any CPLD or FPGA to give you low noise, precision thresholds like a comparator though. Regards, Allan.Article: 62215
Andreas Holz wrote: > > Hello all, > > I'm thinking about a project to reimplement old processor designs > (Symbolics Lisp-machines or a Control-Data cyber 17x, 18x in a chip) > using modern programmable hardware, e.g. FPGA's. > > The complete hardware documentation for these platform is available. > > My knowledge in this task in not up-to-date, as I've not been working > on hardware design for almost ten years (onyl software!). > > I would like to get some suggestions about a FPGA Development > environment and programming system to use for this task. Any other > suggestions or links to similar projects are very welcome. > > If there are other people interested in such kind of project, please > contact me directly. > > This is not a commercial project! > > Andreas This would be an interesting project and might even make a good project for an advanced class in processor design. If I am not mistaken, there is a web site or sites where others are working on similar projects. I have seen projects on PDP-xx machines as well as others. Certainly this is not a difficult task. I would recommend that you find a board using a Xilinx FPGA since they provide more complete design tools for free. The current Altera tools do not include an HDL simulator. I am assumming of course that you intend to use an HDL, and I also recommend it. Here is a list of some FPGA board vendors... http://www.fpga-faq.com/FPGA_Boards.shtml Do a Google search on this and find some of the individuals doing similar projects. I am sure they can give you some good advice. -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAXArticle: 62216
HI , I am trying to use system ACE controller + flash card, to boot my PPC embedded in Virtex 2pro. After initial boot, the PPC will make a choice on downloading one of many .ace files. I would like to know is this possible using system ACE CF controller. I read the data sheet, they mentioned abt MPU to CF interface. I am looking for specific details/applicatin notes, on how to boot ppc from System ACE I have V2pro xc2vp4 ff672 MEMEC board, and System ACE cf controller with 128MB flash card. I would appreciate any assistance Thank you RAmArticle: 62217
Look in the handbook. This has more infocompared to the datasheet. "Peng Cong" <pc_dragon@sohu.com> wrote in message news:bmvf0o$1o5b$1@mail.cn99.com... > Are you sure? I look into the datasheet of Multiplier Generator V6.0, > did not see anything about submodules > > "Anil Khanna" <anil_khanna@mentor.com> 写入消息新闻 > :3f923e9f$1@solnews.wv.mentorg.com... > > Thanks for the reply. > > > > However, I am not using the Xilinx Coregen! > > Anyways, I figured out the answer to this question and now I have another > Q. > > > > The handbook claims that there are certain submodules (of the MULT18X18S) > > available for use. These are submodules like MULT4X4 etc. How does one get > > access to this and what is the primitive name? > > > > Anil > > > > > > "Peng Cong" <pc_dragon@sohu.com> wrote in message > > news:bmqfru$j8h$1@news.yaako.com... > > > If you use Xilinx IP Core > > > A - 6 bit B - 6 bit B- 12 bit > > > is enough > > > > > > "Anil Khanna" <anil_khanna@mentor.com> 写入消息新闻 > > > :3f906a1c$1@solnews.wv.mentorg.com... > > > > I am trying to construct a 6x6 signed multiplier using the Virtex II > > block > > > > multipliers. I know that the V-II multipliers are inherently a 2's > > > > complement signed multiplier. However, my question is - by how much > > should > > > I > > > > sign-extend the inputs? > > > > > > > > Example: > > > > Input A - 6 bit > > > > Input B - 6 bit > > > > Output B- 12 bit > > > > > > > > Should I connect the remaining ports of the multiplier input (A(7:18)) > > to > > > > A(6) or just A(7:12) to A(6)? The handbook suggests that the > > > sign-extension > > > > of the inputs is done till the width of the output. Is this enough or > > > should > > > > I do it till the physical width of the multiplier? > > > > > > > > Thanks > > > > > > > > Anil > > > > > > > > > > > > > > > > > > > >Article: 62218
The topic of where to pick up the Red Hat Release was pointed to by another user who tried Quartus 3.0 with a non Red Hat version of Linux. This has been fixed for Quartus II 4.0. - Subroto Datta Altera Corp. "Jan De Ceuster" <jandc@elis.ugent.be> wrote in message news:bn59aj$tqj$1@gaudi2.UGent.be... > >>And now it works... Maybe Altera should write a cleaner script that > >>first checks if it's a Red Hat distribution... > > > > > > Yes. But it would have been even better if they checked for the > > *features* they need rather than checking the distribution. > > Indeed and I even had to manualy add some directories to the librarypath to get > everything up and running. It just doesn't look profecional to me. 2 days work > (at most) for a decent engineer and the scripts would have been perfect. I'm a > bit dissapointed... > > kind regards, > Jan >Article: 62219
Hi, Whats the difference between IPs OPB_sdram/PLb_sdram and OPB_EMC/PLB_EMC. When I will make a choice between EMC/SDRAM. If i have a onboard SRAM, can i still choose a EMC core. I would appreciate your time and effort you spend to answer. Thankyou RAmArticle: 62220
I would like to use Amplify v3.2 under Windows server 2003 with or without program compatibility mode. Amplify starts well but cannot reach the license feature. (I used floating license definition with the SYNPLICITY_LICENSE_FILE variable). The same program works well under windows 2000 or XP. PS : Synplicity v7.3.3 is full ok under windows server 2003 with the same license definition. Thanks for your help Patrick PangaudArticle: 62221
And I get the same warning for clocked multiplier blocks. I suspect the mapper is goofy. Barry Brown "RobertP" <rpudlik@poczta.onet.pl> wrote in message news:bn5l71$d8e$2@news.onet.pl... > I forgot: I'm using ISE5.2 with the latest service pack, and XST for > synthesis. > > > RobertP wrote: > > > I'm using block rams to create FIFOs in Virtex II device.And mapper > > report problem with using clock, that drives these block rams: > > > > > > WARNING:LIT:175 - Clock buffer is designated to drive clock loads. BUFGMUX > > symbol "clock_reset_clk80_bufg" (output signal=clk) has a mix of > > clock and > > non-clock loads. Some of the non-clock loads are (maximum of 5 listed): > > Pin CLKA of txfifo1_bram3 > > Pin CLKB of txfifo1_bram3 > > Pin CLKA of txfifo1_bram2 > > Pin CLKB of txfifo1_bram2 > > Pin CLKA of txfifo1_bram1 > > > > > > > > I'm a little suprised, because I thought that these ARE clock loads. > > Should I worry about that? > > Any other comments? > > > > -- > > Robert Pudlik > > >Article: 62222
Jon Masters <jonathan@jonmasters.org> wrote in message news:vpcpif664t54d5@corp.supernews.com... > Hi there, > > I would like advice on VDHL source code beautifiers. They're a pain in the arse :-) In a previous contract I was working in a multi engineer team, any one of who could be asked to fix problems in any source file. One guy would automatically run the emacs beautifier on any source code as soon as he'd checked it out, work on it then check it back in. (Only 1/3 of the team used emacs). To anyone consequently doing a diff on his version and the previous one it looked like the whole design had changed instead of the line or two he'd altered. If the diff tool had been configurable to ignore whitespace this might have been a bit better, but there would probably have been other changes to cloud the issues. While I'm on this subject, someone else used to move big chunks of code about to where he thought they should go, even when doing minor changes to the source. This had the same affect as above when later doing a diff. I'd say 1) Learn to write clear, structured commented code. Look at as many different peoples as you can and copy the one that looks right to you. If you've a sytle guide stick to it. 2) If you're editing someone else's source code stick to their style while you're doing it, especially for small changes (as recommended by Jack Ganssle, http://www.ganssle.com/ although don't ask me exactly where). Nial Stewart ------------------------------------------------ Nial Stewart Developments Ltd FPGA and High Speed Digital Design www.nialstewartdevelopments.co.ukArticle: 62223
I always get an error window with 'File :Not Exist' when I try to load a source file. Nial.Article: 62224
Hello, In which reports of time can I see the maximum frequency or haw can I to calculate it?. I am working with ISE 5.1i and for the synthesis I use xst. Thanks, Falc髇.
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Compare FPGA features and resources
Threads starting:
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