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Nah, Lawyers are still top of the list in my book.
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 61326
I have seen very few instances where the synthesized logic did not
behave as coded. The logic turned out is nearly always 100% logically
correct, however it may not be the most efficient way of implementing
that function. Frequently with LUTs, the synthesizer will do weird
things like optimizing out unused inputs on some bits, combining
sub-terms etc. These are valid optimizations, but can make a bus wide
LUT a mess.
Tullio Grassi wrote:
> On 18 Sep 2003, Bob wrote:
>
> > Hello Jake/Ray
> >
> > I appreciate two esteemed people like yourselves offering me your
> > advice.
> >
> > I would rather infer than instantiate (if that doesn't sound too
> > rude).
> [cut]
>
> I suspect that inferring vendor-specific embedded primitives
> (like LUTs, RAM, etc) is one of the few situations where
> logic simulation is not reliable, as the implementation
> depends a lot on the translator.
> At least I had problems with xilinx BRAM that I could
> explain only in this way.
> Try at least one post-PAR simulation to see if the
> LUT behaves as you expect in all operating modes.
>
> Tullio
> Univ. of Maryland
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 61327I'm growing increasingly weary of my current editor lot and am in the market for a new one. What I'd like is something akin to the Visual Studio editor. You know, syntax highlighting (easy) as well as on-line lookup for functions/instances, project management, etc. It would be especially nice if the editor would integrate with the FPGA primitive libraries so I can get parameters and usage information just like in Visual Studio. Visual Slick Edit seems somewhat close, but is pretty rough around the edges for its price tag. Anyone? JakeArticle: 61328
"Ulf Samuelsson" <ulf@atmel.nospam.com> wrote in message news:A2Jeb.8119$P51.16835@amstwist00... > > "SneakerNet" <nospam@nospam.org> skrev i meddelandet > news:cFpeb.164194$JA5.4050546@news.xtra.co.nz... > > Hi Again Colin > > Don't worry about the crack, I found it. > > Did u have this problem, > > WinDriver finds the device, and I assign the Vendor ID and the Product ID > > and windriver generates a inf file, and then tries to install the driver. > > However at this stage, win2k takes over and reports that > > c:\winnt\inf\usb.inf is a closer match and windows ends up using that > driver > > instead of my custom generated driver and I can't do anything about it. > > > > Cheers. > > > Maybe remove usb.inf temporarily from the inf directory, install, and then > move usb.inf back.... > That is what I have done in similar situations. > Maybe you indicate that it is a HID device with your Product Id.... > > -- > Best Regards, > Ulf Samuelsson ulf@a-t-m-e-l.com > This is a personal view which may or may not be > share by my Employer Atmel Nordic AB > > Hi Ulf haha I did that.. but windows still found it LOL.. i even renamed it to _usb.inf_ and it still found it.. LOLArticle: 61329
+ You may not want (or need) an 18-bit multiplier + The design may have exceeded the built-in mults and therefore need other resources. + You may want a pipelined multplier + Placement of a core may be more optimal for a particular design need than the built-in mults Uwe Bonnes <bon@elektron.ikp.physik.tu-darmstadt.de> wrote in message news:<bles4l$q75$1@news.tu-darmstadt.de>... > Kiran <kirandev@msn.com> wrote: > : Hi All, > > : My design has many multipliers of different input/output widths. I > : need to implement it on Xilinx Virtex II XC2V6000 FPGA. I tried using > : CoreGen to generate the multipliers but looks like for each set of > : input/output widths I need to generate a separate multiplier. This is > : very difficult to manage. Is there any way to parameterize the > : CoreGen multiplier so that by using one generic wrapper, the same code > : can be reused for all the multipliers needed in the design? I am > : using Verilog HDL. > > : Sorry if this question has already been asked. I tried searching but > : could not get any answers. > > > Using Ise 5.1 and verilog, > > wire [18:0] a,b; > wire [35:0] c; > > assign c = a*b; > > invoked a multipler. On Spartan 2 it was built from LUTs, and Spartan 3 the > Multiplier blocks were used. > > Why then use coregen? > > ByeArticle: 61330
You may be able to get away with fewer varieties if you instantiate the largest of a particular class of mults, then rely on the map tools to prune out unused logic. I know it's not a very elegant solution, but neither is the core generator (for the reason you indicate). Jake kirandev@msn.com (Kiran) wrote in message news:<9043844f.0310010724.745b61c5@posting.google.com>... > Hi All, > > My design has many multipliers of different input/output widths. I > need to implement it on Xilinx Virtex II XC2V6000 FPGA. I tried using > CoreGen to generate the multipliers but looks like for each set of > input/output widths I need to generate a separate multiplier. This is > very difficult to manage. Is there any way to parameterize the > CoreGen multiplier so that by using one generic wrapper, the same code > can be reused for all the multipliers needed in the design? I am > using Verilog HDL. > > Sorry if this question has already been asked. I tried searching but > could not get any answers. > > Regards, > Kiran.Article: 61331
emacs or xemacs with verilog-mode. It's not exactly what you're looking for, but it has many many great features, including mostly-automatic netlisting of upper levels in your hierarchy. Search for both using yahoo, you'll find them. -Stan "Jake Janovetz" <jakespambox@yahoo.com> wrote in message news:d6ad3144.0310011643.21599fc8@posting.google.com... > I'm growing increasingly weary of my current editor lot and am in the > market for a new one. What I'd like is something akin to the Visual > Studio editor. You know, syntax highlighting (easy) as well as > on-line lookup for functions/instances, project management, etc. > > It would be especially nice if the editor would integrate with the > FPGA primitive libraries so I can get parameters and usage information > just like in Visual Studio. > > Visual Slick Edit seems somewhat close, but is pretty rough around the > edges for its price tag. Anyone? > > JakeArticle: 61332
Starting with Quartus II 2.2 Altera replaced their VHDL and Verilog HDL synthesis front ends with the parsers from Verific www.verific.com , to greatly improve the language coverage and the correctness of the synthesis solution. With each subsequent release several improvements have been made in improving the quality of the synthesis solution in Quartus, including inferencing run times and optimizing the area versus fmax choices. The Quartus synthesis solution is available as part of the free Quartus Web Edition. https://www.altera.com/support/software/download/altera_design/quartus_we/dn l-quartus_we.jsp - Subroto Datta Altera Corp. "John Providenza" <johnp3+nospam@probo.com> wrote in message news:349ef8f4.0310010922.254c437a@posting.google.com... > I'm looking at doing a design with Apex-II parts and will > probably need to use the Verilog synthesizer that comes with > Quartus. My last experience (multiple years ago) was very > unpleasant - lots of synthesis bugs. > > Has this gotten better? > > My experience with XST synthesis recently has been pretty good, > so I'm debating about sticking with Xilinx for this next project > or jumping to Altera since their Apex-II parts seem to fit my > application a bit better. > > Any goog/bad stories? > > Thanks! > > John ProvidenzaArticle: 61333
I love nedit, free too. nedit.org has it Andrew Jake Janovetz wrote: >I'm growing increasingly weary of my current editor lot and am in the >market for a new one. What I'd like is something akin to the Visual >Studio editor. You know, syntax highlighting (easy) as well as >on-line lookup for functions/instances, project management, etc. > >It would be especially nice if the editor would integrate with the >FPGA primitive libraries so I can get parameters and usage information >just like in Visual Studio. > >Visual Slick Edit seems somewhat close, but is pretty rough around the >edges for its price tag. Anyone? > > Jake > >Article: 61334
John, 1- How many 65 bit words per second (ms, ns?) do you have to process? 2- Where do the 65 bits come from? (internal, external) 3- Do they get into the FPGA in parallel or serially? 4- Why are you saying that you need two levels of logic? (trying to control delay with combinatorial logic is not a great idea). 5- Why fight with inference? Instantiate what primitives you need. Two logic levels? Two LUT's to look at two consecutive nibbles. One LUT to AND the output of the above with the next most significant bit (the ninth bit). That's it. Two levels. 24 LUT's. Is that what you wanted? -- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ Martin Euredjian To send private email: 0_0_0_0_@pacbell.net where "0_0_0_0_" = "martineu" "John_H" <johnhandwork@mail.com> wrote in message news:Xwoeb.26$XP3.4711@news-west.eli.net... > Greetings, > > I need to detect runs. I want to look at 65 bits and show when there are 9 > consecutive 1s or 0s from the byte boundaries resulting in 8 values per > clock. This should be comfortably done in two logic levels (I need clean > logic delays). > > The idea is simple but the implementation is tough. I'm working with > Verilog in Synplify, targeting a Xilinx Spartan-3. I have to resort to > design violence to get the results that I believe are "best." > > Any thoughts on how to do this "better?" (the following code likes fixed > fonts) > > - John_H > ===================================== > module testRun ( input clk > , input [64:0] bytePlus1 > , output reg [ 7:0] runByte /* synthesis xc_props = "INIT=R" > */ > ); // INIT included to force register as FD primitive - bleah > > reg [23:0] runBits; // I wanted the syn_keep on this combinatorial "reg" > wire [23:0] runBits_ /* synthesis syn_keep = 1 */ = runBits; // - bleah > reg [ 7:0] runByte_; > integer i,j,k; > > always @(*) > begin > runBits = -24'h1; > runByte_ = -8'h1; > k = 0; // overlapping aaa aaaa > for( i=0; i<64; i=i+j ) // consecutive aaaa > begin // bit regions 876543210 > for( j=0; (i%8+j<8) && (j<3); j=j+1 ) > runBits[k] = runBits[k] & (bytePlus1[i+j]==bytePlus1[i+j+1]); > runByte_[i/8] = runByte_[i/8] & runBits_[k]; > k = k + 1; > end > end > always @(posedge clk) runByte = runByte_; > > endmodule > >Article: 61335
Jake,
I still like Aldec for design entry. Editor is very much studio editor
like, plus you can run sims right there as well as integrate in the rest
of your tool flow. For the price, I think it is a great value.
Jake Janovetz wrote:
> I'm growing increasingly weary of my current editor lot and am in the
> market for a new one. What I'd like is something akin to the Visual
> Studio editor. You know, syntax highlighting (easy) as well as
> on-line lookup for functions/instances, project management, etc.
>
> It would be especially nice if the editor would integrate with the
> FPGA primitive libraries so I can get parameters and usage information
> just like in Visual Studio.
>
> Visual Slick Edit seems somewhat close, but is pretty rough around the
> edges for its price tag. Anyone?
>
> Jake
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 61336
Last time I tried it that way, it wound up with something pretty slow. The
synth doesn't know how to make small tally adders with LUTs.
Ulf Samuelsson wrote:
> > > There is an excellent example of a combinational ones counter in the
> course
> > > notes on our Comprehensive VHDL course ;-) Check out my employers
> website
> > > for more details...
> > >
> > > Our example does use a for loop - I'm not sure why you feel a for-loop
> > > cannot be used for combinational logic, unless you are putting wait
> > > statements inside the for loop, and in that case it probably won't
> > > synthesise (unless you have a behavoral compiler). To work out what a
> loop
> > > will do, simply replicate the contents of the loop once for each
> iteration
> > > of the loop, replacing the loop parameter with a constant. eg
> >
>
> The for loop method generates n-1 adders for n bits.
> Probably quite slow as well.
> The synthesizers might of course be smarter than I think...
>
> --
> Best Regards,
> Ulf Samuelsson ulf@a-t-m-e-l.com
> This is a personal view which may or may not be
> share by my Employer Atmel Nordic AB
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 61337
Top Ten Things I wish I never had needed to learn about LVDS_25_DCI:
1) Parallel DCI input standards in Virtex2 continuously modulate
the input termination offset voltage unless you enable bitgen's
FreezeDCI option
2) With FreezeDCI on, the entire bottom half of 2V40, 2V80, and
any CS144 packages are unavailable for LVDS_25_DCI inputs (this
includes half the global clock inputs to the chip) due to DCI
unavailability in banks having only ALT_VRP/N pins
3) With FreezeDCI on, dual purpose config pins cannot be used as
LVDS_25_DCI inputs
4) 5.2i S/W doesn't catch illegal pin assignments due to #2 and #3
5) With FreezeDCI on, input terminator accuracy for 2R values
degrades to +/-20%
6) With FreezeDCI on, each bank will have a (different) random
input offset voltage due to split terminator 2R variations
7) LVDS_25_DCI terminator overhead power per input pair far exceeds
the theoretical 62.5 mW number published in Answer Record 15633
8) With FreezeDCI on, worst case VCCO power overhead per
LVDS_25_DCI input pair approaches 100 mW
9) With FreezeDCI on, worst case DCI VRP/N VCCO power overhead
per I/O bank approaches 200 mW
10) 5.2i Xpower incorrectly assigns DCI power to the 1.5V VCCINT
supply, and it doesn't use the worst case DCI power numbers
11) V2 Power Estimator spreadsheet doesn't support LVDS_25_DCI,
but if you fake it by using two single ended DCI 2R split
terminated inputs per actual LVDS pair, it also uses the
wildly optimistic power numbers
12) LVDS_25_DCI IBIS models don't work in HyperLynx
13) Massive 8pf IBIS C_COMP input capacitance value for the
V2 LVDS inputs requires external back termination and/or
input matching scheme to achieve reasonable signaling when
driving FPGA inputs from a modern high speed LVDS driver
Interesting Answer Database Search Keywords:
FreezeDCI
LVDS AND DCI AND termination
DCI AND power
IBIS AND Hyperlynx ( in answer archive )
Suggestions to Xilinx:
- Have somebody document the plethora of V2 DCI hardware
and software problems ('challenges'? 'features'?) in one
place ( a detailed application note? ) ASAP.
- Hiding the FPGA IOB/CLB/FF/interconnect power consumption
numbers within an encrypted spreadsheet and buggy SW makes
it impossible to cross-check the resulting power calculations.
- Please take a look at page 145 of the ORCA-4 datasheet
("Package Parasitics"): there, in human readable form, is a
usable package model that can be simulated in any SPICE.
- Also note that the ORCA-4 IBIS C_COMP value for the general
purpose LVDS inputs is a much more reasonable 2 pf.
- Real differential LVDS input terminators are quite wonderful
(no VCCO power hit, no split terminator DC offset problems).
Making them available (LXXX_25_DT) only in the V2Pro, and
not in the Spartan3, is an exceptionally HUGE mistake.
Brian
Article: 61338I just installed ISE 6.1 and tried to start a new project. The program responded by immediately crashing (several times, same result). Anybody else experience this?Article: 61339
Xilinx's marketing is about as bad as it gets. Frankly, I'm surprised that they are the largest FPGA vendor. I have had bad experiences with them in the (far) past. In particular, when they changed vendors for the serial proms. They cut off the old vendor with the (wishful) thinking that the new one would take over. Well, the new one choked big time and us users were left holding the bag. At the time I was running my own company and desparately needed those parts. Good luck!!! I was F**KED!!! Peter took exception the last time I mentioned this. In private e-mail I reminded him that if Xilinx doesn't ship product he still collects his pay check - as a private business owner if I didn't ship product the revenue stopped. My latest run in with brand X shouldn't have happened. I thought I was doing them a favor by ordering a license renewal for $4K. Guess what? XILINX SCREWED UP!!! We have a year end deadline (Sep 25); did Xilinx care? NO!!!! Only by Hurcelean effort did I mananage to get the order placed (after I started a week and a half before the deadline). I got an apology from them. But SO WHAT!! I think they have gotten full of themselves and don't really care. They know us suckers have to deal with them no matter what. Well, maybe we do. Doesn't make me feel any better.Article: 61340
Hi group,
I had a small clarification on Host-PCI Bridge. For Host-PCI
bridge design, PCI 2.3 specs. itself are enough or PCI-PCI Bridge
specs. are needed? Also in case of a Host-PCI Bridge, can we have
Memory Read line, Memory Read Multiple, Memory write and invalidate
commands executed? If we need to implement them do we need larger fifo
inside the bridge? Minimum of how many fifos do we need in a Host to
PCI Bridge Design?
Thanks
Naveen
Article: 61341
Brian,
I completely agree that Xilinx should document these errata in one place,
AND make it easy to find. Having to search for these implies that you
suspect the problem to-begin-with.
There's another nasty gotcha (Virtex-II and above) which still isn't
documented as such -- the issue of requiring that the P and N pin pairs use
the same clock domain (per direction) if either of those pins utilize the
DDR registers in that IOB.
Thanks for pointing these out to us.
Bob
"Brian Davis" <brimdavis@aol.com> wrote in message
news:a528ffe0.0310011956.50945ab5@posting.google.com...
> Top Ten Things I wish I never had needed to learn about LVDS_25_DCI:
>
>
> 1) Parallel DCI input standards in Virtex2 continuously modulate
> the input termination offset voltage unless you enable bitgen's
> FreezeDCI option
>
> 2) With FreezeDCI on, the entire bottom half of 2V40, 2V80, and
> any CS144 packages are unavailable for LVDS_25_DCI inputs (this
> includes half the global clock inputs to the chip) due to DCI
> unavailability in banks having only ALT_VRP/N pins
>
> 3) With FreezeDCI on, dual purpose config pins cannot be used as
> LVDS_25_DCI inputs
>
> 4) 5.2i S/W doesn't catch illegal pin assignments due to #2 and #3
>
> 5) With FreezeDCI on, input terminator accuracy for 2R values
> degrades to +/-20%
>
> 6) With FreezeDCI on, each bank will have a (different) random
> input offset voltage due to split terminator 2R variations
>
> 7) LVDS_25_DCI terminator overhead power per input pair far exceeds
> the theoretical 62.5 mW number published in Answer Record 15633
>
> 8) With FreezeDCI on, worst case VCCO power overhead per
> LVDS_25_DCI input pair approaches 100 mW
>
> 9) With FreezeDCI on, worst case DCI VRP/N VCCO power overhead
> per I/O bank approaches 200 mW
>
> 10) 5.2i Xpower incorrectly assigns DCI power to the 1.5V VCCINT
> supply, and it doesn't use the worst case DCI power numbers
>
> 11) V2 Power Estimator spreadsheet doesn't support LVDS_25_DCI,
> but if you fake it by using two single ended DCI 2R split
> terminated inputs per actual LVDS pair, it also uses the
> wildly optimistic power numbers
>
> 12) LVDS_25_DCI IBIS models don't work in HyperLynx
>
> 13) Massive 8pf IBIS C_COMP input capacitance value for the
> V2 LVDS inputs requires external back termination and/or
> input matching scheme to achieve reasonable signaling when
> driving FPGA inputs from a modern high speed LVDS driver
>
>
> Interesting Answer Database Search Keywords:
>
> FreezeDCI
> LVDS AND DCI AND termination
> DCI AND power
> IBIS AND Hyperlynx ( in answer archive )
>
>
> Suggestions to Xilinx:
>
> - Have somebody document the plethora of V2 DCI hardware
> and software problems ('challenges'? 'features'?) in one
> place ( a detailed application note? ) ASAP.
>
> - Hiding the FPGA IOB/CLB/FF/interconnect power consumption
> numbers within an encrypted spreadsheet and buggy SW makes
> it impossible to cross-check the resulting power calculations.
>
> - Please take a look at page 145 of the ORCA-4 datasheet
> ("Package Parasitics"): there, in human readable form, is a
> usable package model that can be simulated in any SPICE.
>
> - Also note that the ORCA-4 IBIS C_COMP value for the general
> purpose LVDS inputs is a much more reasonable 2 pf.
>
> - Real differential LVDS input terminators are quite wonderful
> (no VCCO power hit, no split terminator DC offset problems).
>
> Making them available (LXXX_25_DT) only in the V2Pro, and
> not in the Spartan3, is an exceptionally HUGE mistake.
>
>
> Brian
Article: 61342Jake Janovetz <jakespambox@yahoo.com> wrote: : + You may not want (or need) an 18-bit multiplier Then define the wires with smaller width : + The design may have exceeded the built-in mults and therefore need : other resources. I didn't test, but maybe synthesis with fall back to LUT multipliers when all block multipliers are allocated : + You may want a pipelined multplier there's an Applikation Note how to code to get pipelined LUT multipliers ( for Block multipliers this doesn't apply) : + Placement of a core may be more optimal for a particular design need : than the built-in mults : Uwe Bonnes <bon@elektron.ikp.physik.tu-darmstadt.de> wrote in message news:<bles4l$q75$1@news.tu-darmstadt.de>... :> Kiran <kirandev@msn.com> wrote: :> : Hi All, :> :> : My design has many multipliers of different input/output widths. I Please, don't fullquote. Bye -- Uwe Bonnes bon@elektron.ikp.physik.tu-darmstadt.de Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt --------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------Article: 61343
>The Ribbon cable is connected to the Celoxica boards using the expansion >header on the celoxica boards. This expansion header allows digital >communition in and out of the FPGA on the Celoxica board. The data on >the ribbon cable ha a bus width of 32 (i.e. is 32 bits wide) and and the >data changes every 100 ns (10 MHz). All I want to do is remove the >ribbon cable and replace it with an optical or wireless communication >system (preferably a wireless system). So system would be: I'm not familiar with what's available in the radio area. You can get fiber transducers that will do the job. Look for gigabit ethernet parts and browse around when you find an interesting vendor. The interface is usually differential PECL. Beware of parts for telco usage. They will be high power and very sensitive to get long range. Expensive. You have to do a parallel to serial conversion on the transmit end. The receiver end has to do clock recovery, serial to parallel, and also lock onto the byte/word boundaries. There is actually another level of complication. The clock recovery needs enough transitions so you probably need something like 8b/10b encoding and decoding. You might find a PHY type chip set that will do all that. But maybe that stuff is all included in the big PCI chip now. If you can't find any PHY chips, consider using several fibers and doing your own Manchester encoding/decoding. Decoding is pretty easy (at least after you see it) if you have a clock that's running at 8x the bit rate. You can drop that to 4x for all but the first FF if you process 2 bits in parallel. Just use enough fibers so your receiver can do the decoding at a sane clock speed. -- The suespammers.org mail server is located in California. So are all my other mailboxes. Please do not send unsolicited bulk e-mail or unsolicited commercial e-mail to my suespammers.org address or any of my other addresses. These are my opinions, not necessarily my employer's. I hate spam.Article: 61344
Stan Lackey wrote: > emacs or xemacs with verilog-mode. It's not exactly what you're looking > for, but it has many many great features, including mostly-automatic > netlisting of upper levels in your hierarchy. Search for both using > yahoo, not to forget the signal completion, complex templates, and things like semi-automated instantiation and testbench-generation :-) This all is at least true for the XEmacs VHDL-mode. Regards, MarioArticle: 61345
naveen wrote: > Hi group, > I had a small clarification on Host-PCI Bridge. For Host-PCI > bridge design, PCI 2.3 specs. itself are enough or PCI-PCI Bridge The PCI-to-PCI bridge spec is intended just for what it says. It does not cover host-bridge issues. That is at least true for the PCI-to-PCI bridge spec I've at hand here. Nevertheless, it cannot be a mistake to read this spec as well when designing other bridges. > specs. are needed? Also in case of a Host-PCI Bridge, can we have > Memory Read line, Memory Read Multiple, Memory write and invalidate Of course. Why not? > commands executed? If we need to implement them do we need larger fifo > inside the bridge? Minimum of how many fifos do we need in a Host to > PCI Bridge Design? It depends mainly on your host bus. If you don't want to support delayed transaction completion (especially for reads but also for writes) you do not need FiFos (or better say buffers) at all. When there's some data not available, you could easily deassert TRDY# until the data becomes available. Btw., a PCI-to-PCI bridge is also not required to implement any data buffers. Of course, that is not the best idea in view of PCI bus efficiency. But finally it depends on the final application and how much time you want invest to develop your host bridge (and how much space you have available in your FPGA ;-). Regards, MarioArticle: 61346
Vinh Pham wrote: > > As for #2, the problem is you have three addresses hooked up to your DP ram: > RDBYTE_CNT, DPRA, and A. One port is a R/W port and must use the same > address for both R and W. The second port is R only and has it's own > address. Yes, you are right. I need to rethink this, maybe it will be possible to use only two addresses and save some resources. -- Robert PudlikArticle: 61347
>Could be a typing error, I already found one. In ECS 6.1i (the schematic >editor), if you put the USELOWSKEWLINES=TRUE attribute on a signal, the >resulting .vhf file contains a spelling error that keeps the design from >synthesizing (SIGNAL is spelled "SIGANL"). Interesting. I wonder how that one got past testing. I'll bet it gets tested now/tomorrow. Many years ago, a friend described a neat trick for testing software. The idea was to make sure the each line of code was at least exerecised in order to find the gross bugs. He started with a clean listing. Install breakpoints. When you get there, mark that line and the rest of the block, that is until the next branch, skip, return or such. Eventually, you have marked off all the easy stuff and now you have to generate test cases to tickle the hard/obscure ones. This is just the software version of making sure your test bench wiggles all the signals at least once. -- The suespammers.org mail server is located in California. So are all my other mailboxes. Please do not send unsolicited bulk e-mail or unsolicited commercial e-mail to my suespammers.org address or any of my other addresses. These are my opinions, not necessarily my employer's. I hate spam.Article: 61348
Whoopsy, brain-fart. My previous code will create 3 levels of logic. If we
didn't have to detect both nine 1s or nine 0s, then it'd work okay.
Here's an idea for one that should generate 2 levels, but it looks uglier.
Definately not as compact as rickman's.
data[64:0] -- input signal
ninth_bit[7:0] -- intermediate signal
run_dibble[31:0] -- intermediate signal
run_byte[7:0] -- output signal
for byte 0...7
ninth_bit[byte] = data[(byte+1)*8]
for dibble 0...3
lsb = byte*8 + dibble*2
msb = byte*8 + dibble*2 + 1
if data[lsb] = ninth_bit[byte] AND data[msb] = ninth_bit[byte] then
run_dibble[byte*4 + dibble] = 1
else
run_dibble[byte*4 + dibble] = 0
end
end loop
lsb = byte*4
msb = byte*4 + 3
if run_dibble[msb:lsb] = "1111" then
run_byte[byte] = 1
else
run_byte[byte] = 0
end
end loop
Article: 61349> Yes, you are right. I need to rethink this, maybe it will be possible > to use only two addresses and save some resources. Best of luck. Always a pain having to re-organize your design.
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