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I know that this has been asked for several times, but I haven't found a satisfying answer yet. Has anybody got a simple vhdl model for an I2C slave ? All I need is to Read/Write some IO bits. I would like it to be as small as possible (20-40 Xilinx CLBs or Altera LCELLs). Thanks for your help, AlexArticle: 61426
Hi, Yes, The crosspoint for using carry-chain or luts are somewhere between 2 and 3 levels. But I have found that I can continue doing logic operation by continuing the carry-chain. It's easy to do "and","or" operation on the carry-chain. So it depends on how signals are used afterwards. But maybe for your problem, simple LUT implementation is a better solution. GöranArticle: 61427
Brian, First, I checked the IBIS model in Hyperlynx v7, and it works fine. Next, the driver for LVDS is required to have a 100 ohm drive impedance. If you use a device that does not comply to this, then you most definitely can and will get reflections shot back to the input. I can not comment on parts that do not meet the LVDS specifications when connected to the FPGA: that requires some engineering (as always). I have received back confirmation that the issues are being worked on from the support group, and I also notified the apps folks about some kind of app note for use of the LVDS DCI feature, since it is not as clean as the internal solution (in Virtex II Pro). Not ignored at all..... Austin Brian Davis wrote: > Austin, > > > > >But I have one correction, the capacitance to ground is ~ 8pf, > >thus the differential capacitance is 4 pf (two 8 pf in series). > > > The 8pf C_COMP number I quoted was the max value from the > latest Xilinx IBIS file; that's about as 'correct' as I can get. > > I agree with your observation that Cdiff = 1/2 C_COMP for > a differential input propagating entirely in odd mode. > > However, please don't overlook the main point of item #13 : > > Although you market these as "840 Mbps" devices, the input > capacitance of the general purpose LVDS IOBs is so high as > to make it extremely difficult to drive the FPGA inputs from > the latest generation of high speed LVDS drivers without well > planned back termination and/or input matching. > > See for instance Table 13, footnote 1 of XAPP622, which > clearly states that, although tested interoperable, the > V2 devices do not meet the rise/fall requirements of the > SFI-4 specification. > > > > >Unfortunately, to meet ESD, and have the IOB also do the > >other 35 standards, the capacitance is not as low as > >everyone would like. > > > I realize there's a lot of baggage in there, but the "Brand L" > C_COMP of 2pf that I quoted shows that others have done much > better in a similar generation of FPGA (and they also included > one-reference-resistor-per-chip adjustable differential input > terminators ). > > > > >Simulations at the die, however, show a very nice waveform, even > >though it may look questionable at the pins of the device (due to > >the t-line effects). > > > The die input might look 'nice' on the very first edge, but not > when the round trip reflection returns from the far end... > > ( In my first tests, the FPGA input reflection completely closed > the data eye at the driver output when using a TI 65LVDS100 driving > about 2" of coupled microstrip into the V2. ) > > > > >And we will check out the IBIS model issue. > > > Xilinx already knows about this one; see Answer Record 1782 in > the Answer Archive. Although archived, it does not list a solution > other than the cheesy 'stick a dummy terminator into the model' > approach. I can confirm that this was still broken in the > March-April '03 time frame when using the latest Xilinx V2 IBIS > models and Hyperlynx version available at the time. > > > > >As for allowing the power estimator, spreadsheet, answers, etc. to > >all catch up with all of the "top ten" list: that is just tough to > >do, but you are right, we should do it (and will). > > > See Webcase 467802 (March '03), Webcase 476968 (May-August '03), > CR 170813, CR 171469 > > > > >Spartan 3 addresses a different market than Virtex II, or II Pro, > >and was never intended to replace them. We reserve the right to > >differentiate product lines by having different features. > > > For frills like PowerPCs, differentiate away... > > But, if you think having a decent differential DCI input > termination solution for Spartan-3 is a luxury, you're way > off target. > > The alternative of placing external resistors on the high > pin count BGA packages being offered in the Spartan-3 family > quickly gets to be unoptimal/unworkable. > > Many of the high speed parts that were formerly (P)ECL are now > moving to LVDS for high speed I/O ( A/D, D/A, mux/demux, etc ). > > > > >but that was a) not the market we were after, > > > The first page of your Spartan-3 datasheet lists the following: > - 622 Mb/s data transfer rate per I/O > - Six differential signal standards including LVDS > - Termination by Digitally Controlled Impedance > > How is it that you can tout the resistor-saving advantages of > DCI for single ended I/O, but then ignore the most critical, > higher speed, differential I/O standards? > > Brian > > > > >Brian, > > > >Excellent list. > > > >But I have one correction, the capacitance to ground is ~ 8pf, thus the > >differential capacitance is 4 pf (two 8 pf in series). Unfortunately, > >to meet ESD, and have the IOB also do the other 35 standards, the > >capacitance is not as low as everyone would like. Simulations at the > >die, however, show a very nice waveform, even though it may look > >questionable at the pins of the device (due to the t-line effects). > > > >Nothing beats an on die 100 ohm termination. > > > >LVDS_25_DCI was never intended to replace a simple 100 ohm external > >termination. That was reserved for the improved input terminator (a > >simple 100 ohms) that was added to Virtex 2 Pro. It was also an > >afterthought, that was suggested to us by a customer, when they messed > >up, and forgot all the resistors. It is VERY ugly in the power > >department, and we did not realize that the power could be as high as > >~85 mW per pair due to the way the DCI circuit operates. Also, freezing > >DCI does mean that you might be trying to measure the 25 ohm termination > >voltage with the reference resistors, so the current in them does > >increase, too. > > > >If I may suggest, use LVDCI_25_DCI only for clock inputs, or a few > >signals. Always use DCI_Freeze to reduce the jitter. Also look at what > >happens when you do not have a 100 ohm termination. For some signals, > >and lengths of pcb, it may not be required. And we will check out the > >IBIS model issue. > > > >As for allowing the power estimator, spreadsheet, answers, etc. to all > >catch up with all of the "top ten" list: that is just tough to do, but > >you are right, we should do it (and will). > > > >Spartan 3 addresses a different market than Virtex II, or II Pro, and > >was never intended to replace them. We reserve the right to > >differentiate product lines by having different features. I am sure > >everyone would like to have a Spartan 3 that could replace a Virtex II > >or II Pro, but that was a) not the market we were after, and b) not > >possible with the process/design/technology we chose. > > > >The Spartan folks are busily planning and designing their next chip(s), > >and we in the Virtex camp are busy with our next product offering. > > > >Thanks for your comments, > > > >Austin > >Article: 61428
Goran Bilski <goran@xilinx.com> wrote in message news:<blj44a$hht2@cliff.xsj.xilinx.com>... > Hi, > > The register file is included in that number. > > Göran Thanks. One other question, is it a pure RTL design or does it instantiate Xilinx specific primitives? Ditto for NIOS? Cheers, JonArticle: 61429
> > What I've figured out is this: if I begin with the given tutorial > files, delete everything on the block diagram, and make a minimal > system, everything works great. If I make the exact same minimal > system starting from a new project file, then it won't work. > Obviously there is some setting already adjusted in the example > tutorial file that is not mentioned in the tutorial, but I can't > figure out what it is. Has anyone else experienced this? > > When it does not work, here is what happens. After programming the > fpga, it runs momentarily (I can configure the led's to a given state > to verify, also the GERMS monitor spits out the correct system boot > id) and then the board defaults back to its original demo > configuration. > Hi, I believe what's missing here is the requirement (for these boards) to tri-state unused IO pins. This is a project setting that is turned on in the example designs (and probably in the tutorial design files). To do this with your new design (in Quartus 2/3.0): Go to the Assignments menu --> Device --> Device & Pin Options --> Unused Pins tab, and select the option to reserve all unused pins "As inputs, tri-stated". Some background: The Nios dev boards have a feature for implementing and demonstrating remote reconfiguration of the Stratix/Cyclone device. This is implemented by a single IO which is connected to the board's MAX7128 configuration controller - if the FPGA asserts this IO, the MAX device will follow the power-on configuration sequence in an attempt to boot the FPGA with (presumably) a new FPGA configuration stored in flash. However, if this pin is not used in your design, and is not reserved as tri-stated, the pin could (and does) float to tell the MAX device to perform re-configuration. Our literature on the older Nios/Apex dev board *did* have this step in the tutorial steps (although that board didn't have the "blow your brains out" remote reconfiguration feature, you did need to tri-state unused IOs to prevent bus contention if you weren't talking to external memory in your design). This step was regrettably omitted in the Stratix/Cyclone tutorials -- I will make sure this is corrected for the next rev of these documents! Another documentation note: The 1S40 board manual document "mnl_nios_board_stratix_1s40.pdf", does have pin-out tables describing pin assignments for all features on the board. Alternatively, the "standard_32" example design for the 1S40 board has Quartus pin assignments for all features as well (this makes it very easy to just grab what you need for a new design without worrying about an incorrect IO assignment). Also, to Jerry, who had OCI problems: I believe this is a different issue, as your design is booting/resetting just fine but the debugger wouldn't connect... if you have not heard from your FAE, feel free to zip up your Quartus project and send it my way to the 'decoded' email address below. My yahoo mail account has been completely hosed as a result of the M$ "patch" virus going around :( Jesse Kempa Altera Corp. jkempa at altera dot comArticle: 61430
Martin Euredjian wrote: > The only reason I might get something out of it will be because I will pour > over the 500 page book on my own and experiment for many, many hours. That's where learning happens. > I took the course because, after a two-year effort --starting from scratch-- > to learn FPGA's, That's a pretty broad topic. Consider picking focusing on a more specific goal. > I don't need to pay $1,000, > travel and burn two days' work to endure that experience. Learning that was worth the price of admission. > So, I wonder. Was this a fluke? Hey, that's *our* trademark, "if it works, it's a fluke" :) > Are Altera's courses better? No. Just different. > I heard that Altera chooses to use insiders. Is this true? Yes. > Does it make a difference? The problem is that vendors can't help talking about their specific architecture and special features. There is too little coverage on design entry and simulation, where there is the most to learn. related thread: http://groups.google.com/groups?q=vhdl+trial+error+self+study+boris -- Mike TreselerArticle: 61431
hjones1380@hotmail.com (pjjones) writes: > I'm working with a Stratix EP1S40 evaluation baord, after going > through the tutorial successfully (there is no mention of pin > assignments in the tutorial, that would have been a nice touch i > think), I tried a similar nios processor design from scratch to no > avail. Hmm. I've done several designs that I've tried on en NIOS Development kit. Have you assigned the correct location to all the pins? Pay attention to the PLD_RECONFIGREQ_N which will trigger a reconfiguration when asserted. If you download your code directly to the FPGA without storing it in the FLASH it will start running the design stored in the FLASH. Petter -- A: Because it messes up the order in which people normally read text. Q: Why is top-posting such a bad thing? A: Top-posting. Q: What is the most annoying thing on usenet and in e-mail?Article: 61432
Martin, I am sorry you had a bad experience. I will ask about it. I had heard from others that this particular course was a good one (some of my own staff have taken it), so I am hoping that your experience was not the course, but perhaps the instructor (still unfortunate, and not acceptable). Austin Martin Euredjian wrote: > I recently took the "Advanced FPGA Implementation (v6)" Instructor-Led > Course and came out of it with a fair bit of dissappointment. I don't want > to engage in Xilinx-bashing but it bothers me that the course was simply not > worthy of the title it was given. > > The only reason I might get something out of it will be because I will pour > over the 500 page book on my own and experiment for many, many hours. The > class boiled down to a bunch of slides (a very small subset of the book, > maybe 20%) being read out loud with a degree of re-interpretation. The labs > were based on an obscure design that was not introduced at all. So, all you > could do in the alloted time was type from the book like a robot and move > on. No real learning took place there. > > I took the course because, after a two-year effort --starting from scratch-- > to learn FPGA's, I thought that an advanced course taught by an expert in > the field would be a great way to take my skills up a notch or two. I > needed to get to that proverbial last few percent and, frankly, I also felt > stuck with regards to timing optimization, floorplanning and other advanced > areas. I thought that an "advanced" course would be taught by a peer who'd > offer the sort of insight that only comes from significant experience in the > field and, yes, inside information. That is certainly not what happened. I > can read slides just as well as the next guy. I don't need to pay $1,000, > travel and burn two days' work to endure that experience. > > So, I wonder. Was this a fluke? Are the other coursed different, better, > worst? Are Altera's courses better? It seems that Xilinx contracts out the > trainig to a third party (a company called "Technically Speaking". I heard > that Altera chooses to use insiders. Is this true? Does it make a > difference? > > Thanks, > > -- > ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ > Martin Euredjian > > To send private email: > 0_0_0_0_@pacbell.net > where > "0_0_0_0_" = "martineu"Article: 61433
> So, I wonder. Was this a fluke? Are the other coursed different, better, > worst? Are Altera's courses better? It seems that Xilinx contracts out the > trainig to a third party (a company called "Technically Speaking". I heard > that Altera chooses to use insiders. Is this true? Does it make a > difference? To answer your question about Altera: Yes, we do have a dedicated training department with teachers who do the classes at customer sites. I understand that our distributor Arrow also leads traning events. For special workshops and things like that (such as the SOPC World events going on now or other internal training events), other Altera employees specializing in that area may present. Occasionally we have had third parties present *on their specific product*, such as those who do synthesis tools. Here's a link to the Altera Training homepage: https://buy.altera.com/etraining/etraining.asp Hope this helps, Jesse Kempa Altera Corp. jkempa at altera dot comArticle: 61434
Just about the circle: Another approach for circle drawing is using trignometry. The inputs for circle drawing macro are of course the circle Center(X0,Y0), Radius R, and the real time scanning index (x,y), assume active pixel matrix is 512x512. First we need to check if vertical index is within the drawn circle by compare |y-Y0| <= R, if yes then scale |y-Y0| to radius R. Let say yy = |y-Y0|/R. For this we may use LUT for 1/R, L1(R) = 1/R. yy = |y-Y0| * L1(R) (1) Notes that yy = sin(teta), teta is an angle in first quadrant, 0<= yy <= 1 Known sin(teta) one can find cos(teta) by another LUT, let say L2(yy)=xx, where xx=cos(teta) or L2(|y-Y0| * L1(R)) = xx (2) Notes: sin^2(teta) + cos^2(teta)=1 Perform multiplying to find out |x-X0| = R*xx or |x-X0| = R*L2(|y-Y0| * L1(R)) (3) solve for x from (3) : x = X0 +- R*L2(|y-Y0| * L1(R)) (4) From equation (4), one can see x is a function of X0, Y0, R, and y. Note that (4) can be computed during horizontal blank time (take several clock cycles), register results, and perform another calculation... That means for a pair of LUTs L1, L2, it can draw more than one circle. use LUT to figure out |x-X0|, where LUT imply function F(S) = C where S=sin(teta) and C = cos(teta) in the first quadrant. We can use RAM LUT for this function F(S)= C, where S=sin(theta) and C=cos(theta) in the first quadrant circle. The inputs to this circle macro function are of course the Center(X0,Y0) and Radius R.Article: 61435
Just about circle: Another approach for circle drawing is using trignometry. The inputs for circle drawing macro are of course the circle Center(X0,Y0), Radius R, and the real time scanning index (x,y), assume active pixel matrix is 512x512. First we need to check if vertical index is within the drawn circle by compare |y-Y0| <= R, if yes then scale |y-Y0| to radius R. Let say yy = |y-Y0|/R. For this we may use LUT for 1/R, L1(R) = 1/R. yy = |y-Y0| * L1(R) (1) Notes that yy = sin(teta), teta is an angle in first quadrant, 0<= yy <= 1 Known sin(teta) one can find cos(teta) by another LUT, let say L2(yy)=xx, where xx=cos(teta) or L2(|y-Y0| * L1(R)) = xx (2) Notes: sin^2(teta) + cos^2(teta)=1 Perform multiplying to find out |x-X0| = R*xx or |x-X0| = R*L2(|y-Y0| * L1(R)) (3) solve for x from (3) : x = X0 +- R*L2(|y-Y0| * L1(R)) (4) From equation (4), one can see x is a function of X0, Y0, R, and y. Note that (4) can be computed during horizontal blank time (take several clock cycles), register results, and perform another calculation... That means for a pair of LUTs L1, L2, it can draw more than one circle.Article: 61436
Make sure all unused pins are "As Inputs Tri-Stated". This is done in the Settings-> Device ->Device & Pin Options I think having the default "As output, driving ground" causes problems on the development board, because some of the unused pins may be connected to other things such the recofiguration signal to the Max Device (active low). I have burned myself plenty of times on this. --Chris "Nial Stewart" <nial@spamno.nialstewart.co.uk> wrote in message news:<3f7d76a1$0$11000$fa0fcedb@lovejoy.zen.co.uk>... > > I'm working with a Stratix EP1S40 evaluation baord, after going > > through the tutorial successfully (there is no mention of pin > > assignments in the tutorial, that would have been a nice touch i > > think), I tried a similar nios processor design from scratch to no > > avail. > > I've got the Cyclone eval board. The tutorial for this _does_ mention > pin assignments, you've to run a Tcl script called assign_pins.tcl > or something similar (it's on a different PC that's off at the minute). > > Things kept mysteriously breaking when I'd run this script and I > found the script contained a device assignment statement which switched > the device from a Cyclone 1C12XXX to a Stratix device (can't remember > exactly which one). I just removed the device assignment line > to stop it changing the device after I'd set it when setting the > project up. > > > > > > What I've figured out is this: if I begin with the given tutorial > > files, delete everything on the block diagram, and make a minimal > > system, everything works great. If I make the exact same minimal > > system starting from a new project file, then it won't work. > > Obviously there is some setting already adjusted in the example > > tutorial file that is not mentioned in the tutorial, but I can't > > figure out what it is. Has anyone else experienced this? > > It might be worth checking your pin assignment Tcl script to check > that it's not doing the same to you. > > > Nial Stewart > ------------------------------------------------ > Nial Stewart Developments Ltd > FPGA and High Speed Digital Design > www.nialstewartdevelopments.co.ukArticle: 61438
Austin Lesea <Austin.Lesea@xilinx.com> wrote in message news:<3F7DA078.521C7B51@xilinx.com>... > Brian, > > First, I checked the IBIS model in Hyperlynx v7, and it works fine. > > Next, the driver for LVDS is required to have a 100 ohm drive impedance. If > you use a device that does not comply to this, then you most definitely can > and will get reflections shot back to the input. > > I can not comment on parts that do not meet the LVDS specifications when > connected to the FPGA: that requires some engineering (as always). Austin: Market will decide! -qlyus > > I have received back confirmation that the issues are being worked on from > the support group, and I also notified the apps folks about some kind of app > note for use of the LVDS DCI feature, since it is not as clean as the > internal solution (in Virtex II Pro). > > Not ignored at all..... > > Austin >Article: 61439
Vinh Pham wrote: >The orignal question was: What algorithms can you use to generate live >video, that contains only line art (lines, rectangles, curves, circles, >etc.), if you can't use a frame buffer. > >The benefit of using a frame buffer is flexibility. Namely you get random >access to any pixel on the screen. This opens up a wide range of algorithms >you can use to play the performance-area-complexity tradeoff game. > >Without a frame buffer, you only have sequential access to your pixels. No >going back, no going forward. Quite Zen I suppose. Anyways, you lose access >to a lot of frame buffer algorithms, but some can still be used. > > > I guess you are talking about raster-scan displays without a pixel to pixel frame buffer behind it, and not about vector-drawing displays (like an oscilloscope in X-Y mode). Interesting theoretical enterprise, but I really don't see the point. I remember quite some years ago talking to a guy who had invested millions of $ in developing software for Evans&Sutherland color vector displays for the drug design industry. I just casually threw out the comment that in 5 years the E&S gear would be in the dumpster, and everybody would have switched to pixel/raster scan systems. They were doing stuff with up to 100,000 simulated spheres on the screen, and he essentially told me I was so nuts that he couldn't even begin to explain how impossible it would be for a frame buffer to ever handle such a task. Well, of course, all that is history now, and his company had to invest a BUNDLE in converting all their software to adapt to the frame buffer mode of doing things. JonArticle: 61440
> Oh, boy... Vinh, you didn't need to apologize. But I do appreciate the Yeah I did. There were two annoying voices in my head. "You should apologize because..." "Screw that, you sholdn't apologize because..." I was getting sick of hearing them arguing :_p > gesture. It's far too easy to get wires (messages, meaning, intent, > whatever) crossed over this form of communication. Yes, it's difficult enough to communicate face to face, much harder when all you have are smiley faces. And we're always too lazy to read or write carefully. Another problem is it's too easy to forget there's a live person on the other side of the screen. We forget our manners and tend to write the first thing that comes to mind. > I could go on, but don't want to turn this into a huge philosophy thread. Then you have far more self control than I ;_) I tend to write overly long posts that most people never finish reading. > So, I just thought it was funny that it seemed I couldn't explain myself out > of a paper bag. I kept saying "these are the specs" and you (and others) > would say "never mind the specs, this is the better way to do it". And > round-and-round in circles we went. No big deal. Yeah a silly little cycle we got ourselves into. At some point things start turning more emotional than intellectual. People's comments become overly critical and we end up being defensive. > But thanks, I appreciate it. I'll go ahead and take back all those bad > things I said about you as soon as my wife gets home. I promise. :-) LOL. I bet your wife will roll her eyes. If you ever watched the movie Swingers, there's a scene where a bunch of friends almost get into a violent confrontation with another group of guys, a gun gets drawn. A few scenes later, they're all hanging out together playing Nintendo like they were highschool buddies. Anyways, thanks for accepting the apology and not rubbing things in. Regards, VinhArticle: 61441
qlyus <qlyus@yahoo.com> wrote: : Austin Lesea <Austin.Lesea@xilinx.com> wrote in message news:<3F7DA078.521C7B51@xilinx.com>... :> Brian, :> :> First, I checked the IBIS model in Hyperlynx v7, and it works fine. :> :> Next, the driver for LVDS is required to have a 100 ohm drive impedance. If :> you use a device that does not comply to this, then you most definitely can :> and will get reflections shot back to the input. :> :> I can not comment on parts that do not meet the LVDS specifications when :> connected to the FPGA: that requires some engineering (as always). : Austin: Market will decide! <lots of quote deleted> qlyus: Wow! About 170 line quoted to add one single line. Please don't spoil the archives that way! Bye -- Uwe Bonnes bon@elektron.ikp.physik.tu-darmstadt.de Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt --------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------Article: 61442
Interesting you wrote this, Valentin -- because I was revisiting VS.NET this morning trying to decide what features I liked. I bottom-lined it at the fact that I like the class method and parameter tooltips. I wished something were availble to me like that under Matlab and FPGA tools for functions and primitives. Aside from that, I don't like the project organization nearly as much as I do under Protel DXP. I actually enjoy using the DXP GUI. I appreciate a low-price (free for WebPack) product, but I would certainly pay for a well-designed product that helps me get work done faster and doesn't force the tool to be in the way. Matlab is an example of a good tool gone bad. They added this cheese-ball GUI interface and probably paid good money to develop it. It just contributed to the bloat of the package and their prices have skyrocketed ever since. Jake "Valentin Tihomirov" <valentin@abelectron.com> wrote in message news:<3f7d51a0$1_1@news.estpak.ee>... > > development. I tried Visual Studio > > .NET for a software app I needed to write. > > It is very intelligently-designed. > > I have some experiance in developing with Visual Studio. It has reputation > of "Visual Notepad". It is not a visual tool like for ex. Dephi. I with you > to appretiate something IntelliJ Idea like. That is what I can call > "intelligent". WebPack and VS are good editors for entering text and > highlighting keywords. VS cannot exactly determine where function is > declared, neither it can determine errorous line of code from linker. As > well as WebPack doesn't. > > Protel DXP is an impressive tool, Aldec is much more specific. However, I > use WebPack due to its zero price. I would avoid Visual Studio as it is too > big (3GB) and clunky notepad.Article: 61443
> Lot's of good stuff. I'll have to read it later tonight. I just wanted to Don't worry about it, there's nothing profound in it, I just carried away when I start writing :_) > modify one assumption you made. Resolution. I'll be working at 4K x 2.5K > and maybe as high as 4K x 4K and 60 frames per second soon. My current work > is at 2K x 1.5K, 60 fps though. Jeeze that's quite a bit of bandwidth there. > http://www.ecinemasys.com/products/display/edp100/pdf/edp100_preliminary.pdf Cool way to expand the use of a Cinema Display. I bet HD sized CRTs are awfully heavy and delicate. So with your product someone could view live HD footage from inside a small helecoptor, for instance? Looks like it'll change the way people think of and us HD displays. Pretty cool to make a product that can affect the way people do their work. > The design is 100% mine, electrical, board layout, mechanical, FPGA, > firmware, GUI, etc. Must be fun having a hand in every aspect of a product, it's your baby. Like the olden days of hand crafted cars, before Ford turned it into an assembly line. > Some of the highlights: Two 1.485GHz inputs, two 1.485GHz outputs, 165MHz > DVI output, USB, lots of interesting real-time processing going on. Is PCB layout particulary challenging? Heh everything probably is when you're processing that much data. Doesn't seem like it needs much ventilation, so heat's not much of a problem? :> Yes, it has a frame buffer (four frames actually). No, it shouldn't be used > to render graphics primitives. But...but...;_)Article: 61444
> than 2 LUTs of delay, but very slightly. The code looks cleaner and > the implementation is tight. Yes, it looks really clean. Nice :_) Cool use of the XNOR and AND functions to do your compare. A lot more elegant than all my for loops. Learn something new every day. But something is nagging me. Can't your xnor/and scheme be implemented in two levels of LUTs without the need of a MUXF5? I must be missing something, or maybe the problem is the synthesizer isn't mapping it that way? The first level LUTs would implement (output = (bit0 xnor bit1) and (bit1 xnor bit2)). You'd have four LUTs in the first level, then the second level LUT would AND all of them together.Article: 61445
Followup to: <g94qnv8hcapk91jgl1djj6nqlvtq9ounte@4ax.com> By author: kkilzer.remove.this@mindspring.com In newsgroup: comp.arch.fpga > > Thanks to all for the clear explanations. I will further assume that > since SRAM is similar to logic (unlike DRAM), that the SRAM is > practically immune to upset also. I'll stop worrying about random > events in the logic, and concentrate my testing on the other factors > that were mentioned. > SRAM is more immune than DRAM, but SRAM is frequently built using process-optimized cells, and do have a (small) probability of being affected by intrinsic radiation. This is why most processor vendors have started using ECC on the caches; especially the larger (L2+) caches. That being said, I don't expect to see these in an FPGA, and it's highly unlikely to be the source of any problems you might see. -hpa -- <hpa@transmeta.com> at work, <hpa@zytor.com> in private! If you send me mail in HTML format I will assume it's spam. "Unix gives you enough rope to shoot yourself in the foot." Architectures needed: ia64 m68k mips64 ppc ppc64 s390 s390x sh v850 x86-64Article: 61446
> Interesting theoretical enterprise, but I really don't see the point. Someone just had a rare situation where they couldn't use a frame buffer. You can think of it as an intellectual exercise :_) > I remember quite some years ago talking to a guy who had invested millions of $ in developing Hahaha no wonder he refused to believe you. Sort of like when you buy a crappy product, but you make yourself believe it's great, because of all the money you spent on it. Did E&S's vector display draw only outlines of spheres, or shaded? Shading with x-y vectors doesn't sound too fun. What do you think was the main reason why people switched to pixel/raster? Simplicity? Scales better? Thanks for the interesting anecdote JonArticle: 61447
That was a good read. Of course, anything that says FPGA designers will have a bright and glorious future is always nice ;_) Thanks jakabArticle: 61448
>From the article: Antifuse also has some power consumption advantages over SRAM. Can anybody explain that to me? Perhaps that refers to static current? [The SRAM part of an SRAM FPGA doesn't change during normal operation so the F part of C*V^2*F is 0.] -- The suespammers.org mail server is located in California. So are all my other mailboxes. Please do not send unsolicited bulk e-mail or unsolicited commercial e-mail to my suespammers.org address or any of my other addresses. These are my opinions, not necessarily my employer's. I hate spam.Article: 61449
"Mike Treseler" wrote: I'll have to respectfully disagree with some of what you said. > > The only reason I might get something out of it will be because I will pour > > over the 500 page book on my own and experiment for many, many hours. > > That's where learning happens. If all learning could happen from books schools and universities, at all levels, wouldn't have a reason to exist. I think humankind is genetically wired to very efficiently learn through a tradition of verbal communication that cannot be ignored. Of course, a lot of real and very significant in-depth learning happens outside of that context, but one cannot state that this is the only way learning happens at the exclusion of the verbal tradition. Then there's the issue of efficiency. I've taken a few very well taught courses over the years where, within a few days, you go from a rudimentary understanding of the subject to having a very clear and organized insight from which to build. This isn't so much due to the verbal tradition I was speaking of, but rather because someone who truly understands the subject AND is a good teacher lays out the subject right there, in front of you, to assimilate and build from. Good teachers are worth 1000 books. No doubt about it. So, if you attend a good course, you can be on your way very quickly. It's a matter of efficiency. And, while it might be true that all in the universe could be learned from books and, these days, the Internet, there's a real imporant factor we must not forget: the business equation. If what you do is a hobby then, by all means, burn time experimenting and reading through hundreds of documents, surfing the Web or playing with dev boards. However, in the context of a business that needs to get product out the door, it is much more efficient to pay someone to show you the ropes quickly and then get on with your work. > > I took the course because, after a two-year effort --starting from scratch-- > > to learn FPGA's, > > That's a pretty broad topic. > Consider picking focusing on a more specific goal. You misunderstood where I was coming from. Having "graduated" after two years of very hard work in the field I wanted to get an insight into techniques that would let me squeeze another 5% of perfomance out of a design. I also wanted to understand if there were better approaches to the overall subject, at a high level. That's why I went to an "ADVANCED" class, and not an intro to FPGA's. In my mind, if you say you are teaching an advanced class there are a few requirements that cannot be violated. One of them being who teaches that class and what degree of information is communicated. Let me ask you this. Do you think that spending 45 minutes listing all of the I/O out of a DCM block has a place in an advanced class? Or how many clocks can be distributed in a Virtex II? How about getting into how to properly start-up a DCM with real-world issues and code? Well, we didn't do the latter. We did the former. And, when a student asked about how to use the phase shifter clock input there was no answer. > > I don't need to pay $1,000, > > travel and burn two days' work to endure that experience. > > Learning that was worth the price of admission. $1,000 is a lot of money for a printed version of PowerPoint slides. I would gladly pay $5,000 for a class that had the right content. Money is not the issue here. If you tell me you'll teach an advanced class for $1K, then do it. If that class requires $10K, then tell me so. -- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ Martin Euredjian To send private email: 0_0_0_0_@pacbell.net where "0_0_0_0_" = "martineu"
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