Custom Search
Site Home Archive Home FAQ Home How to search the Archive How to Navigate the Archive
Compare FPGA features and resources
Threads starting:
Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z
Silly question but, is your design meeting timing? (how fast is the design in question?) Have you tried over constraining? -- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ Martin Euredjian To send private email: 0_0_0_0_@pacbell.net where "0_0_0_0_" = "martineu" "MM" <mbmsv@yahoo.com> wrote in message news:blhqhd$cijqt$1@ID-204311.news.uni-berlin.de... > Hi all, > > I've been going through the archives trying to find a hint to the problem I > am having with a state machine (it occasionaly enters illegal states and > doesn't come out) and I found this post: > --------------------------------------------------------------------- > From: iglam (rluking@deletethispart.home.com) > Subject: Re: safe state machine design problem > Newsgroups: comp.lang.vhdl, comp.arch.fpga > Date: 2001-06-08 08:26:41 PST > > > If you are using enumerated types, then your > when others clause is doing nothing. You've already listed > all of the elements of the state type when you built your > case statement. So, the first thing is, your synthesis tool > tosses that line. > > Next, your synthesis engine decides to one-hot build the state machine. > OK, great. Then, you screw up the state by forcing two bits high, and > it goes out to lunch. Makes sense. The synthesis tool was not > instructed to put in logic to avoid or get out of lockout states. > > Either enumerate the Illegal states and get the synthesis tool to > build a regulare state machine > > or > > Get the synthesis tool to put the lockout state protection in. I'm not > familiar with Leonardo, so someone else will have to suggest specific > solutions. > > Bob > --------------------------------------------------------------------- > > So, I was wondering if ignoring illegal states when using enumerated types > is true for XST? That would explain at least some of my problems... Can I > somehow force XST to make a state machine safe without manually coding all > the states? > > > Thanks, > /Mikhail > >Article: 61402
Austin, > >But I have one correction, the capacitance to ground is ~ 8pf, >thus the differential capacitance is 4 pf (two 8 pf in series). > The 8pf C_COMP number I quoted was the max value from the latest Xilinx IBIS file; that's about as 'correct' as I can get. I agree with your observation that Cdiff = 1/2 C_COMP for a differential input propagating entirely in odd mode. However, please don't overlook the main point of item #13 : Although you market these as "840 Mbps" devices, the input capacitance of the general purpose LVDS IOBs is so high as to make it extremely difficult to drive the FPGA inputs from the latest generation of high speed LVDS drivers without well planned back termination and/or input matching. See for instance Table 13, footnote 1 of XAPP622, which clearly states that, although tested interoperable, the V2 devices do not meet the rise/fall requirements of the SFI-4 specification. > >Unfortunately, to meet ESD, and have the IOB also do the >other 35 standards, the capacitance is not as low as >everyone would like. > I realize there's a lot of baggage in there, but the "Brand L" C_COMP of 2pf that I quoted shows that others have done much better in a similar generation of FPGA (and they also included one-reference-resistor-per-chip adjustable differential input terminators ). > >Simulations at the die, however, show a very nice waveform, even >though it may look questionable at the pins of the device (due to >the t-line effects). > The die input might look 'nice' on the very first edge, but not when the round trip reflection returns from the far end... ( In my first tests, the FPGA input reflection completely closed the data eye at the driver output when using a TI 65LVDS100 driving about 2" of coupled microstrip into the V2. ) > >And we will check out the IBIS model issue. > Xilinx already knows about this one; see Answer Record 1782 in the Answer Archive. Although archived, it does not list a solution other than the cheesy 'stick a dummy terminator into the model' approach. I can confirm that this was still broken in the March-April '03 time frame when using the latest Xilinx V2 IBIS models and Hyperlynx version available at the time. > >As for allowing the power estimator, spreadsheet, answers, etc. to >all catch up with all of the "top ten" list: that is just tough to >do, but you are right, we should do it (and will). > See Webcase 467802 (March '03), Webcase 476968 (May-August '03), CR 170813, CR 171469 > >Spartan 3 addresses a different market than Virtex II, or II Pro, >and was never intended to replace them. We reserve the right to >differentiate product lines by having different features. > For frills like PowerPCs, differentiate away... But, if you think having a decent differential DCI input termination solution for Spartan-3 is a luxury, you're way off target. The alternative of placing external resistors on the high pin count BGA packages being offered in the Spartan-3 family quickly gets to be unoptimal/unworkable. Many of the high speed parts that were formerly (P)ECL are now moving to LVDS for high speed I/O ( A/D, D/A, mux/demux, etc ). > >but that was a) not the market we were after, > The first page of your Spartan-3 datasheet lists the following: - 622 Mb/s data transfer rate per I/O - Six differential signal standards including LVDS - Termination by Digitally Controlled Impedance How is it that you can tout the resistor-saving advantages of DCI for single ended I/O, but then ignore the most critical, higher speed, differential I/O standards? Brian > >Brian, > >Excellent list. > >But I have one correction, the capacitance to ground is ~ 8pf, thus the >differential capacitance is 4 pf (two 8 pf in series). Unfortunately, >to meet ESD, and have the IOB also do the other 35 standards, the >capacitance is not as low as everyone would like. Simulations at the >die, however, show a very nice waveform, even though it may look >questionable at the pins of the device (due to the t-line effects). > >Nothing beats an on die 100 ohm termination. > >LVDS_25_DCI was never intended to replace a simple 100 ohm external >termination. That was reserved for the improved input terminator (a >simple 100 ohms) that was added to Virtex 2 Pro. It was also an >afterthought, that was suggested to us by a customer, when they messed >up, and forgot all the resistors. It is VERY ugly in the power >department, and we did not realize that the power could be as high as >~85 mW per pair due to the way the DCI circuit operates. Also, freezing >DCI does mean that you might be trying to measure the 25 ohm termination >voltage with the reference resistors, so the current in them does >increase, too. > >If I may suggest, use LVDCI_25_DCI only for clock inputs, or a few >signals. Always use DCI_Freeze to reduce the jitter. Also look at what >happens when you do not have a 100 ohm termination. For some signals, >and lengths of pcb, it may not be required. And we will check out the >IBIS model issue. > >As for allowing the power estimator, spreadsheet, answers, etc. to all >catch up with all of the "top ten" list: that is just tough to do, but >you are right, we should do it (and will). > >Spartan 3 addresses a different market than Virtex II, or II Pro, and >was never intended to replace them. We reserve the right to >differentiate product lines by having different features. I am sure >everyone would like to have a Spartan 3 that could replace a Virtex II >or II Pro, but that was a) not the market we were after, and b) not >possible with the process/design/technology we chose. > >The Spartan folks are busily planning and designing their next chip(s), >and we in the Virtex camp are busy with our next product offering. > >Thanks for your comments, > >Austin >Article: 61403
Bob Perlman wrote: > >Second, how much offset voltage modulation are you seeing with DCI >update enabled? > Enough to scare me bitless. I don't have a plot at hand, IIRC one side of a quiescent undriven LVDS_25_DCI input exhibited pulse modulation with a peak amplitude of about +/-100 mV away from nominal Voffset for a duration of ~2 us at ~25 kHz rate. For a better idea of the pulse width and rate of the modulation waveform, look at the plot of Answer Record 12573 and imagine that for the entire duration of one of those VRP/VRN stairsteps, your DCI resistor(s) suddenly modulate +/- 20% in value. > >Is it enough to justify all the difficulties you're >experiencing with FreezeDCI? > Personally, I would not use any of the DCI standards without using FreezeDCI (or the DCIUpdateMode of the newer V2P parts). Although the problems I described yesterday pertained to one of the parallel termination standards, the underlying problem exists for the series terminators as well, it's just not as visible, but could easily affect output edge jitter. BrianArticle: 61404
"Mike Treseler" <mike.treseler@flukenetworks.com> wrote in message news:3F7C9A79.8090106@flukenetworks.com... > No. I mean change the synthesis seting from one-hot to binary. > > Synthesis does not always cover the "others" case > completely for one-hot encoding. I tried gray and it didn't help. I will try binary tomorrow, but I would like to know when XST covers the "others" case and when it doesn't.... /MikhailArticle: 61405
"Martin Euredjian" <0_0_0_0_@pacbell.net> wrote in message news:pi5fb.8964$5P7.7307@newssvr27.news.prodigy.com... > Silly question but, is your design meeting timing? (how fast is the design > in question?) > Have you tried over constraining? The design isn't really fast, only 50 MHz. The state machines in question are not on critical path. Overconstraining doesn't work well because of a big 3rd party core, which if overconstrained doesn't meet the timing at all. I think Mike is right and my problem is related to asynchronous inputs, but I still want to know more about how XST extracts state machines... /MikhailArticle: 61406
You can apply a different set of constraints (tigher) just to the logic of your state machine while other parts of the design are governed by a (presumably) looser PERIOD constraint. What you need to do is define FROM/TO constraints to the logic related to the state machine. The easiest way to do it might be to use the constraints editor and find all the FF's related to that module. It's pretty easy from there forward. The PERIOD constraint has the lowest priority of all, so FROM/TO will override it only for the specified logic. So, you could have a PERIOD set to 20ns while FROM/TO is specified to 10ns. Also, I forgot to ask. Does this happen during/around any reset signals? I suffered the pain of having one-hot state machines wake up in illegal states. Ultimately it was due to not handling reset properly and having FF's cleared/set at different times. -- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ Martin Euredjian To send private email: 0_0_0_0_@pacbell.net where "0_0_0_0_" = "martineu" "MM" <mbmsv@yahoo.com> wrote in message news:blivi5$ckn15$1@ID-204311.news.uni-berlin.de... > "Martin Euredjian" <0_0_0_0_@pacbell.net> wrote in message > news:pi5fb.8964$5P7.7307@newssvr27.news.prodigy.com... > > Silly question but, is your design meeting timing? (how fast is the design > > in question?) > > Have you tried over constraining? > > The design isn't really fast, only 50 MHz. The state machines in question > are not on critical path. Overconstraining doesn't work well because of a > big 3rd party core, which if overconstrained doesn't meet the timing at all. > I think Mike is right and my problem is related to asynchronous inputs, but > I still want to know more about how XST extracts state machines... > > /Mikhail > >Article: 61407
I recently took the "Advanced FPGA Implementation (v6)" Instructor-Led Course and came out of it with a fair bit of dissappointment. I don't want to engage in Xilinx-bashing but it bothers me that the course was simply not worthy of the title it was given. The only reason I might get something out of it will be because I will pour over the 500 page book on my own and experiment for many, many hours. The class boiled down to a bunch of slides (a very small subset of the book, maybe 20%) being read out loud with a degree of re-interpretation. The labs were based on an obscure design that was not introduced at all. So, all you could do in the alloted time was type from the book like a robot and move on. No real learning took place there. I took the course because, after a two-year effort --starting from scratch-- to learn FPGA's, I thought that an advanced course taught by an expert in the field would be a great way to take my skills up a notch or two. I needed to get to that proverbial last few percent and, frankly, I also felt stuck with regards to timing optimization, floorplanning and other advanced areas. I thought that an "advanced" course would be taught by a peer who'd offer the sort of insight that only comes from significant experience in the field and, yes, inside information. That is certainly not what happened. I can read slides just as well as the next guy. I don't need to pay $1,000, travel and burn two days' work to endure that experience. So, I wonder. Was this a fluke? Are the other coursed different, better, worst? Are Altera's courses better? It seems that Xilinx contracts out the trainig to a third party (a company called "Technically Speaking". I heard that Altera chooses to use insiders. Is this true? Does it make a difference? Thanks, -- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ Martin Euredjian To send private email: 0_0_0_0_@pacbell.net where "0_0_0_0_" = "martineu"Article: 61408
Thanks to all for the clear explanations. I will further assume that since SRAM is similar to logic (unlike DRAM), that the SRAM is practically immune to upset also. I'll stop worrying about random events in the logic, and concentrate my testing on the other factors that were mentioned. KevinArticle: 61409
ge wrote: > > Never mind. Once again, as soon as I ask the question, I find the > answer. It's in the fitter help, and Atmel's FAQ. You can also run the fitters Fit150x.exe -h2 >GetCL.txt this puts the help dump into the TXT file for later reference. -jgArticle: 61410
Hi, The register file is included in that number. Göran Jon Beniston wrote: >Xilinx's MicroBlaze CPU is listed as requiring 950 LUTs. Does this >include the register file, or does that use a block RAM? > >Cheers, >JonB > >Article: 61411
Austin Lesea wrote: > > Any idea why Lattice quote a MAX of 64 pins at IO MAX voltage stress > > levels ? (I'm bemused at how the 65th pin knows the state of the other > > 64 :) <snip> > So, 64 IOs may be just under the 15 or 20 year life projection model limit, and > 65 IOs may be just over the limit in the model. Our experience was that the > number of IOs under stress did not make a measurable difference. I agree that it > is pretty hard to imagine that having a next door neighbor with a hot plate > increases your chances of burning down your house, but it does make sense that > overall, the more devices you have under stress, the sooner one would expect a > failure........even if we did not see that in our testing. Yes, I'm sure it's some arbitrary FIT number, or could be some test equipment limit :) - but it does raise the eyebrows .... > > The most recent tests did allow us to relax the bank requirements for V2P, so now > all banks may operate at 3.3V, and it will not affect the lifetime nor the > reliability of the part (as opposed to the original banking restrictions). > > It could be that they have not seen the same results in their testing from their > fab? Turns out this is very tricky stuff, and implants, layout, etc affects the > performance of these devices under these extrememly high field stress > conditions. There is a magic recipe that one finds, and then sticks with it > (just like any other IC process). Thanks, interesting summary. I recall seeing a note from Philips research a couple of years ago, about a breakthrough in high voltage devices (> 100V) in (IIRC) 0,5u process. Seems what they found was thinner worked better, the opposite of what E field stress would suggest, and they concluded it was because the 'loose electrons' has less time to accelerate, and so had less energy with which to do serious damage :) Does show there is no substitute for bench tests... -jgArticle: 61412
Hi, What synthesis tool did you use? When I instanciate primitives directly in my code, they tend to stay in the netlist. The synthesis tool usually leaves them alone. If isn't working attach a U_SET attribute to them so the tools thinks it's a RPM which is normally leaves alone. That has been my approach for doing primitives. Göran John_H wrote: >Goran Bilski <goran@xilinx.com> wrote in message news:<blhm91$h0f1@cliff.xsj.xilinx.com>... > > >>Hi, >> >>Why not use the carry-chain? >> >>You can do any kind of detection on that primitive and it will save you LUTs >> >>Göran >> >> > >I tried that approach earlier today but I wasn't getting the carry >chain I was trying to infer. The Virtex-IIs started getting poorer at >getting on/off carry chains timing-wise relative to the general logic >resources so I was trying to get general logic to work; I suspect >Spartan-3s are similar. If I go straight to register, I would need 4 >LUTs to go into the register through the XORCY instead of the natural >XORCY so the logic savings isn't a given to achieve the speed but I >could keep it to 3 LUTs with a small routing hit. > >I believe I'd need to implement all the carry chain primitives through >the generate block, including the MUXCYs and XORCY elements because >the synthesizer sees that "oh, it's a short chain" and converts my >simple arithmetic form to a cascade of LUTs rather than the carry >chain. I tried my tricks, I stopped pursuing. > >Maybe I'll try to coax it again tomorrow. Thank goodness for that >generate! > >Article: 61413
I'm not an IT guy, but I remember that if you were using an IMAP based mail server (instead of POP3), you could download just the headers...Article: 61414
> development. I tried Visual Studio > .NET for a software app I needed to write. > It is very intelligently-designed. I have some experiance in developing with Visual Studio. It has reputation of "Visual Notepad". It is not a visual tool like for ex. Dephi. I with you to appretiate something IntelliJ Idea like. That is what I can call "intelligent". WebPack and VS are good editors for entering text and highlighting keywords. VS cannot exactly determine where function is declared, neither it can determine errorous line of code from linker. As well as WebPack doesn't. Protel DXP is an impressive tool, Aldec is much more specific. However, I use WebPack due to its zero price. I would avoid Visual Studio as it is too big (3GB) and clunky notepad.Article: 61415
Hi all! I have a design with combinational clocks. The synthesis report asks me to use CLOCK_SIGNAL with these signals. However, I have a problem using this constraint. It can only be used through Verilog/VHDL and not from constraints editor(Xilinx ISE 5.1). So i am using the following statement: //synthesis attribute CLOCK_SIGNAL of J1106 is yes; However, this doesn't seem to work. Their is still the message in synthesis report "Please use CLOCK_SIGNAL constraint....". The hierarchy of my design is as follows: module DFF_54174.v instantiated in module SHEET3.v as Z158. Module SHEET3.v instantiated in module DMAB.v [TOP LEVEL] as CIRCUIT3. The signal to which i want to apply constraint is pin10 of DFF_54174 tied to J1106 in SHEET3.v. J1106 is a wire in TOP level DMAB.v. Now is my above constraint statement OK? If yes why is now working? Where to place this statement? TOP level? or in SHEET3.V or in DFF_54174.v ? The synthesis report indicates this signal as : CIRCUIT3_J11061:O ? should i use this instead of J1106? Should i use quotes around [yes]? Regards RiderArticle: 61416
Neeraj Varma <neeraj@cg-coreel.com> wrote: : I'm not an IT guy, but I remember that if you were using an IMAP based mail : server (instead of POP3), you could download just the headers... : "rickman" <spamgoeshere4@yahoo.com> wrote in message : news:3F78E378.49B36C58@yahoo.com... :> I believe there is a way to configure Eudora to pull in just the headers < a lot of full quote deleted> <Rant mode on> Why keep people complaining about spam while by fullquoting they spoil the archives? <Rant mode off> -- Uwe Bonnes bon@elektron.ikp.physik.tu-darmstadt.de Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt --------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------Article: 61417
Hello,
I'm trying do implement some large integer operation
(Multiple-precision arithmetic) in Nios software application (modular
addition, multiplication and inverse). I'd found a few complicated
library files and it's work perfectly in Windows and Linux
environment. When I try to compile by using GNUPro compiler, a lot of
standard header files is missing.
Does anybody know solutions for this problem? Or any simpler
source code accompany with step by step instruction for beginner?
Article: 61418A good read for anyoane interested in FPGA http://www.embedded.com/showArticle.jhtml?articleID=15201141 --- jakabArticle: 61419
> I'm working with a Stratix EP1S40 evaluation baord, after going > through the tutorial successfully (there is no mention of pin > assignments in the tutorial, that would have been a nice touch i > think), I tried a similar nios processor design from scratch to no > avail. I've got the Cyclone eval board. The tutorial for this _does_ mention pin assignments, you've to run a Tcl script called assign_pins.tcl or something similar (it's on a different PC that's off at the minute). Things kept mysteriously breaking when I'd run this script and I found the script contained a device assignment statement which switched the device from a Cyclone 1C12XXX to a Stratix device (can't remember exactly which one). I just removed the device assignment line to stop it changing the device after I'd set it when setting the project up. > > What I've figured out is this: if I begin with the given tutorial > files, delete everything on the block diagram, and make a minimal > system, everything works great. If I make the exact same minimal > system starting from a new project file, then it won't work. > Obviously there is some setting already adjusted in the example > tutorial file that is not mentioned in the tutorial, but I can't > figure out what it is. Has anyone else experienced this? It might be worth checking your pin assignment Tcl script to check that it's not doing the same to you. Nial Stewart ------------------------------------------------ Nial Stewart Developments Ltd FPGA and High Speed Digital Design www.nialstewartdevelopments.co.ukArticle: 61420
I would tackle it one .h file at time. Do a search and make sure you don't already have the required header files, but your compiler search path is not including their location. Then, if you don't have them, start copying them over from the working systems. Or possibly do a search on sourceforge, etc. You could also post the particular header filenames here with for better help. Ken "Maxlim" <maxlim79@hotmail.com> wrote in message news:a6140565.0310030509.51bec4d1@posting.google.com... > Hello, > I'm trying do implement some large integer operation > (Multiple-precision arithmetic) in Nios software application (modular > addition, multiplication and inverse). I'd found a few complicated > library files and it's work perfectly in Windows and Linux > environment. When I try to compile by using GNUPro compiler, a lot of > standard header files is missing. > Does anybody know solutions for this problem? Or any simpler > source code accompany with step by step instruction for beginner?Article: 61421
Thanks a lot for your responses but I still don't understand some points. For example, what do you mean whan you say there's a linux core running on the spartan ? Doas it mean that there a soft CPU wich runs linux ? About you P.S, it's exactly what we want to do. Could you also tell me if the PCI bus is 32 or 64 bits ? Do I have to buy a PC with a 64 bit PCI slot ? Regards, Stephane On Tue, 30 Sep 2003 15:22:12 -0700, Heng Tan wrote: > Hi,there > I received my avnet VirtexII Pro development kit(XC2VP7) this month. I > know it is somehow different from the evaluation board(stronger in > general). But I guess I can try to give some premitive views. And > right now, since I am still a newbie on this board, the information I > gave may not be accurate. > > 1.In the flash memory of the development board, there already stores a > linux core there, which will run on the spartan(the pci bridge) when > power up. you can use a serial cable to connect with a host pc and use > a hypertermianl program to watch. The flash also installed some other > applications which will help you monitor the board like avmon. I can't > provide further details right now since my work are usually done in > windows > > 2.I already installed the board into a pci slot and used it. So the > answer to the second question is yes.( although it took me more than a > week to contact avnet engieer and figure out some tedious technique > detail. The documment coming with the board is not that helpful.) > There is a tool called PCIutility which can help you to debug the > board and download the file. However all these work are finished under > the 3rd party driver (jungo or to say windriver). So as far as I know, > probably only on windows. > > 3.I havn't test the memory speed yet. So I can't tell whether there is > a bottleneck yet.( you need to write your own project both hd and sw > to contol all types of the memory) > > 4. with the pciutility I mentioned above, yes you can program the FPGA > through PCI. > > 5. you can connect it to a host pc not simply a monitor. > > Hope it is helpful to you. > > P.S. Do you know whether it is possible to feed input to the FPGA on > board from a PC and read output to the PC?? If so, how?? I need to > implement an algorithm and now stuck here. I mean write your own API > instead of using some tools. >Article: 61422
Does SDK 6.1i run in native mode under Linux? Is it shipping? BTW: Has anybody in Scandinavia received their ISE 6.1i package yet? Petter -- A: Because it messes up the order in which people normally read text. Q: Why is top-posting such a bad thing? A: Top-posting. Q: What is the most annoying thing on usenet and in e-mail?Article: 61423
I'm also a beginner in programming CPLD / FPGA. I can recommend the book "VHDL for programmable Logic" by Kevin Skahill (ISBN: 0-201-89586-2). As first development kit is the Xilinx ISE Webpack very good. It's complet free and easy to use. Check out: www.xilinx.com Hope, that helped you Sincerely Dominic SuterArticle: 61424
Goran Bilski <goran@xilinx.com> wrote in message news:<blj78j$h0h1@cliff.xsj.xilinx.com>...
> Hi,
>
> What synthesis tool did you use?
> When I instanciate primitives directly in my code, they tend to stay in
> the netlist.
Synplify does a good job of leaving the instantiated primitives in the
code, sure. My first issue was that I believe carry chains are longer
than 2 levels of LUTs. The second issue is that I was trying to infer
- not instantiate - the adder chain by adding 1 to {1,1,1} when all
three LUTs worth of logic are valid, using the sign as my output. The
synthesizer turned the inferrence into LUTs which is probably more
effective in logic delay. I would need to generate 3 MUXCYs per chain
for 8 chains. If I want the quick-register destination, I need to
also instantiate the XOR in the sign bit. 4 primitives replicated 8
times for timing which *may* be worse. I chose not to pursue hte
instantiations because of the expected lower performance.
> The synthesis tool usually leaves them alone.
> If isn't working attach a U_SET attribute to them so the tools thinks
> it's a RPM which is normally leaves alone.
> That has been my approach for doing primitives.
>
> Göran
>
> John_H wrote:
>
> >Goran Bilski <goran@xilinx.com> wrote in message news:<blhm91$h0f1@cliff.xsj.xilinx.com>...
> >
> >
> >>Hi,
> >>
> >>Why not use the carry-chain?
> >>
> >>You can do any kind of detection on that primitive and it will save you LUTs
> >>
> >>Göran
> >>
> >>
> >
> >I tried that approach earlier today but I wasn't getting the carry
> >chain I was trying to infer. The Virtex-IIs started getting poorer at
> >getting on/off carry chains timing-wise relative to the general logic
> >resources so I was trying to get general logic to work; I suspect
> >Spartan-3s are similar. If I go straight to register, I would need 4
> >LUTs to go into the register through the XORCY instead of the natural
> >XORCY so the logic savings isn't a given to achieve the speed but I
> >could keep it to 3 LUTs with a small routing hit.
> >
> >I believe I'd need to implement all the carry chain primitives through
> >the generate block, including the MUXCYs and XORCY elements because
> >the synthesizer sees that "oh, it's a short chain" and converts my
> >simple arithmetic form to a cascade of LUTs rather than the carry
> >chain. I tried my tricks, I stopped pursuing.
> >
> >Maybe I'll try to coax it again tomorrow. Thank goodness for that
> >generate!
> >
> >
>
> --
Site Home Archive Home FAQ Home How to search the Archive How to Navigate the Archive
Compare FPGA features and resources
Threads starting:
Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z