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True, but those muxes are virtually useless for data path because the bit
pitch doesn't match the bit pitch of the arithmetic. Count 4-LUTs or
flip-flops instead.
Peter Alfke wrote:
> rickman wrote:
> > Xilinx likes to
> > pad the number since they feel they have "uber-cells" which count as
> > more than 1 each. But then again, they don't define the term "logic
> > cell", so I guess they can count them any way they want.
>
> Not really, the "padding" is exactly 12.5%, so it has been defined and
> is deterministic.
> Marketing wants to get credit for the additional multiplexers that the
> competition does not have.
> If you are a purist, just count slices and devide by 2, or multiply CLBs
> by 4 (Virtex and Spartan2) or by 8 (Virtex2 and Spartan3). That gets you
> the number of LUTs+flip-flops.
>
> Peter Alfke
> >
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 60626Alan Nishioka <alann@accom.com> wrote: : Allan Herriman <allan.herriman.hates.spam@ctam.com.au.invalid> wrote in message news:<qoocmv4dr277d3hu3tem6qbik3ap5ju1g7@4ax.com>... :> Does anyone know what to do with the pin on V2P called "RSVD"? :> :> I guess I'm meant to leave it open, but I haven't found anything in :> the datasheet or the Xilinx answers database that says for sure. : http://direct.xilinx.com/bvdocs/userguides/ug012.pdf : Table 5-1 page 345 in the Virtex II-Pro Platform FPGA User Guide says : RSVD Reserved pin - do not connect Could it be that RSVD means ReSerVeD? :-) -- Uwe Bonnes bon@elektron.ikp.physik.tu-darmstadt.de Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt --------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------Article: 60627
Absolutely no hacking and rewriting required if you download the Linux kernel from http://penguinppc.org/dev/kernel.shtml (chose linuxppc_2_4_devel tree). Virtex-II Pro is fully supported in this kernel tree including drivers for Uart, Intc, System ACE, Ethernet, GPIO, PCI, IIC, TFT, touchscreen, and PS/2. The kernel has recently been upgraded to work well with EDK generated HW systems. While the kernel is targetting the ML300 board it works on the Insight board with just one change (you have to hardcode the Ethernet MAC address in arch/ppc/boot/simple/embed_config.c). - Peter Shamile wrote: > Hi Jon, > > This sounds pretty exciting. I have some questions. > > 1) What board are you using. I am assuming its some board with Virtex > II Pro. > 2) Where did you download the kernel sources from? > 3) What bootload/monitor program did you use (U-boot/Red boot). Or you > arent using one? > 4) Do you have ethernet support? > > I know you are still at debugging stage but any information will be > useful to us as we are in the process of getting Linux running on > Memec's V2P4 evaluation board. > > Thanks, > > Shamile > > Jon Masters <jonathan@jonmasters.org> wrote in message news:<vlrf2keihait3c@corp.supernews.com>... > >>Hi, >> >>I thought I would let you know that I have now got Linux booting and >>running a sash shell on the serial console. >> >>I use the Microblaze serial driver, a little of the Mind patches >>(however I had to rewrite the interrupt controller driver because of the >>swapped registers and fix other bits) and stuff I have written myself. >>This runs on stock 2.4.21, not the Montavista kernel. >> > > >>There are a few issues like busybox having problems because of a bug in >>the page table code which causes problems for shared binaries. >>I had to implement a fix for the Xilinx TLB errata and a few other bits >>and I think this has introduced a subtle bug somewhere. >> >>More info when the port is complete at which point I will post a link. >> >>Jon.Article: 60628
Allan Herriman wrote: > On Tue, 16 Sep 2003 11:19:13 -0700, "Steven K. Knapp" > <steve.knappNO#SPAM@xilinx.com> wrote: > > >>The Spartan-3 pinout tables are described in the Spartan-3 data sheet, which >>also provides a direct link to a ZIP file containing all the ASCII text >>tables. >> >>The Spartan-3 applications team slightly modified the text format to make it >>easier to parse with a simple script. > > > The individual .csv files in the zip file > http://www.xilinx.com/bvdocs/publications/s3_pin.zip > have *different* formats (numbers of columns, etc.). That means a > parser must cope with a number of special cases, as well as handling > the completely different format used for Virtex (etc.) parts. > > Is it possible to make all the formats the same? (This is a > rhetorical question and doesn't require an answer.) Ideally there's be a text file for each device, for each package, with 6 columns: row, col, pin, name, bank, type ... ... ... Using commas or tabs or whatever as the field seperator doesn't matter too much, most data import utilities can deal with it. As much as it pains me, I'm using MS excel to do this, just import the raw data into sheets, then create secondary sheets that use the vlookup() function to pull out the data I need. Not ideal, but it works. Back to the purpose of my original message, it seems that I was naively optimistic that there would be any footprint compatability across families, within the same package type. V2 and V2Pro have a few common pins (or pin classes), such as the power and GND, but most of the rest are different. Spartan3 is even more different again. Within families it's fine - that's obviously the "upgrade path" that Xilinx have designed for. Cheers, JohnArticle: 60629
I used Webpack version 5.x a while ago and was able to
access block rams by infering them rather than instantiating
them. I don't know if this worked in version 4.x. For this
approach to work, you need to craft your Verilog code to match
the BRAM structure so the synthesizer could see that you REALLY
want BRAM and not distributed ram. It took me several iterations
to find the proper Verilog style.
Here's code that seemed to infer BRAM for a Spartan chip:
// ____________________________________________________________
// IN Buffer
reg [7:0] in_buf [511:0];
reg [8:0] in_rd_addr;
always @(posedge clk)
if (fifo_rd_valid)
in_buf[in_ptr] <= fifo_rd_data;
always @(posedge clk)
in_rd_addr <= next_in_rd_ptr;
assign fast_rd_data = in_buf[in_rd_addr] ;
Good Luck!
John Providenza
Marc Guardiani <marc@guardiani.com> wrote in message news:<%0K8b.1112$Kt4.203@nwrdny02.gnilink.net>...
> Matt,
>
> Thanks for the info. I looked at the Xilinx web site and what they are
> now calling Foundation is not what they had called Foundation
> previously. Previously, ISE started and Foundation ended with version
> 4.x (which used Aldec technology). What they are now calling Foundation
> is something completely different than what I was refering to. I stand
> corrected.
>
> Marc
>
>
> Matt wrote:
> > Marc,
> >
> > Xilinx has four versions of their ISE software. They are:
> >
> > 1) Webpack
> > 2) BaseX
> > 3) Foundation
> > 4) Alliance
> >
> > 1 and 2 are subsets of Foundation which has the XST synthesis tool. The
> > differentiator is that #3 has the full toolset with support for all Xilinx
> > devices. Numbers 1 and 2 have XST but only support the low to mid range
> > devices. Alliance is the third party flow which does not include XST.
> > It should be noted that XST does not support devices based on the 4000
> > architecture. i.e. 4000 family, Spartan/Spartan XL. All other families are
> > supported. If you need support for the 4000 stuff you need to go third
> > party.
> >
> > Hope this helps...
> >
> >
> > Matt
> >
> > "Marc Guardiani" <marc@guardiani.com> wrote in message
> > news:R_u8b.758$U41.369@nwrdny01.gnilink.net...
> >
> >>Are you going to be using ISE or Foundation? They are two completely
> >>different software packages. ISE is very similar to the Webpack (another
> >>reply you received describes the differences). Foundation is no longer
> >>supported by Xilinx and is based on third party software. Also
> >>Foundation will not do the newer FPGAs and ISE will not do the older
> >
> > FPGAs.
> >
> >>Dave wrote:
> >>
> >>>I am just about to go through a 115 page introduction tutorial on the
> >
> > XCESS
> >
> >>>website for using the Xilinx Webpack 4.x edition. However I will be
> >
> > using
> >
> >>>the ISE Foundation 4.x edition and want to know if I am wasting my time
> >>>reading the entire Webpack tutorial to learn how to use the ISE
> >
> > Foundation
> >
> >>>edition. I am assuming its all the same, with Webpack just having less
> >>>features. Anyone who is familiar with both editions that can let me know
> >
> > to
> >
> >>>go ahead with this or STOP - and find a tutorial at Xilinx instead (I
> >
> > need
> >
> >>>to install the software for their tutes I think) would be much
> >
> > appreciated.
> >
> >>>Initial stages will be purely schematic entry. VHDL will come later.
> >>>
> >>>Regards
> >>>Dave
> >>>
> >>>
> >>
> >
> >
Article: 60630So, the 12.5% stand for "virtually useless" multiplexers, useful RAM capability, and the super-useful SRL16 shift-register capability that enhances Ray's formidable talents even more. :-) Peter Alfke ================================== Ray Andraka wrote: > > True, but those muxes are virtually useless for data path because the bit > pitch doesn't match the bit pitch of the arithmetic. Count 4-LUTs or > flip-flops instead. > > PArticle: 60631
Touche'
Yes, I agree that the other stuff far outweigh the uselessness of the muxes.
It still is a shame the muxes are not oriented so that the inputs are from
adjacent columns so that the bit pitches match. The SRL16's are especially
powerful as well as under-appreciated. I still count those as LUTs if I am
comparing FPGAs though, but keeping in mind there is no equivalent in the
competing arrays. I'd trade away the muxes long before I gave up the carry
chains and SRL16s (Xilinx still has the best carry chain structure out of all
the FPGA vendors).
Peter Alfke wrote:
> So, the 12.5% stand for "virtually useless" multiplexers, useful RAM
> capability, and the super-useful SRL16 shift-register capability that
> enhances Ray's formidable talents even more. :-)
>
> Peter Alfke
> ==================================
> Ray Andraka wrote:
> >
> > True, but those muxes are virtually useless for data path because the bit
> > pitch doesn't match the bit pitch of the arithmetic. Count 4-LUTs or
> > flip-flops instead.
> >
> > P
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 60632
Hi Peter,
It is difficult to answer this without seeing the actual design. If you
can send me the qar file , I will have an engineer figure out what is
triggering this behavior. If you have a mysupport request which has the
design files, the mysupport request number will work too. Is the path to the
mif file embedded as a VHDL parameter?
Thanks
- Subroto Datta
Altera Corp.
"H. Peter Anvin" <hpa@zytor.com> wrote in message
news:bka9eg$9qd$1@cesium.transmeta.com...
> I'm having a very odd problem... Quartus II (2.2) has started ignoring
> .mif file changes on me when doing "smart compile", which requires me
> to sit for 20 minutes and recompile the whole design for a simple
> memory change.
>
> The really weird part is that this is new behaviour -- I have one
> project on which this works beautifully and it was a major assistance
> debugging that design, but on a different (somewhat larger) project,
> it doesn't work at all -- Quartus seems to just ignore the .mif file
> changes and happily produces bitstream files with all the old memory
> contents.
>
> Is there a hidden option somewhere? I have added all the .mif files as
> project files; it doesn't seem to affect this behaviour.
>
> -hpa
>
> P.S. Upgrading to Quartus 3.0 is not an option due to the changes in
> platform requirements.
>
>
> --
> <hpa@transmeta.com> at work, <hpa@zytor.com> in private!
> If you send me mail in HTML format I will assume it's spam.
> "Unix gives you enough rope to shoot yourself in the foot."
> Architectures needed: ia64 m68k mips64 ppc ppc64 s390 s390x sh v850 x86-64
Article: 60633rob d wrote: > > Here is a solution that I can't yet find a hole in. > > Put a comparator on the output of the flip flop(ff1) and call its > output "meta" > comparator indicates meta when ff1 output is just above a logic 1 min > down to just below a logic 0 max. > > now create the next flip flop > > when meta then ff2 = not ff2 (if ff1 is metastable its input was > changing) > else ff2 = ff1. > > ff2 will never be meta stable as long as timing for meta is met. > > We can now use ff1 in a state machine by creating a combinatorial > signal that reflects what ff1 is doing or trying to do. > > when meta then ff1_meta_hard = ff2 else ff1_meta_hard = ff1. > > even if you don't shoot me down I don't expect thousands of > comparators in Vertex 4! :-) You could build it and try it ? Using 4013 FF's should make triggering metastable easier, and then you can see if your fix works. If you look at Philips photos, you will see it's more a bounce, ( or a change-of-mind) effect, than a slow-edge one, so a system that relies on slow-edge detection will not help much ? The numbers do show metastable-tail settling times have been getting faster with new generations, and the local gm/capacitance must be helping that. One real-world issue with comparators, is they are MUCH slower than the two-gate regen buffer inside flip flips. Then there is the die area... - jgArticle: 60634
Hello again, I have an array of 16 10 bit coefficients, and I would like to store these in LUT on an FPGA instead of Flops. Can I do this in Xilinx and Altera devices by selecting various options say on Quartus, or can I switch on any synthesis switches or do I have to change my VHDL. Any ideas as always is greatly appreciated. Thanks BobArticle: 60635
Clyde R. Shappee <clydes@the_world.com> wrote in message news:3F6891AD.B0291535@the_world.com... > Then, please enlighten us as to how to use the block rams with Web-pack, without > using the core generator. I already have. "Have a look at the data sheet for whatever device you're targeting to see what the blockrams should be called. As an example a 256* 8 bit dual port ram in SpartanIIE is RAMB4_S8_S8, you'll have to check the data sheet for port names." And see Uwe's example above/below. Spoon feeding bit..... If you look in webpack/vhld/src/unisims/unisim_VCOMP.vhd you'll see the models for all the rams supported. RAMB4 is supported in Spartan devices (as specified in the SpartanII-E data sheet), I presume RAMB16 configurations are supported in Virtex devices. > I looked at your web page and did not see in your example projects how you did > it. Download pico2spart.zip, unzip it and look at ../SW/picocode.vhd This contains five blockram instantiations with the associated configurations containing the software for the Virtex picoblaze in a SpartanII. These Blockrams are 1024 addresses* 4 bits. For an example of a singla 256*16 ram download picoblaze.zip, then look at ../sw/ROM_form.vhd . This is a template file, but it's exactly the way the ram's instantiated in a real design. Did you ask the Xilinx apps guy "Does web-pack support blockrams?", or "Does web-pack support this ram I've generated with Coregen?" ?. As I said, it would be almost a complete waste of time for Xilinx to release web-pack if you couldn't get at the Rams. Nial. ------------------------------------------------ Nial Stewart Developments Ltd FPGA and High Speed Digital Design www.nialstewartdevelopments.co.ukArticle: 60636
thx... I found that I can use the hyper terminal to communicate with the nios through the debug port, but I wonder whether the debug port has power pin to give the mouse.Do I need to do anything to activate the power pin or not? Thank you very much San "H. Peter Anvin" <hpa@zytor.com> ??? news:bjqb6b$5la$1@cesium.transmeta.com ???... > Followup to: <bjmki8$1dam$1@justice.itsc.cuhk.edu.hk> > By author: "clsan" <clsan@cuhk.edu.hkk> > In newsgroup: comp.arch.fpga > > > > I have tried using the console uart instead of debug uart, it still can't > > work. > > > > I have connected the mouse to the board by a serial cable. Any one have any > > document that I can refer to? > > Thank you very much. > > > > Well, you need a null modem in between (the ports on the Nios card are > wired DCE; the mouse expects to be connected to a DTE.) > > Then, you need to find the exact combination of control signal outputs > that the mouse expects. This is how the mouse is powered!! > > -hpa > -- > <hpa@transmeta.com> at work, <hpa@zytor.com> in private! > If you send me mail in HTML format I will assume it's spam. > "Unix gives you enough rope to shoot yourself in the foot." > Architectures needed: ia64 m68k mips64 ppc ppc64 s390 s390x sh v850 x86-64Article: 60637
Jesse, Thanks for the tips. Turning of rubberbanding is working like a charm. Also, FYI, Altera online support verified the behavior and submitted an enhancement request. I'm happy enough. Ken "Jesse Kempa" <kempaj@yahoo.com> wrote in message news:95776079.0309171039.2e0ba177@posting.google.com... > Ken, > > This seems to be an evil of block-based schematic design. The more > traditional blocks that we'd instantiate have a fixed set of ports... > and no need to move connections around. For SOPC-type systems where > peripherals and memory are added (or removed) with a mouse click, it > becomes more difficult. > > One trick I use is to highlight an area in the schematic file > containing groups of pins & wires (connected to a block), and then cut > & paste them to a blank area of schematic (for example the SDRAM pins > as a group). Since the sets of IO for some piece of IP such as the > SDRAM controller don't change, any update you do to a Nios/SOPC system > will produce part of the schematic block with the exact same > arrangement of IO ports... after modifying my system (and having the > schematic block updated), I just select (as a group) the original IO > pins, and drag them to connect up to the schematic block. > > It seems though, that many folks are steering away from schematic > blocks because of this in complex designs, in favor of hierarchic HDL. > This approach can be taken for Nios designs as our top level (from > SOPC Builder) is in fact an HDL file, but we provide schematic > top-levels in our example designs for clarity & getting started > purposes. > > Jesse Kempa > Altera Corp. > jkempa at altera dot com > > > > "Kenneth Land" <kland1@neuralog1.com> wrote in message news:<vmf84etmtns5a1@news.supernews.com>... > > Can anyone tell me how to avoid redoing all the Nios block port connections > > whenever I edit the processor config? > > > > Whenever I add something to the Nios config in SOPC builder and update the > > block, all of my connections are broken and all I know to do is reconnect > > them one at a time manually. This takes quite awhile. > > > > Is there anyway to have the update preserve the existing connections? It > > seems to be based only on physical possition within the graphical editor > > which seems strange to me. > > > > Thanks, > > KenArticle: 60639
I'm trying to find a board consisting of a Virtex II or Virtex II Pro and a fair amount of on-board memory i.e. 256 or 512MB. The board has to be capable of outputting the data read from memory through some kind of port at very high bandwidth - GBytes/s. It also has to be attached to either a PCI interface or preferably a VMEbus. Does anyone know of any single boards, or boards that could be doubled up that would be capable of doing this?Article: 60640
Ray Andraka wrote: > > True, but those muxes are virtually useless for data path because the bit > pitch doesn't match the bit pitch of the arithmetic. Count 4-LUTs or > flip-flops instead. > > Peter Alfke wrote: > > > rickman wrote: > > > Xilinx likes to > > > pad the number since they feel they have "uber-cells" which count as > > > more than 1 each. But then again, they don't define the term "logic > > > cell", so I guess they can count them any way they want. > > > > Not really, the "padding" is exactly 12.5%, so it has been defined and > > is deterministic. > > Marketing wants to get credit for the additional multiplexers that the > > competition does not have. > > If you are a purist, just count slices and devide by 2, or multiply CLBs > > by 4 (Virtex and Spartan2) or by 8 (Virtex2 and Spartan3). That gets you > > the number of LUTs+flip-flops. > > > > Peter Alfke > > > Personally, I find marketing to frequently be irritating and annoying. When I try to get technical information from a data sheet or web site and marketing distorts or glamorizes the information so much that it interferes with my work, I find that both an insult to my intelligence and a waste of my time. I am aware of why Xilinx marketing distorts the cell counts and I don't really care by how much. I care about the fact that I have to ignore a column of data in a data sheet as marketing hype and use a calculator to get the *real* numbers. Clearly the marketing people don't think we can add and multiply ourselves. -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAXArticle: 60641
Sure- they could be conveniently stored in an SRL or RAM implementation of the LUT. Most explicitly, you'll want to instantiate the RAMs or SRLs in VHDL. You can infer this sort of thing but I don't really see why you would. Simulation models can handle the simulation stuff and instantiation makes the synthesizers job all that much easier. It's generally easier to read the code, too. Jake stenasc@yahoo.com (Bob) wrote in message news:<20540d3a.0309180006.ac62b3d@posting.google.com>... > Hello again, > > I have an array of 16 10 bit coefficients, and I would like to store > these in LUT on an FPGA instead of Flops. Can I do this in Xilinx and > Altera devices by selecting various options say on Quartus, or can I > switch on any synthesis switches or do I have to change my VHDL. Any ideas > as always is greatly appreciated. > > Thanks > BobArticle: 60642
You can enter them through configuration (that works in Xilinx as well as Altera). In Xilinx FPGAs (only!) you can also treat 10 LUTs as RAM and store and retrieve constants during operation at any time, and you can also load the LUTs serially with the help of the SRL16 option. Many ways... Peter Alfke ============================ Bob wrote: > > Hello again, > > I have an array of 16 10 bit coefficients, and I would like to store > these in LUT on an FPGA instead of Flops. Can I do this in Xilinx and > Altera devices by selecting various options say on Quartus, or can I > switch on any synthesis switches or do I have to change my VHDL. Any ideas > as always is greatly appreciated. > > Thanks > BobArticle: 60643
Rick, I will not defend the +12,5%, but I can explain it: It is the price we all pay for the intense and sometimes ruthless competition in this market. Without a bloodthirsty competitor "in our rear-view mirror", we would be gentlemanlike and give you conservative numbers. But the way it is, our marketing folks think it would throw away some really (really!) powerful features if they are not somehow represented in the numbers. Each Xilinx Logic Cell does more than an Altera LE, there can be no doubt about that. This is not an excuse (personally I agree with you), but an explanation. Peter Alfke ========================== rickman wrote: I care about the fact that I have to ignore a > column of data in a data sheet as marketing hype and use a calculator to > get the *real* numbers. Clearly the marketing people don't think we can > add and multiply ourselves. >Article: 60644
Steven Archibald wrote: > > I'm trying to find a board consisting of a Virtex II or Virtex II Pro > and a fair amount of on-board memory i.e. 256 or 512MB. The board has > to be capable of outputting the data read from memory through some > kind of port at very high bandwidth - GBytes/s. It also has to be > attached to either a PCI interface or preferably a VMEbus. Does anyone > know of any single boards, or boards that could be doubled up that > would be capable of doing this? I don't know of any boards that can do this. But out of curiosity, how many would you be using? I find I get some number of requests for high end FPGA products, but the quantities are always very small and the requirements are normally different enough that it would be hard to satisfy all of them with a single board. But I have considered trying anyway. But it would take a first customer with some reasonable quantity requirement to get over the startup hump. -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAXArticle: 60645
> > > > Now for your second issue: why did your design not work after a smart > > recompile? I can think of two possibilities: > > > > 1. There is some dangerous timing in your design (race conditions, > > asynchronous transfers without handshaking, transfers between clock > > domains without timing constraints, etc.). By re-placing and routing > > your design, a race condition that was latent may have become a > > problem. > > Yes, you are right. The clocking is kind of messy in my design, lots > of clock gating and other manipulations. So, I can accept it if the > compiled design never worked, that may even make me feel better: I > really shouldn't do those nasty things on clock. > > If I change any logics around cross-clock domain region, clock > generator (not pll), clock pll or even an inverter anywhere, I can > probably accept the fact that re-placing and fitting kill the design. > However, failing after moving a few output pins, which have no timing > constraints at all, is hard to understand. > > > Yi Hi Yi, When you change anything in your design, and you haven't back-annotated, and aren't using incremental fitting, nothing stops the compiler from changing the placement and routing a lot. In general the placement and routing will change a lot, but will still achieve similar speed and routability -- that's all that matters. There are many (millions, billions?) of placement and routing solutions to a given design with similar performance. Unless you do things to force Quartus to get a very similar place and route after a design change, your place and route will change a lot, but will be comparable on all the metrics you care about. The problem with race conditions are that there are things that you haven't told Quartus about which will make your design work or not work. Whether a given placement and routing works in the presence of race conditions will be random. VaughnArticle: 60646
Andrew Paule <lsboogy@qwest.net> wrote in message news:<6E2ab.725$VC1.32489@news.uswest.net>... > What format are they in? > Veribest, *.sbk and *.blk files.Article: 60647
"clsan" <clsan@cuhk.edu.hkk> wrote in message news:<bkbs56$sbn$1@justice.itsc.cuhk.edu.hk>... > thx... > I found that I can use the hyper terminal to communicate with the nios > through the debug port, but I wonder whether the debug port has power pin to > give the mouse.Do I need to do anything to activate the power pin or not? > > Thank you very much > > San > Hi San, You might check the dev. board schematic (installed into the Nios kit "documents/nios_stratix_1s10" folder) page 32, which goes over the RS232 connections between FPGA & DB9 connectors. We use the same circuit for both serial ports on the board. The distinction of communication vs. debug serial port is just for software purposes (where does STDOUT go...). For hardware development & interfacing purposes, both ports are functionally equivalent. You might also look at whether the 'extra' UART pins are needed for your mouse (I personally don't have any experience with serial mice!). In the most basic UART you can create with SOPC Builder, there are TXD & RXD pins only (because we are just interfacing to a PC terminal). The remaining UART pins (RTS, CTS, etc.) are optional, and can be turned on by editing the UART details for the UART(s) in your SOPC Builder system... Jesse Kempa Altera Corp. jkempa at altera dot comArticle: 60648
Hello,
I have a project in mind where I would like to caclculate the resistance
of a sensor. Because of the remainder of the circuit configuration, this
must be done using a voltage divider. If I implement this in a spartan3,
what is the fastest I can do a 16bit divide (unsigned) Obviously I can do a
shift and subtract, but I would prefer something a little faster. Any
suggestions? (I know I could go to a fast DSP but again, I would prefer to
stick with what I am most comfortable with (FPGAs). My intent is to use the
smallest spartan3 if posible.
Thanks,
Theron Hicks
Article: 60649"Eduard Nikke" <ednikke@hotmail.com> wrote in message news:<SEJ7b.12842$MJ3.93276@phobos.telenet-ops.be>... > Hi, > > Can someone help me with this issue. > > I am looking to build a serialer in a FPGA. > Base frequence is 72MHz - 7 bits serialiser - so I need a LVDS frequence of > 504MBps. > > I thought this wat not possible in a Cyclone device but just reads the app. > note and it seems to be possible. > > I have only some strong concerns because there is no timing budget and the > IOB are not DDR IOB blocks. > > Does any one has experience with this app. note ? > > Thanks, > > Eduard Hi Eduard, I believe you are referring to app note: http://www.altera.com/literature/hb/cyc/cyc_c51009.pdf What it says is correct -- Cyclone can do 640 Mb/s LVDS. More specifically, the -6 and -7 speed grades are characterized (guaranteed) to do 640 Mb/s LVDS, while the -8 (slowest) is only currently characterized for up to 550 Mb/s LVDS. Regards, Vaughn Altera
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