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I tried to connect my fpga board through a parallel cable to my PC - when i run boundary scan mode in IMPACT, it doesn't recognize the connection. I know that it worked with other PCs - i think it's dependent on the configuration of the parallel port (ECP...) - but do you know what i can do to be able to connect my board? Which configuration settings have to be done for my parallel port - are there any in the BIOS? thank you, simoneArticle: 59926
There is not refreash rate for the ram. It is static ram and does not need to be refreashed. Your 700K Hz could be lots of stuff. But I would suspect your design. Steve "Stefan Tillich" <stefanti@gmx.at> wrote in message news:fca6d5eb.0309010503.1d26bfe@posting.google.com... > Hello, > > I have a custom-made FPGA-board with a Xilinx Virtex-E (XCV-300E) > FPGA. I'm trying to measure the FPGA's power consumption over a sensor > resistor betwenn the FGPA's ground pins and the board's ground. > > The trace of the current has peaks, which occur at a rate of > approximately 700 kHz (independent whether the FPGA is configured or > not). I was wondering if those peaks may result from the refreshing > of the FPGA's BlockRAM cells. > > Is that possible and if the BlockRAM cells' refreshing is causing the > current peaks, is there a way to deactivate refreshing (as I'm not > using the RAM's) with the Xilinx WebPack (ISE 5)? > > Best regards, > Stefan TillichArticle: 59927
Hi, I have a Virtex II -5 and I would like to use the DDR registers in the IOBs. I read a few application notes involving these registers and it is always sais that the skew between two signals ouptut from DDR registers, especially if the IOBs are in the same bank, is negligible. What is negligible ? What if the IOBs are not in the same bank ? I read in a previous post that a reasonable 30% tracking could be expected between two IOBs but that this tracking was much much better when a same category of the device was considered. What is this tracking downto when considering IOBs ? Thanks, JFArticle: 59928
The bottom line is if you want a moving window averager you are going to have to have a memory that will hold the entire window of points. If your FPGA doesn't have enough memory (and it won't for 250,000x10 data) then you will need external memory. Otherwise your question is like how do you put a gallon of water into a pint sized glass.Article: 59929
"Jonathan Bromley" <jonathan.bromley@doulos.com> wrote in message news:biv4fl$17e$1$8300dec7@news.demon.co.uk... > "Paul Baxter" <pauljnospambaxter@hotnospammail.com> wrote in > message news:3f524aa7$0$254$cc9e4d1f@news.dial.pipex.com... > > > At the risk of starting a toolset discussion, I would recommend > > www.aldec.com and their ActiveHDL product. > > > > Its mainly a very user friendly simulator (still not perfect, but a lot > > friendlier than Modelsim > > Can you explain a bit more please? I've heard many people say that > Aldec is more "user-friendly", but personally (strictly personally!) > I've always found its project system and its obsessive copying of > files from place to place to be thoroughly confusing. It makes > life very easy for you if you have just an HDL design and a > single testbench file and no other tools interested in those > source files, but as soon as I try to do anything more complicated > I get hopelessly mired in its bizarre project system. (By the > way, I always detested the Aldec project machine in the older > Xilinx tools!). It certainly lays down a few directories for certain activities (such as synthesis) but I have quite a flexible arrangement of src code in several sub-dirs and library directories with no problems. It doesn't copy these files into another directory with the tool chain I have (Altera/Leonardo). The exception is that constraint files of various types would need copying (automatically) into the synthesis directory (though it can generate default ones in place). I also have had no problems with a hierarchy of testbench files/dirs for my specific combination of tools but of course each toolset combination will be different. As to user-friendliness, its been a year or so since I last looked at modelsim, but I found its user interface to have a steeper learning curve than aldecs. Having said that, as you advance, both provide similar advanced windows and tools. I guess my main comment is that aldec's felt integrated as one application whereas I always felt modelsim was a collection of loosely coupled screens that didn't work so well together. I was probably tainted by being fairly new to a grown-up simulator (Quartus doesn't really count) and appreciating the integrated approach of aldec. Although my benchmarks are out of date (18 months ago) when I did evaluate both, both aldec and Mentor put up a similar speed for a typical mix of functional and timing simulations. That left user-interface and ease of use as my deciding factor. Paul, Small world: 15 miles from Jonathon :)Article: 59930
I'm trying to make a project with 2 reconfig modules. I am using LUT's inside each module to create constant values (I need those to feed the BUS MACRO), but instead of using the signal I created to feed the bm's, the tool (PAR?) creates several "Global_Logic1"'s, and worse, some come from beyond the module frontier! Of course, when reconfiguration takes place, it stops working. Anyone ever had a problem like this? Is there a way to stop it from creating all those signals and just use the ones I tell it to use? Help!!! Thanks. =)Article: 59931
All the work Xilinx is doing with MontaVista on Linux for Virtex-II Pro (i.e. PowerPC) is published under GPL to the open source repository accessible at http://www.penguinppc.org (see "Kernel Source", linuxppc_2_4_devel) This means that all the kernel sources for the different hardware cores (peripherals) running on Virtex-II Pro are available from the repository and, thus, make it into the different distributions from various "vendors". MontaVista Linux is one of them, SuSE and ELDK are others. We (Xilinx) recommend MontaVista as its Linux partners for Virtex-II Pro FPGA based systems for various reasons, support is one of them. Said that, you are still free to do-it-yourself using the the exact same sources. There seems to exist a lot of confusion about different ports, so let me summarize: - official open source repository with the latest and greatest Virtex-II Pro (PPC) support: http://www.penguinppc.org - professional Linux distribution for Virtex-II Pro with corresponding support recommended by Xilinx: http://www.mvista.com I hope, this helps. - Peter Antti Lukats wrote: > John Williams <jwilliams@itee.uq.edu.au> wrote in message news:<bhefdn$q8g$1@bunyip.cc.uq.edu.au>... > > Hi Jon, > > > > Jon Masters wrote: > > > Hi, > > > > > > I have integrated various patches and the Xuartlite driver from John > > > Williams to get kernel 2.4.20 up and running on the development board. > [] > > Along this line - could you (or anybody else) maybe give us a run-down > > of the status of the various linux ports for the V2Pro PPC devices? I'm > > aware of the MontaVista commercial port, but am unsure about costs and > > licensing and access and so on. Someone suggested to me recently that > > the MontaVista V2Pro dev. env. was big $$$. Is it possible to work > > around this using free tools and so on? > [] > > Cheers, > > > > John > > Hi Jon and John, > > I also wanted to ask for clarification, because there is uLinux MB > and ?? Linux for PPC V2Pro, I only guess that Jon referred a real PPC > linux, not uLinux for MB running in V2Pro. > > as for Linux V2Pro - ELDK has been reported to work on V2Pro devices so > a free linux for V2Pro already exists and has been verified on real > V2Pro development boards. This report was from some avnet guy so his > work is not public ASFAIK, but already the info that ELDK works on V2Pro > (or is easy to get working) should help. > > I have only used ELDK to write some Hello.c applications and have run > them in Mvista on ML300, so have not attempted kernel compile or boot > image creation. > > anttiArticle: 59932
Hi !
Is this possible, to implement function with 4 inputs, 1 output using
also DFFE component with clk, ena and preset signals provided in one Logic
Cell ??
I mean, can code listed below be compiled to use less than 2 cells of
resources ?? I always thought, that controlling signals for latches in Logic
Cells don't increase of resource utility.
SUBDESIGN c_cell
(
clk :INPUT;
ena :INPUT;
reset :INPUT;
c_prev :INPUT;
b[0..1] :INPUT;
a :INPUT;
q :OUTPUT;
)
VARIABLE
q :DFFE;
BEGIN
q.clk = clk;
q.ena = ena;
q.clrn = reset;
q.d = c_prev $ (a&(b0$b1));
q = q;
END;
Article: 59933I'm not intimately familiar with Matlab, and I'd like to know which pieces I need for a project. Normally I get filter coefficients from ScopeFIR, and then go straight to Verilog. Sometimes I model FIR filters, mixers, etc., using behavioral Verilog, but more often than not I just go straight to the synthesizable Verilog. I can simulate this in Modelsim and do a DFT on the results using ScopeDSP. Then I can change bitwidths or filter lengths based on the results. What if I need to make a Matlab model before making synthesizable code? It seems to me that making a behavioral Verilog model is just faster and easier to use as a base for synthesizable code, but I haven't used Matlab in a while so perhaps I'm mistaken. Do you know which of the many toolboxes and add-ons I'd need to do this? I just want to make a simple fixed-point model of the DSP chain, including FIR filters and mixers. Can I do this with just the basic Matlab package? I don't even need Matlab to generate the coefficients or to make pretty block diagrams or plots. -KevinArticle: 59934
Terry wrote: > Hi, have anyone successfully installed Xilinx Foundation Series 2.1i on > Linux? > > I've tried doing so, but without success. > This is what I have done. > > cd /mnt/cdrom > wine setup.exe > > With the above command executed, a new window with the Xilinx logo > appeared and disappeared without doing any installation. > > The specs of my comp. are as follow: > Pentium 3 500 MHz > Mandrake 9.1 > > Thank you. Might this be related to the buggy Java interpreter mentioned in "Xilinx Foundation Series F2.1i + win2k" (comp.arch.fpga) /RogerL -- Roger Larsson Skellefteå SwedenArticle: 59935
"Christos" <chris_saturnNOSPAM@hotmail.com> wrote in message news:<bive8h$n0j$1@sunnews.cern.ch>... > The exponential weighted averaging cannot be used because all data into the > window have to be treated equally as all have the same importance. > If using a LPF and n is the number of samples in the window then if you want > to have an average of the last 100 values received then your filter has to > be 100 tap long. > Correct? I am asking just in case I have not understood fully how digital > filters are implemented. The truth is that I have never done it, just read > about it. Yes and no. The benifit of using the exponential weighted averaging is that the filter is a _single_ tap, not n-taps long. It is an IIR-filter structure. If you wanted to average with a FIR-filter structure then, yes you would need n taps.Article: 59936
Hi Kevin Aylward (kevin@anasoft.co.uk), you wrote: >> If I e.g. place a RAM component into MultiSim, will it simulate >> it? I.e. can I (using switches and hex displays) write on the >> RAM and then read back? Is the IC really simulated, or it's just >> a graphic symbol? >> >> If so, is there any other program that will do it? > > In principle yes. This depend on if you can figure out how to drive > multisim. [snip] Thanks for your reply. I managed to enter data into the simulated RAM via switches, and read it back correctly using hex displays. But, ain't it possible to directly load a binary file into the simulated RAM (or EPROM) to initialize its values? I'd like to design a very simple CPU, and having to load the program each time via switches is, to say the very least, tedious. Thanks! -- MikeArticle: 59937
"Maciek" <mkazula@elka.pw.edu.pl> writes: > Hi ! > Is this possible, to implement function with 4 inputs, 1 output using > also DFFE component with clk, ena and preset signals provided in one Logic > Cell ?? > I mean, can code listed below be compiled to use less than 2 cells of > resources ?? I always thought, that controlling signals for latches in Logic > Cells don't increase of resource utility. Hi Maciek, What device are you targetting? The older (10K/1K) series don't have dedicated clock enable signals, or synchronous presets/clears, so they take up one of your inputs each. This changed with later devices, eg Apex has dedicated CE inputs for the LE, and LAB wide synch clear and load signals. The data that is loaded uses the d3 input still. Looking at the Cyclone datasheet, it seems to be similar to Apex in that regard. Does that help? Cheers, Martin -- martin.j.thompson@trw.com TRW Conekt, Solihull, UK http://www.trw.com/conektArticle: 59938
"Simone Winkler" <simone.winkler@gmx.at> schrieb im Newsbeitrag news:1062440513.66052@news.liwest.at... > I tried to connect my fpga board through a parallel cable to my PC - when i > run boundary scan mode in IMPACT, it doesn't recognize the connection. > I know that it worked with other PCs - i think it's dependent on the > configuration of the parallel port (ECP...) - but do you know what i can do > to be able to connect my board? Which configuration settings have to be done > for my parallel port - are there any in the BIOS? > > thank you, > > simone > > We did a lot of work on parallel port based system, conclusion is that setting the parallel port to ECP or EPP+ECP gives most problems. What kind of download cable is in use??? (only have experience with Xilinx DLC5) Just trie the other settings in PC BIOS setup (go into BIOS setup at boot time, before system startup). So try all other mode settings in following order: 1.) SPP (standard parallel port, 8-bit out/4-bit in) 2.) PS2 (also called enhanced or bi-directional, software controlled 8-bit out/8-bit in ) 3.) EPP(enhanced parallel port, hardware controlled 8-bit out/8-bit in ) All three modes should be compatible with Xilinx parallel download cable (DLC5). There may be a mode called EPP+ECP, but in most cases it gives more problems as ECP mode. good luck! with best regards, Peter Seng ############################# SENG digitale Systeme GmbH Im Bruckwasen 35 D 73037 Göppingen Germany tel +7161-75245 fax +7161-72965 eMail p.seng@seng.de net http://www.seng.de #############################Article: 59939
"Paul Baxter" <pauljnospambaxter@hotnospammail.com> wrote in message news:3f539d0d$0$248$cc9e4d1f@news.dial.pipex.com... > > "Jonathan Bromley" <jonathan.bromley@doulos.com> wrote in message > news:biv4fl$17e$1$8300dec7@news.demon.co.uk... > > "Paul Baxter" <pauljnospambaxter@hotnospammail.com> wrote in > > message news:3f524aa7$0$254$cc9e4d1f@news.dial.pipex.com... > > > > > At the risk of starting a toolset discussion, I would recommend > > > www.aldec.com and their ActiveHDL product. [...] > It certainly lays down a few directories for certain activities (such as > synthesis) but I have quite a flexible arrangement of src code in several > sub-dirs and library directories with no problems. It doesn't copy these > files into another directory with the tool chain I have (Altera/Leonardo). > The exception is that constraint files of various types would need copying > (automatically) into the synthesis directory (though it can generate default > ones in place). > > I also have had no problems with a hierarchy of testbench files/dirs for my > specific combination of tools but of course each toolset combination will be > different. > > As to user-friendliness, its been a year or so since I last looked at > modelsim, but I found its user interface to have a steeper learning curve > than aldecs. Having said that, as you advance, both provide similar advanced > windows and tools. I guess my main comment is that aldec's felt integrated > as one application whereas I always felt modelsim was a collection of > loosely coupled screens that didn't work so well together. > > Although my benchmarks are out of date (18 months ago) when I did evaluate > both, both aldec and Mentor put up a similar speed for a typical mix of > functional and timing simulations. That left user-interface and ease of use > as my deciding factor. Thanks for your comments. Obviously time for me to start using Aldec more regularly, so I get a chance to learn to love it ... > Paul, Small world: 15 miles from Jonathon :) So, hi-tech is alive and well in southern England! -- Jonathan Bromley, Consultant DOULOS - Developing Design Know-how VHDL * Verilog * SystemC * Perl * Tcl/Tk * Verification * Project Services Doulos Ltd. Church Hatch, 22 Market Place, Ringwood, Hampshire, BH24 1AW, UK Tel: +44 (0)1425 471223 mail: jonathan.bromley@doulos.com Fax: +44 (0)1425 471573 Web: http://www.doulos.com The contents of this message may contain personal views which are not the views of Doulos Ltd., unless specifically stated.Article: 59940
Please does anyone have experience with EDK 3.2 for embedded design? I am trying to make my microblaze processor to be interrupted when I push a certain input button. I can make Timer-interrupt work, but I cant make and outside stimuli to interrupt the processor. Anyone know how to do this? I have added a interrupt-controller to the opb bus, and set its irq to the same net as the Microblaze Interrupt. JohnArticle: 59941
For the moment I have used a process similar to the one you describe. The circular buffer is a SR and the result of the X-Y is fed to an accumulator using signed numbers. I think it works very well (the clk has to be min 20 ns, otherwise it goes unstable/setup violations, but this is not a problem as the real clk will be much slower). On the other hand this is going to be used only up to ~10 ms of data (250 values). The processes that will go up to 100s will take an average of 8 values and store that value to the external memory. In that way the data are minimised by a factor of 8 and the system error is negligible. The SRAM that was found can be used in the architecture of 1M x 72bit, so 8 accesses in parallel times two in 40 us seems to be more than ok One problem now is how to implement this! my experience do go that far! You've said something about instantiating a processor (I guess something like NIOS), are you sure that this will not complicate things more? Is there something ready to implement a circular buffer to the external ram? The second problem, and the reason why I asked for help in this group, is that those SRAMS are quite expensive and having in mind that 2000 of them will be needed, it increases the cost significantly. So they are pressing me to find some other way to implement it. (usual stuff: we want the pie and the dog fed!) Ray has given me the idea of the CIC (he will be acknowledged for that in my thesis, as well as all the rest which took the time to answer) but I still haven't figured how it is working! Soon I hope, so that I can figure out if I can use it. And answering your question about LHC, this system is for machine protection and it is called Beam Loss Monitor. The superconducting magnets have to be prevented from quenching by the particles showers hitting them as some particles are lost from the trajectory. Inside the tunnel some Ionisation Chambers are installed (3600) and they give an amplitude proportional to the particle rate passing through them. This current is fed to a CFC (Current to Frequency Converter) and a counter is measuring the frequency. The counter data, as well as some status, CRC etc from 16 chambers are sent through an optical link to the surface for processing. And here is where I come, I have to design the threshold comparator for this. Samples at 40us is enough as it is ~half a LHC cycle and maybe it will be increased to 89us (~11KHz)which is one cycle. Just imagine what would be my problems if 40MHz was used and I had to go up to 100s of data!! Christos "Kolja Sulimma" <news@sulimma.de> wrote in message news:b890a7a.0309011019.757aa770@posting.google.com... > christos.zamantzas@cern.ch wrote: > > The final system will have to keep 10 moving sums with the largest being > > 250,000 (8-bit) values for each of the 16 independent input channels. > and > >the sample rate is slow enough: 25 KHz > > This is easy todo, even without the CIC Filters suggested by Ray > Andraka: > In external memory you keep a circular buffer of 16x250000 samples. > You keep your 160 Sums inside of your FPGA. To update them you do the > following: > For each channel > input the new sample X > write new sample to its external ram location in a circular buffer > for each moving sum of this channel > read the value Y that "falls of" the sum from external ram > add X-Y to the moving sum inside the FPGA. > > This requires 16 writes and 160 reads to external memory with a > resulting bandwidth of 4.400.000 memory accesses per seconds. > If the values are stored in memory with the right alignment you can do > 4 accesses in parallel reducing the bandwidth to 1.100.000 accesses > per second. > > Maybe you should instantiate a processor in you fpga and use that to > implement this. > > OT: > What are you doing at LHC that has a sample rate of 25kHZ? > > Kolja Sulimma > Frankfurt > What are youArticle: 59942
Peter, Austin! Nobody can help me? Luiz CarlosArticle: 59943
Assume you nailed down the MAC for calculating one element, to calculate one row at a time, you just add a 10:1 mux before the MAC and select inputs for the next element after the current element is done and the accumulator is cleared. A counter or a simple state machine can be used to control the mux select signal. This will take at least 10 times longer to get all 100 elements. Jim Wu jimwu88NOOOSPAM@yahoo.com http://www.geocities.com/jimwu88/chips "walala" <mizhael@yahoo.com> wrote in message news:<bipbje$51c$1@mozo.cc.purdue.edu>... > Dear all, > > I want to design an arithmatic datapath unit for digital signal processing > using VHDL and/or Verilog. > > The input are 5 elements(either sequential or parallel) each having 8 bits. > It needs to multiply each of these 5 inputs with a predefined constant > matrix(10x10, floating point scaled and round to integer). The output will > be a 10x10 matrix summing the above five matrices up, each element having 12 > bits). So for each element of the matrix, I can have a MAC unit. The > internal computation will be 16 bits. > > Hence for each 5 inputs x1, x2, x3, x4, x5, the output matrix > > Y=x1*C1+x2*C2+x3*C3+x4*C4+x5*C5 where Y, C1, C2, C3, C4, C5 are matrices; > > If I put an MAC for each element, I will have a purely parallel > architecture, but I need 100 16bits MAC units, which will be too resource > consuming. > > I am considering to make a parallel-serial architecture, at each time, it > outputs one row, which will be 10x12 bits... so the output will be > row-by-row. > > I also need to consider to streamlize the datapath operation. Since there > will be a stream of 5 elements input in a non-stop fashion, the output will > also be non-stop streaming. So after one row is outputted, that row can be > used for computation/storage of the results for the next 5 input elements. > > I am ok so far in thinking... but further thinking makes me confused and > perplexed... how to do sequential timing control(how to what to do at which > cycle)? do I need to pipelining? how to design the architecture? I mean, I > know pipelining theoratically from one semester course, but now I am going > to implement one, I am totally lost... > > Finally, how to program this? Is there any examples for this? > > Please help me! > > Thanks a lot, > > -WalalaArticle: 59944
"John T." <john@dat.com> wrote in message news:<bj1l57$plr$1@news.net.uni-c.dk>... > Please does anyone have experience with EDK 3.2 for embedded design? > I am trying to make my microblaze processor to be interrupted when I push a > certain input button. I can make Timer-interrupt work, but I cant make and > outside stimuli to interrupt the processor. Anyone know how to do this? > I have added a interrupt-controller to the opb bus, and set its irq to the > same net as the Microblaze Interrupt. > > John simple external ints should work as well (as timer ints), well connecting a push-button directly to int net probably isnt the best idea, there will always be some bouncing :( just a note: if you have multiple interrupt sources then you have to assign to them all different names and write those names with "&" concatenated in the edit core dialog - this was something that did take long time for me to understand (until I found that is in the IP core manual, not INTC pdf but general IP cores document). just check that the int lines are connected in the system.vhd file and that the interrupt handler procedures are assigned correctly, then when you enable int it should come? antti http://www.graphord.com/forumArticle: 59945
> Hi Maciek,
>
> What device are you targetting?
>
> The older (10K/1K) series don't have dedicated clock enable signals,
> or synchronous presets/clears, so they take up one of your inputs
> each.
>
> This changed with later devices, eg Apex has dedicated CE inputs for
> the LE, and LAB wide synch clear and load signals. The data that is
> loaded uses the d3 input still.
>
> Looking at the Cyclone datasheet, it seems to be similar to Apex in
> that regard.
>
> Does that help?
>
> Cheers,
> Martin
Hi Martin!
Thank You for Your suggestion about checking the targeting device. I
still don't know how to use AHDL to take advantage of dedicated control
inputs in Apex devices, but I think I will solve this problem soon.
Regards,
Maciek
Article: 59946Luiz, The input comparator is not characterized as a general purpose comparator, but it actually is pretty useful in that way. There is some samll offset voltage from the mis-match between the differential pairs (both nmos and cmos to cover the voltage range). I do not know what this offset might be, but I suspect it is less than a few tens of millivolts, worst case from the transistor models. The comparator will switch as soon as the voltage is greater than the offset (we spec 100 mV for speed reasons, not because it needs > 100 mv to function). So with 50 mV it will switch, just more slowly than if it was 100 mV. Austin Luiz Carlos wrote: > Peter, Austin! > Nobody can help me? > > Luiz CarlosArticle: 59947
Uwe, If the setup is violated, there may be a runt pulse. It will not stall, as soon as the next set of control signals comes along, it will operate normally again. Austin Uwe Bonnes wrote: > Peter Alfke <peter@xilinx.com> wrote: > : Click at > : http://www.xilinx.com/xcell/xl24/xl24_20.pdf > > : This circuit allows totally asynchronous selection between two clock sources. > : But remember: both clock must be wiggling (however slowly). You cannot > : use this circuit to enable/disable a clock, which is actually a far > : simpler problem. > : The BUFGMUX in Virtex is not quite this clever, it has a set-up time > : requirement on the S control input. :-( > > Peter, > > what happens if this setup time is violated? Will the BUFGMUX stall (no more > output clock until some reset), will it produce a runt ( some clock pulse > smaller than any of both input clocks) or will it switch clocks only > delayed? I didn't find anything in the datasheet. > > Nye > -- > Uwe Bonnes bon@elektron.ikp.physik.tu-darmstadt.de > > Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt > --------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------Article: 59948
Jay, Better in a relative sense: it does not have a setup time requirement (Peter's circuit). But, Peter's circuit does not match all delays, and keep the skew to 0 as part of the DCM feedback loop, either. Austin Jay wrote: > Peter, > > So you mean this circuit is better than the BUFGMUX? > > "Peter Alfke" <peter@xilinx.com> ??????:3F4E7B2D.CFBD1D0D@xilinx.com... > > Click at > > http://www.xilinx.com/xcell/xl24/xl24_20.pdf > > > > This circuit allows totally asynchronous selection between two clock > sources. > > But remember: both clock must be wiggling (however slowly). You cannot > > use this circuit to enable/disable a clock, which is actually a far > > simpler problem. > > The BUFGMUX in Virtex is not quite this clever, it has a set-up time > > requirement on the S control input. :-( > > Glad that someone found this old tidbit useful... > > Peter Alfke > > ============================= > > Marten wrote: > > > > > > "David Lamb" <gretzteam_nospam@yahoo.com> wrote in message > > > news:bilfne$sel$1@home.itg.ti.com... > > > > Hi all, > > > > I have a vhdl component with a "clock_in" input. Depending on the mode > of > > > > operation, I want to switch between two different clock signals. I > will > > > > never switch on the fly though. Can I use a mux in front of the > clock_in > > > > input? I'm afraid it might glitch. > > > > Thanks > > > > David > > > > > > > > > > > > > > David, > > > > > > Do a query for 'clock sources' in the category 'XCELL Journals' on the > > > Xilinx web site. This will provide you with a link called 'XCELL 24 - > > > Trouble-Free Switching Between Clocks (Q1 97)', which, in turn will lead > you > > > to xl24_20.pdf, a neat little circuit that hopefully will ease your > worries > > > :) > > > > > > Keep in mind that whatever you put in the clock path will affect the > setup > > > and hold time requirements for the particular component. > > > > > > Take care, > > > > > > Marten > > > > > > ] remove the obvious to repy by e-mail [Article: 59949
Håkon, You are welcome. It is wonderful to hear from folks who are doing what I used to do for 23 years (design telecoms equipment) and using the parts I helped design. It is your feedback that leads to future feature enhancements, Austin "Håkon Lislebø" wrote: > Yes I use a 2V40 in that application (155Mb clock data switch/mux), and I > have not found a simple way to multiplex the clock quality logic. We ended > up with a combination of SW logic and HW logic for supervising of the DCM's. > It works, but the SW guys dont like the extra lines of code! A picoBlaze is > interesting for my next project, I'll take a deeper look at that one. Thank > you for the conversation! > > Hakon Lislebo > > "Austin Lesea" <Austin.Lesea@xilinx.com> wrote in message > news:3F4B78A5.6E3FEED8@xilinx.com... > > Håkon, > > > > Well, sounds like you really do have a demanding application, and it > therefore > > it needs a well thought out and debugged solution. I would hate to try to > match > > our system design skills with yours (and get it wrong) so the cheapest and > best > > way to address thius is still using LUTs, SRL16s, and FFs. > > > > And what are you using, a 2V40? We are still talking about less than a > few > > hundred CLB's, which is a tiny number in a 2V1000 or larger. If it is a > 2V40, > > or a 2V80, I can see your point, as it might get a bit crowded. > > > > Is it possible to multiplex your clock quality logic among multiple DCMs? > Sort > > of a reset controller? Or use a picoBlaze to control all DCM resets? It > is not > > a function that needs the speed of the fabric, so one can replace it with > > software, and a soft controller core like the picoBlaze. Might be an > > advantageos trade-off. > > > > Austin
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