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Chen, For University Support: MIT is hosting a Xilinx users group. This will be an unmediated forum where you can exchange curriculum and project ideas with your peers around the world as well as find solutions to problems. To subscribe send email with subscribe in the subject line to: xilinxusers-admin@mit.edu , once you have subscribed send subsequent comments etc. to: xilinxusers@mit.edu . By subscribing, you will get a digest of the email traffic sent to you. The Xilinx University Program thanks MIT and specifically Andrew Huang for hosting this newsgroup. (From our website as our hotline does not support students), Austin Chen Bin wrote: > Hi, > I am a colledge student,one of my dreams is to design a 16-bit CPU,it has > some basic functions,such as arithmatic and MMU and so on. > > But I don't have any idea how to get it.Can you give some suggestions about > it? > > I mean,what steps should I take to obtain this dream,and at each step,which > book should I read,how long will I get the dream? > > Any help appreciated!! > > This is a cry from a puzzled student for your help. > > Chen BinArticle: 59951
JF (is this a new thing in France? All of the Jean-whatevers going by their intitals? Seems to be popular for ex-patriot French Engineers here in silicon valley to suddenly go from Jean-Louis or Jean-Reynard to JL or JR .... it isn't Texas you know...and I didn't think the French were too enamored of Bush....) The skew from one IOB to an adjacent IOB is less than 20 ps. The skew across the entire top, bottom, left or right edges, can be found in the source synchronous section of the data sheet, or by probing the timing of the paths in FPGA Editor. If you use a flip chip package, we also have "flight time" maps of the delay from the pad to the pin, so that you may design your pcb to remove this skew as well. For designs using DDR avbove 600 Mbs, one has to use both the IOB to IOB skew, and the pad to pin flight time information to keep your timing budget as tight as possible. Bon Chance, Austin jean-francois hasson wrote: > Hi, > > I have a Virtex II -5 and I would like to use the DDR registers in the IOBs. > I read a few application notes involving these registers and it is always > sais that the skew between two signals ouptut from DDR registers, especially > if the IOBs are in the same bank, is negligible. What is negligible ? What > if the IOBs are not in the same bank ? I read in a previous post that a > reasonable 30% tracking could be expected between two IOBs but that this > tracking was much much better when a same category of the device was > considered. What is this tracking downto when considering IOBs ? > > Thanks, > > JFArticle: 59952
"Luiz Carlos" <oen_br@yahoo.com.br> wrote in message news:8471ba54.0309020217.567a3f03@posting.google.com... > Peter, Austin! > Nobody can help me? > > Luiz Carlos Maybe they can shed some light, but using a digital circuit for analog functions is like trying to use a car as a tractor. It might work but it sure as heck wasn't designed to plow fields - you're bound to have problems. Since digital logic has fixed thresholds and large noise margins (difference beteween Vih and Vil) there's no need for the designers to be detailed about keeping the internal noise to the sub-millivolt level when there's so much activity in the adjacent I/O cells or internal logic. The Vref pins on the bank are designed for I/O signalling where the threshold does not change so dynamically changing this value dramatically can have unforseen effects. LVDS signalling produces the best differential capability, allowing a dynamic "Vref" for your doomed analog comparator in the digital device but the noise margin for LVDS is still a rather large value. If you put nothing else in the FPGA, I imagine you could get good noise-free results with a consistent transition (though subject to an offset voltage in the many 10s of millivolts). My guess is you want more than just the analog comparator in there. Consider using... an analog comparator! - John_HArticle: 59953
Well, if you have the tools, why don't you have a look at the results? Just use the Floorplanner or the FPGA Editor. If nothing helps, try a more recent version. You may wish to have a look at the xilinx home page. BR Chris Kload wrote: > Hi all, > > Lets assume I'm using a Xilinx Virtex device and I have a VHDL design > that includes the following > > a<=b+c; > > Will the design tools (I happen to be using Foundation 2.1i) infer a > "simple" adder or will the tools automatically infer an adder that uses > the dedicated carry look ahead logic?? Will that logic be placed > appropriately (i.e. like the ACC and ADD standard components that use > the RLOC constraint)? > > Thanks for your help. >Article: 59954
Hi all,
I'm working with Quartus II 2.2 sp2 and my target fpga is APEX20KE.
I have described a latch in my VHDL code with an enable signal, something
like this
library ieee;
use ieee.std_logic_1164.all;
entity my_lat is
port (d : in std_logic;
en : in std_logic;
clk : in std_logic;
q : out std_logic);
end my_lat;
architecture rtl of my_lat is
signal next_q, q_local : std_logic;
begin
next_q <= d when (en='1') else q_local;
q_local <= next_q when (clk='1') else q_local;
q <= q_local;
end rtl;
Quartus II synthesizes this code mapping the latch on a lut with the
following equation:
--A1L5 is q_local~1 at LC3_1_S1
--operation mode is normal
A1L5 = clk & (en & d # !en & A1L5) # !clk & A1L5;
The gate level backannotated simulation produces oscillation on q output.
Actually this what I see in a more complex design (this is only an example).
Looking the equations it seems to be all ok, even if SDF extracted doesn't
contain any TIMING CHECKS for combinatorial part of a LE, nevertheless the
equation describes a combinatorial loop.
(CELL
(CELLTYPE "apex20ke_asynch_lcell" )
(INSTANCE q_local_a16.lecomb )
(DELAY
(ABSOLUTE
(PORT dataa (3754:3754:3754) (3754:3754:3754) )
(PORT datab (11093:11093:11093) (11093:11093:11093) )
(PORT datac (3754:3754:3754) (3754:3754:3754) )
(PORT datad (274:274:274) (274:274:274) )
(IOPATH dataa combout (800:800:800) (800:800:800) )
(IOPATH datab combout (783:783:783) (783:783:783) )
(IOPATH datac combout (726:726:726) (726:726:726) )
(IOPATH datad combout (335:335:335) (335:335:335) )
)
)
)
Any suggestion?
Thanks in advance,
Andrea
Article: 59955Terry wrote: > Hi, have anyone successfully installed Xilinx Foundation Series 2.1i > on Linux? > > I've tried doing so, but without success. > This is what I have done. > > cd /mnt/cdrom > wine setup.exe > I can guarantee it will work with VMWare. But, this requires a full Windows (your favorite flavor here) OS to be installed as a guest to the Linux system. And, there is no longer a free version of VMWare. They do have demos, however. JonArticle: 59956
Thanassis Roubies wrote: >Problem Description: >--------------------------------------- >I have created the parallel cable III from the design that is online >at the xilinx website. i am trying to configure my xc95108 but i cant >and i receive an error message > >Error Message: >--------------------------------------- >Error: impact:1210 - '1':Boundary scan chain test failed at bit >position '1'. a problem may exist in the hardware configuration..... > >My parallel cable is very short,and my parallel port works perfectly >fine,since the printer is working. i don't have the cable over a >monitor. i am in despair. i don't know what to do. if i don't program >my CPLD i can't go on. could anyone help? > > A classic problem. I have seen this many times. First, check the BIOS settings of the parallel port to make sure it is set the way you want it. (I think SPP may be the most reliable mode for the parallel cable.) Second, you may need to switch motherboards, use a different PC, use a plug-in parallel card, etc. There are some motherboard parallel port chips that simply do NOT work properly with the parallel cable III, due to some of the level translating features it has. I have had this happen with several systems over the years. I've got some stable systems that work fine with the P. C. III, but I can't really tell you what it is about them that makes them work better. SMC chips seem to work best, one-chip mothrboards seem to have the most problems. JonArticle: 59957
Simone, You may also want to take a look at soln 15742. It covers basic cable connection debugging tips. http://support.xilinx.com/xlnx/xil_ans_display.jsp?iLanguageID=1&iCountryID=1&getPagePath=15742 If this solution doesn't resolve your connection issue, please do contact the Xilinx supports. http://support.xilinx.com/support/techsup/tappinfo.htm Regards, Wei Xilinx Applications Simone Winkler wrote: > I tried to connect my fpga board through a parallel cable to my PC - when i > run boundary scan mode in IMPACT, it doesn't recognize the connection. > I know that it worked with other PCs - i think it's dependent on the > configuration of the parallel port (ECP...) - but do you know what i can do > to be able to connect my board? Which configuration settings have to be done > for my parallel port - are there any in the BIOS? > > thank you, > > simone > >Article: 59959
Hi, Michael! Michael wrote: > Hi Kevin Aylward (kevin@anasoft.co.uk), you wrote: > > >>>If I e.g. place a RAM component into MultiSim, will it simulate >>>it? I.e. can I (using switches and hex displays) write on the >>>RAM and then read back? Is the IC really simulated, or it's just >>>a graphic symbol? >>> >>>If so, is there any other program that will do it? >>> >>In principle yes. This depend on if you can figure out how to drive >>multisim. >> > > [snip] > > Thanks for your reply. I managed to enter data into the simulated > RAM via switches, and read it back correctly using hex displays. > > But, ain't it possible to directly load a binary file into the > simulated RAM (or EPROM) to initialize its values? > > I'd like to design a very simple CPU, and having to load the program > each time via switches is, to say the very least, tedious. > > Thanks! > -- > Mike You might want to take a peek at http://www.xs4all.nl/~averschu/idass/ Instead of having to load RAM's by throwing (virtual) switches, you can just enter data by typing away - saves and loads Intel HEX as well. Greetings and hav vun, Ad VerschuerenArticle: 59960
Jonathan Bromley wrote: > Can you explain a bit more please? I've heard many people say that > Aldec is more "user-friendly", but personally (strictly personally!) > I've always found its project system and its obsessive copying of > files from place to place to be thoroughly confusing. I agree with you on Aldec projects, but I don't get along with Modelsim's TCL Project Manager either. My sim process is to cvs update all the project files to a local directory, run an emacs-vhdl-mode make, and fire off a vsim -do from a shell. -- Mike Treseler.Article: 59961
Hi all, I have done some other investigations on the problem and I have a theory. As I already mentioned in the previous message the latch has been synthesized using a LUT of a LE. The SDF characterizes the lecomb by PORT and IOPATH statements; no TIMING CHECK is present. For simplicity consider EN signal statically at 1. If the D input has a transition just before the falling edge of CLK (< PORT(D) delay) an oscilation occurs. The explanation is the following: The D transition that occurs with CLK=1 throws a transition on Q (=LE's combout) after PORT(D)+IOPATH(D) delay. Neverthless the CLK causes the latch to hold Q value at CLK transition time after PORT(CLK)+IOPATH(CLK). This triggers the oscillation. Probably the situation is similar to setup time violation, but Quartus II models the latch via a LUT an surely there is no trace of this trouble in the static analysis. Thanks, Andrea "Andrea" <NSP_g.cocchi@NSP_swapp-eng.it> ha scritto nel messaggio news:bj2k4f$5pf$1@lacerta.tiscalinet.it... > Hi all, > > I'm working with Quartus II 2.2 sp2 and my target fpga is APEX20KE. > I have described a latch in my VHDL code with an enable signal, something > like this > > library ieee; > use ieee.std_logic_1164.all; > > entity my_lat is > port (d : in std_logic; > en : in std_logic; > clk : in std_logic; > q : out std_logic); > end my_lat; > > architecture rtl of my_lat is > signal next_q, q_local : std_logic; > begin > next_q <= d when (en='1') else q_local; > q_local <= next_q when (clk='1') else q_local; > q <= q_local; > end rtl; > > Quartus II synthesizes this code mapping the latch on a lut with the > following equation: > > --A1L5 is q_local~1 at LC3_1_S1 > --operation mode is normal > A1L5 = clk & (en & d # !en & A1L5) # !clk & A1L5; > > The gate level backannotated simulation produces oscillation on q output. > Actually this what I see in a more complex design (this is only an example). > Looking the equations it seems to be all ok, even if SDF extracted doesn't > contain any TIMING CHECKS for combinatorial part of a LE, nevertheless the > equation describes a combinatorial loop. > > (CELL > (CELLTYPE "apex20ke_asynch_lcell" ) > (INSTANCE q_local_a16.lecomb ) > (DELAY > (ABSOLUTE > (PORT dataa (3754:3754:3754) (3754:3754:3754) ) > (PORT datab (11093:11093:11093) (11093:11093:11093) ) > (PORT datac (3754:3754:3754) (3754:3754:3754) ) > (PORT datad (274:274:274) (274:274:274) ) > (IOPATH dataa combout (800:800:800) (800:800:800) ) > (IOPATH datab combout (783:783:783) (783:783:783) ) > (IOPATH datac combout (726:726:726) (726:726:726) ) > (IOPATH datad combout (335:335:335) (335:335:335) ) > ) > ) > ) > > > Any suggestion? > > Thanks in advance, > Andrea > >Article: 59962
Hi Luiz, I'll try to comment. > The manual says: > Vout = low, if Vin <= Vref - 0.5 > Vout = high, if Vin >= Vref + 0.5 > But, what does hapen if Vin=Vref+0.1? I see other numbers in document "Spartan-II:DC and Switching Characteristics" (table on pg.3). Inequations should be as following: Vout = low, if Vin <= Vref - 0.1 Vout = high, if Vin >= Vref + 0.1(volts, here and below) > Does Vout still go high? Suppose Vin=Vref+0.02 in your question to match corrected inequations. Vout will not go high. As you are breaking the logical input level requirements hence the input buffer will behave like non-linear differential amplifier (so it is always possible to find such Vin value on DC input-to-output transfer curve that Vout will stand between Vhigh and Vlow, say Vout=(Vhigh+Vlow)/2+Voffset and this point will be stable if Vin is stable). > I think this is related to the metastability problem, but I preferred > to start a new thread. I don't think this is about metastability unless you bring positive feedback to input buffer. This is only my opinion, I can't verify it with measurements, unfortunately. Regards, AndreyArticle: 59963
The problem with the multiplier block approach is that the
construction is predicated on the specific coefficients. As
a result it is considerably harder to use for an arbitrary
set of coefficients. It may reduce area over a straight FIR
filter running at the same clocks per sample, but at a
considerable cost in design time and flexibility. You also
give up regularity in the structure, which may reduce the
overall performance. Essentially what the block multiplier
and distributed arithmetic approaches are is a rearrangement
of the bitwise product terms. The mutliplier block takes
advantage of duplicate terms by adding the inputs before
they are multiplied by the term.
Michael Spencer wrote:
> Hello,
>
> Has anyone compared FPGA implementations of full-rate
> digital FIR filters based on the use of Multiplier Blocks
> vs. traditional FIRs with constant coefficient
> multipliers? By full rate, I mean: one output result per
> clock cycle and no interpolation or decimation.
>
> For anyone not familiar, a multiplier block is a network
> of shifters and adders that performs multiplications by
> several coefficients efficiently by exploiting common
> sub-expressions. The multiplier block can be exploited in
> FIR filters by transposing the standard filter so that the
> products of all the coefficients with the current
> input-sample are required simultaneously.
>
> Also, by representing the coefficients in the
> Canonical-Signed-Digit number system (a small number of
> +1 and -1’s) along common sub-expression sharing the
> multiplier block can get even smaller.
>
> For example, the multiplier block for a 100 tap FIR filter
> (fp=0.10 and fs=0.12) can be realized with only 61 adds
> (zero explicit multiplications). See filter example #4 in
> “FIR Filter Synthesis Algorithms for Minimizing the Delay
> and the Number of Adders,”
> http://ics.kaist.ac.kr/~dk/papers/TCAD2001.pdf
> If the adder depth is constrained to a maximum of four,
> then the authors’ algorithm can do the multiplier block in
> 69 additions.
>
> It would seem that this approach would be very efficient
> in a target such as the Xilinx Spartan-IIE (with no
> dedicated multipliers).
>
> Another question: If we only need one result per K clock
> periods (K ~= 1000 for audio applications), could a
> multiplier block approach realized with, say, bit-serial
> addition be more efficient than some other approach such
> as distributed arithmetic?
>
> Comments welcome. Thanks.
>
> -Michael
> ______________________
> Michael E. Spencer, Ph.D.
> President
> Signal Processing Solutions, Inc.
> Web: http://www.spsolutions.com
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin
Franklin, 1759
Article: 59964> The processes that will go up to 100s will take an average of 8 values and > store that value to the external memory. In that way the data are minimised > by a factor of 8 and the system error is negligible. > The SRAM that was found can be used in the architecture of 1M x 72bit, so 8 > accesses in parallel times two in 40 us seems to be more than ok > One problem now is how to implement this! my experience do go that far! > You've said something about instantiating a processor (I guess something > like NIOS), are you sure that this will not complicate things more? > Is there something ready to implement a circular buffer to the external ram? > > The second problem, and the reason why I asked for help in this group, is > that those SRAMS are quite expensive and having in mind that 2000 of them > will be needed, it increases the cost significantly. So they are pressing me > to find some other way to implement it. (usual stuff: we want the pie and > the dog fed!) I don't understand why you need 2000 SRAMs. 25 KHz x 16 x 100 = 40 MB or 8 SRAMs.Article: 59965
Hi Philip,
Thanks for your post, those pictures were certainly very
interesting! What parts did you use? I notice they seem to disagree
with Peter's quote that "Metastability just affects the delay on the Q
output.". I wonder, Peter, if Xilinx FFs behave differently from the
ones in Philip's photos? (Other than speed, of course.) I must admit,
one reason I posted was that I found hard to believe that any FF
wouldn't show runt pulses, or funny output levels, albeit for brief
periods of time, during metastable events.
It's also interesting that the straight shift register isn't
necessarily the best way to reduce metastability effects. That was
what I suspected and was another reason behind my post. I agree that
the 'four paths out of phase' solution is better, and preserves the
sampling resolution. Often the sampling resolution needs to be
preserved, which was why I didn't present an 'enabled every third or
fourth go' type circuit.
Anyway, thanks to all for their thoughts, it's an interesting
topic!
cheers, Syms.
Article: 59966Symon, I think the sampling o-scope shots agree perfectly with what Peter said. Runt pulse, and funny levels are the easiest metastable results to catch, as they are just before the long unknown settling time behavior that is so vexing to designers. It also makes a difference where you look: a master-slave FF reduces the duration of the unknown transistion over a simple FF without a slave to help "sharpen up" the transistions. Austin Symon wrote: > Hi Philip, > Thanks for your post, those pictures were certainly very > interesting! What parts did you use? I notice they seem to disagree > with Peter's quote that "Metastability just affects the delay on the Q > output.". I wonder, Peter, if Xilinx FFs behave differently from the > ones in Philip's photos? (Other than speed, of course.) I must admit, > one reason I posted was that I found hard to believe that any FF > wouldn't show runt pulses, or funny output levels, albeit for brief > periods of time, during metastable events. > It's also interesting that the straight shift register isn't > necessarily the best way to reduce metastability effects. That was > what I suspected and was another reason behind my post. I agree that > the 'four paths out of phase' solution is better, and preserves the > sampling resolution. Often the sampling resolution needs to be > preserved, which was why I didn't present an 'enabled every third or > fourth go' type circuit. > Anyway, thanks to all for their thoughts, it's an interesting > topic! > cheers, Syms.Article: 59967
"Maciek" <mkazula@elka.pw.edu.pl> wrote in message news:<bj0c04$vn2$1@julia.coi.pw.edu.pl>... > Hi ! > Is this possible, to implement function with 4 inputs, 1 output using > also DFFE component with clk, ena and preset signals provided in one Logic > Cell ?? > I mean, can code listed below be compiled to use less than 2 cells of > resources ?? I always thought, that controlling signals for latches in Logic > Cells don't increase of resource utility. > SUBDESIGN c_cell > ( > clk :INPUT; > ena :INPUT; > reset :INPUT; > c_prev :INPUT; > b[0..1] :INPUT; > a :INPUT; > q :OUTPUT; > ) > > VARIABLE > q :DFFE; > BEGIN > q.clk = clk; > q.ena = ena; > q.clrn = reset; > q.d = c_prev $ (a&(b0$b1)); > q = q; > END; Hi Maciek, Change the code as follows : VARIABLE my_reg :DFFE; Instead of VARIABLE q :DFFE; my_reg.clk = clk; .... .... q = my_reg.q and it should work (i.e. fit in one Logic Cell).. I checked it for the APEX, Stratix and Cyclone families. - Subroto Datta Altera Corp.Article: 59968
Bob Perlman wrote: > > Whoever said, "If you require noise to shift you out of metastability, > then the people who argue that more noise will get you out quicker > could then be right," could you explain further? Are you saying that > noise is required to resolve the metastable state, or is this a > counter-argument to the "noise may get you out faster" claim? Or is > it something else entirely? I guess this was not well stated. This was in response to someone else who seemed to be saying that noise is needed to get out of metastability. Just before this I believe I spoke about the perfect balance point being so small that it was not significant. So noise is not really needed. The quote above was to say that if noise really is required, then the advocates of more noise may be right. But my point is that noise is not needed since there is virtually never a "perfect" balance. -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAXArticle: 59969
I second Paul's endorsement of Aldec. I've been using both Aldec and Modelsim
for several years now. I prefer to do the bulk of the work in Aldec. I find it
more intuitive, and like Paul said, it is a fairly well integrated set of
tools. I haven't had any big problems with the project management, I guess it
is what you are used to. Compared to modelsim, I think the aldec tools are more
comfortable to use, and the design entry is miles ahead of modelsim. I use the
full Aldec AHDL mixed sim package, which last I checked was competitive
pricewise with the single language version of Modelsim. Aldec also lets you
open more than one instance of the tools, which is really handy if you are
someone that is working on more than one project (as a consultant, I
occasionally need to open a different project to answer a query about a design
that I might not be working on that day). Modelsim complains with a license
unavailable message if you try that there.
Paul Baxter wrote:
> At the risk of starting a toolset discussion, I would recommend
> www.aldec.com and their ActiveHDL product.
>
> Its mainly a very user friendly simulator (still not perfect, but a lot
> friendlier than Modelsim and on a par with its power and speed) but it also
> does much of the design entry and state machine generation/ testbench
> generation and project management as well.
>
> It also integrates very well with a large number of synthesis tools so that
> you never need to leave ActiveHDL to synthesise and then simulate the
> finalised P&R product.
>
> I believe you can get a reduced price Altera-only or Xilinx-only version.
>
> My 2 pence worth :) Having used it for real for a year or so. No affiliation
> with the company etc. etc.
>
> Paul Baxter
>
> "Robert Abiad" <abiad@ssl.berkeley.deletethisandaddedu> wrote in message
> news:3F4E6463.5030207@ssl.berkeley.deletethisandaddedu...
> >
> > Hello,
> >
> > I'm wondering if anyone wants to offer up their opinion of Mentor's HDL
> Designer
> > series or FPGA Advantage (Designer + simulation&synthesis)? I recently
> acquired
> > it, but am wondering about the quality of the resulting code. It looks
> like it
> > might be very easy to produce stuff with it, but does it save time coding
> in the
> > end?
> >
> > Thanks,
> > -robert
> >
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 59970Luiz Carlos wrote: > > > If you think there is no uncertanty in measuring the spin of an > > electron, you need to go back to school. > > Rick, I din't say that. I said electron spin does not presents > metastability. It does not matter in the least what state the electron is in. Metastability is a measurement problem. When you try to measure the state of a FF with a gate or second FF, that is where metastability is an issue. The first FF is in a state where the voltage will ultimately resolve itself to a final value. So the issue of metastability is really one of measuring the state well enough to resolve the final state of the FF. Just like the metastability was created by the inability of the FF to measure the state of the input at the sampling time. Electron spin has all the same measurement issues that a FF has. If the state of the electron spin is changing as the measurement is made, then what state is it in? What will be the result of the measurement? > Anyway, did you hear about spintronics? Maybe the scientists behind > this idea may go back to school too! > > Look at > http://www.eetimes.com/story/OEG20001221S0035 > Cut and paste please, I don't know how to include hypertexts. > I think that shows my whole point of view: if you believe, insist! > > Unhappily (for me) I could not find the text about the electron > position. -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAXArticle: 59971
Glen Herrmannsfeldt wrote: > > "rickman" <spamgoeshere4@yahoo.com> wrote in message > news:3F50A0E8.15AAA082@yahoo.com... > > (snip regarding the DEC KA-10, metastability, and self-timed logic) > > > I am no expert in async logic, but I have never heard of a circuit that > > can even detect metastability. I also thought that async logic did not > > "measure" the time it took for a calculation, it simply allowed > > different times for different calculations. The control path for a > > given circuit has a longer delay than the data path and would be > > dependant on the calculation being performed. How exactly would a > > circuit detect when an async calculation is complete? > > Well, I agree with the skepticism in the first place, but consider a CPU > with lights indicating the current contents of the registers. Normally, the > values will be changing very fast. If they suddenly stop changing, it could > be because of unresolved metastability. The logic will wait quietly for it > to resolve, and then continue. I don't see how this is possible. You are assuming that the CPU has some way to measure that a FF output is metastable. I don't know of any way of doing that. How is this circuit designed? > It might be, though, that the machine is in I/O wait, and there really is > nothing to do. I never got to actually see the machine, but at the time > many machines had console lights, at least for the instruction counter and a > few other important registers. (Though I don't believe that the PDP-10 had > a wait state like IBM S/360 did, where no instructions were executed.) It is also possible that the lights are not a valid indication of the state of the CPU. Since the CPU runs at thousands of times faster than the eye can see, it is entirely possible that a loop is being executed that makes the lights appear to be lit, but are actually flashing much faster than you could see. If the duty cycle is high for each light that is flashing you would not see a dimming either. -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAXArticle: 59972
I'd be curious to hear about a benchmark or two:
what is the transform time for a given size FFT, say 256 points?
what is the FPGA utilization for that FFT?
Precision/accuracy?
I have an FFT kernel specifically designed for FPGAs that also has nothing
idle during the FFT processing. It also does not use the usual C-T
butterfly, and has only local data flow. The data sheet for the 16 point
kernel is posted on my website.
Seung wrote:
> Hello
>
> I have a patent and recently added one more on innovative FFT
> algorithm and architecture.
> If you're a business minded expert on FPGA with interests in DSP, this
> is a great opportunity. Our FFT is 'the' optimal HW solution as
> follows:
>
> 1. Minimum HW complexity: 100% HW utilization
> 2. Suitable for super fast pipelined FFT: only local data flow - not
> based on butterfly algorithm
> 3. Minimum clock cycles: baseline architecture needs N clock for
> N-point FFT
> 4. Scalable to arbitrary large FFT size
> 5. Multi-dimension extension: world's first 'intrinsic'
> multi-dimensional FFT algorithm & architecture (not relay on 1-D FFTs)
> : great for 2-D/3-D real-time medical imaging, SAR, etc.
>
> If you're interested in building a business together based on this
> innovation,
> please contact me with your resume. It'll be ideal if you have
> contacts for potential customers.
>
> Any help on this matter from FPGA/DSP group members will be
> appreciated.
>
> Thanks.
>
> Seung P. Kim, Ph.D
> Silicon Computing, Inc.
> Mountain View, CA
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 59973
Hi Austin,
Maybe I got the wrong end of the stick, but when Peter said:-
"I have never seen strange levels or oscillations ( well, 25 years ago
we had TTL oscillations). Metastability just affects the delay on the
Q output." I thought he meant that he'd only seen metastability where
the output from the FF was always either on or off, just that
sometimes the transition was delayed. Philip's pictures clearly show
'strange levels'. This is important, I believe, when deciding what the
effects of metastable FFs are on following circuitry. I guess we'll
have to wait until he returns from his Portugese jaunt before we find
out what he meant!!
Of course, I agree the Master/Slave thing helps. A master FF
on its own is what I'd call a latch, the clock controlling whether
it's transparent or not. The slave is the sameish circuit again, fed
from the output of this, but its clock is inverted. So, I guess that
you're saying because the master and slave are fabricated right next
to each other, the input to the slave can be expected to transition
faster than the input to the master which travels from further away?
Less capacitive interconnect to drive. (BTW, I assumed throughout the
metastability stuff we were talking about D-type FF, rather than
latches.)
thanks, Syms.
Austin Lesea <Austin.Lesea@xilinx.com> wrote in message news:<3F550102.DC2B872F@xilinx.com>...
> Symon,
>
> I think the sampling o-scope shots agree perfectly with what Peter said.
> Runt pulse, and funny levels are the easiest metastable results to catch,
> as they are just before the long unknown settling time behavior that is so
> vexing to designers.
>
> It also makes a difference where you look: a master-slave FF reduces the
> duration of the unknown transistion over a simple FF without a slave to
> help "sharpen up" the transistions.
>
> Austin
>
> Symon wrote:
>
> > Hi Philip,
> > Thanks for your post, those pictures were certainly very
> > interesting! What parts did you use? I notice they seem to disagree
> > with Peter's quote that "Metastability just affects the delay on the Q
> > output.". I wonder, Peter, if Xilinx FFs behave differently from the
> > ones in Philip's photos? (Other than speed, of course.) I must admit,
> > one reason I posted was that I found hard to believe that any FF
> > wouldn't show runt pulses, or funny output levels, albeit for brief
> > periods of time, during metastable events.
> > It's also interesting that the straight shift register isn't
> > necessarily the best way to reduce metastability effects. That was
> > what I suspected and was another reason behind my post. I agree that
> > the 'four paths out of phase' solution is better, and preserves the
> > sampling resolution. Often the sampling resolution needs to be
> > preserved, which was why I didn't present an 'enabled every third or
> > fourth go' type circuit.
> > Anyway, thanks to all for their thoughts, it's an interesting
> > topic!
> > cheers, Syms.
Article: 59974"Antti Lukats" <antti@case2000.com> skrev i en meddelelse news:80a3aea5.0309020440.3a8e4a23@posting.google.com... > "John T." <john@dat.com> wrote in message news:<bj1l57$plr$1@news.net.uni-c.dk>... > > Please does anyone have experience with EDK 3.2 for embedded design? > > I am trying to make my microblaze processor to be interrupted when I push a > > certain input button. I can make Timer-interrupt work, but I cant make and > > outside stimuli to interrupt the processor. Anyone know how to do this? > > I have added a interrupt-controller to the opb bus, and set its irq to the > > same net as the Microblaze Interrupt. > > > > John > > simple external ints should work as well (as timer ints), well > connecting a push-button directly to int net probably isnt the best > idea, there will always be some bouncing :( > > just a note: if you have multiple interrupt sources then you have to > assign to them all different names and write those names with "&" > concatenated in the edit core dialog - this was something that did > take long time for me to understand (until I found that is in the IP > core manual, not INTC pdf but general IP cores document). > > just check that the int lines are connected in the system.vhd file and > that the interrupt handler procedures are assigned correctly, then > when you enable int it should come? > > antti > http://www.graphord.com/forum Thanx for the reply. My question is more likely: Where, in what menu do you set an external input to be an interrupt source??? Where do you declare the name of the interrupt function??? With a timer you can do that by right-clicking the timer and chose a name for the "timer interrupt handler function". Beset Regards John
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