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Hi, I've installed ModelSim 5.7d SE and Xilinx ISE 5. and am trying to build the Xilinx libraries using compxlib -s mti_se -f all -l all -o c:\modeltech_5.7b\xilinx_libs -p c:\Modeltech_5.6b\win32 It complains that it cannot find mti_se executable. I found technotes on compxlib on the Xilinx website but it didn't shed much light on how the -simulator switch works. Can anyone help me out ? IT WOULD BE REALLY APPRECIATED !!!!Article: 59751
see if you can find jed2abl around - many of the abel compilers had this feature - converted jedec files to abel code Andrew yusuke wrote: >Hi, > Is it possible to convert jedec to logical equations? I've got a jed >file for a xilinx cpld(XC9536xl) and I'm trying to recover a job done >a long time ago. Or, is it possible to discover the pinout based on >the jed file? This would be quite useful too. > >Thanks in advance, >yusuke >PS: Sorry for my poor English skills. > >Article: 59752
Peter Alfke <peter@xilinx.com> wrote in message news: > > But we cannot fix it, not with voting, nor with hysteresis, nor with any > other contraptions. > > My thanks to Bob Perlman for kicking me in the shins. It's good to have > friends. :-) > Peter Alfke Question: When a D-type flip-flop is in meta-stability, is it's output (Q pin) voltage equal to the input (D pin) voltage? If it's not the same voltage, then a cascaded flip-flop, clocked just after the first one, would not be in meta-stability! Isn't it? Luiz CarlosArticle: 59753
Josh Model wrote: > >*Right. we get all 40 numbers (outputs of Multiply accumulates) once every >N clock cycles, with N probably being determined by the update rate at which >we can find the maximum. In the ideal situation, N = 1, and we update the >maximum index every clock cycle. > How do you load 40 20-bit numbers into an FPGA in parallel? That would take 800 pins! And, I don't think the brute force solution, with a cascade of comparators will work very fast, as the ripple-through time of 20 comparators is going to be quite slow. I suppose a binary tree-structured arrangement of the comparators has got to be better, and the additional cost of comparators looks like it is very small. I worked out that 41 comparators will build the tree (20, 10, 5, 3, 2 and 1) and then you could pipeline the stages. It looks like a 6-stage pipeline would do the job. If the clock is not really fast, then you could combine pipeline stages and do it in 3 clocks. JonArticle: 59754
John Williams <jwilliams@itee.uq.edu.au> wrote in message news:<bigoij$bs8$1@bunyip.cc.uq.edu.au>... > Jean Nicolle wrote: > > my manager said it couldn't be done. So just to prove him wrong :-) > > There is no better reason! :-) > > > http://www.fpga4fun.com/PWM_DAC.html > > > > Well, pretty simple stuff anyway. > > Nice work Jean, it's a great thing you're doing with that site. I agree. But for better audio quality with little extra effort have a look at this: http://www.xilinx.com/apps/xappsumm.htm#xapp154 Kolja SulimmaArticle: 59755
Nevermind - I fixed my own problem. Thanks if you were going to reply.Article: 59756
The output level of a flip-flop during its metastable time is irrelevant. If it were in the middle ( which it isn't) we could easily fix this with a zener diode. The problem is timing. The Q output can - and will - change to the opposite state at a totally unpredictable time. That's the problem: unpredictable timing, not unknown levels. Cascading flip-flops is the standard remedy, but it introduces latency. Remember: Metastability causes an extra 3 ns of unpredictable delay once in a billion years... Seems to be an affordable risk. Peter Alfke ========================= Luiz Carlos wrote: > > Peter Alfke <peter@xilinx.com> wrote in message news: > > > > But we cannot fix it, not with voting, nor with hysteresis, nor with any > > other contraptions. > > > > My thanks to Bob Perlman for kicking me in the shins. It's good to have > > friends. :-) > > Peter Alfke > > Question: When a D-type flip-flop is in meta-stability, is it's output > (Q pin) voltage equal to the input (D pin) voltage? > > If it's not the same voltage, then a cascaded flip-flop, clocked just > after the first one, would not be in meta-stability! Isn't it? > > Luiz CarlosArticle: 59757
gregs@altera.com (Greg Steinke) wrote in message news:<5c1de958.0308261353.598286c4@posting.google.com>... > Matt, > Generally speaking, this kind of problem indicates that the device did > not correctly receive the preamble to the configuration bitstream, and > therefore did not start to process the data. This explains why nSTATUS > doesn't go low; the device has not yet started to look at the CRC for > each frame of data. > The problem turned out to be in the file I was sending. I was using an SOF, because I thought it was raw. Once I found the .rbf option, I switched to that, and it works now. I didn't find mention of this in appnote 250, which is on Cyclone configuration. Thanks for your help. MattArticle: 59758
On a sunny day (Tue, 26 Aug 2003 18:58:54 GMT) it happened Rene Tschaggelar <tschaggelar@dplanet.ch> wrote in <d8a593f9a0070578ab8201755480f4a3@news.teranews.com>: >NOSPAM@NOSPAM.invalid.com wrote: >> Hello, >> Please, does anybody know if there's any FPGA manufacturer >> that will give a sample FPGA for free? > >You're going to spend days and weeks with the free software, >to become familiar. >And you may have to build your own programmer, again a day of >layout and etching, so what does it help if you don't have to >pay 4$ for a 4$ part ? That will buy you a huge peche melba here, nice if its 40 celcius.Article: 59759
FWIW, I'm using the full 5.2i (not Webpack, the full package) as well as Norton Antivirus and have yet to have any problems related to their interaction. -- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ Martin Euredjian To send private email: 0_0_0_0_@pacbell.net where "0_0_0_0_" = "martineu" "Leon Heller" <leon_heller@hotmail.com> wrote in message news:3f4c8fd6$0$256$cc9e4d1f@news.dial.pipex.com... > In common with some other software I use, WebPack ISE is screwed up by > Norton Anti-virus software; for instance, User Constraints Chip Viewer > hangs. I'm still using 4.2, but 5.2 might have the same problem. I found > this rather puzzling, until I realised what was wrong. > > Leon > -- > Leon Heller, G1HSM > leon_heller@hotmail.com > http://www.geocities.com/leon_heller > >Article: 59760
Maybe the following would help some people:
http://www.fpga-faq.com/FAQ_Pages/0017_Tell_me_about_metastables.htm
Let me be dogmatic:
Flip flops may go metastable when input signals do not meet the setup
and hold specifications with regard to the clock signal. These inputs
include D, CE, CLR, PRE, S, R, T, J, K.
There is no cure for metastability. What you can do is trade latency
of your system for higher MTBF.
People that have found a cure are wrong.
Circuits that purport to solve metastability through hysteresis fail
because the hysteresis circuit itself can go metastable
Circuits that purport to solve metastability with injected noise fail
because the noise is as likely to push a non-metastable event into
being a metastable event as it is to helping to resolve such an
event.
Just because current flip flops are better than stuff of a few years
ago, and the probability and resolution time of metastable events
is better, does not mean you can ignore this stuff. If someone
says that things are so good now that "you almost don't have to
worry about this anymore", what it means is that you absolutely
need to understand it and design for it. If you don't, you will
have unreliable systems.
Nothing improves the MTBF of a metastable synchronizer better than
just waiting longer. Not clocking the intermediate signal on the
negative clock edge. Not voting. Not threshold testing. Not adding
noise. Not fancy SPICE simulations. Not predicting circuits. Not
circuits designed to bias the outcome to either 1 or 0. Not
clocking it twice as fast through twice as many flip flops.
Nothing.
>From Thomas Cheney, October 1979:
"In closing, there is a great deal of theoretical and experimental
evidence that a region of anomalous behavior exists for every device
that has two stable states. The maturity of this topic is now such that
papers making contrary claims without theoretical or experimental support
should not be accepted for publication".
Philip Freidin
Philip Freidin
Fliptronics
Article: 59761Peter Alfke wrote: > > Rick: > as I mentioned, the metastability-catching is so small, that you may not > hit it consistently even if you try ( 0.07 femtoseconds width for a 1.5 > ns metastable delay. > If you can accomodate 3 ns of delay, the probability gets so small, you > can forget about it. Every extra half nanosecond increases the MTBF a > million times. I understand how the resolution time affects the failure rate. I also understand that the timing window is so small that it is very hard to hit even if you try. My point is that the analysis has been done assuming a random distribution of timing which is not valid for this case. If you have an MTBF of 100 years with the standard model, you may well see an MTBF of an hour or less with this situation. I will be using a half clock cycle (10 ns) minus some 5 ns of delay which should give me lots of room for settling. But unless I acutally know something about my timing distribution it will be hard to say what my expected MTBF is. Of course, it is actually very unlikely that the timing of my circuit will be such that the problem shows even without the resolution time. But this sort of circuit does not prevent the worse case timing if all the planets line up and the constellations are aligned. > If you are still not convinced, you could develop a training ( adaptive > ) search for a safe clock phase. Virtex-II DCMs do this exceptionally > well with their fine phase control, but there are also other, less > elegant methods. Unfortunately this design is in the 5 volt tolerant chip I am using. I won't mention any brands, but if you remember our previous conversations about such chips you will realize that it is not a Xilinx part. Too bad, I actually prefer the Xilinx parts and tools. :( -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAXArticle: 59762
> I've installed ModelSim 5.7d SE and Xilinx ISE 5. and am trying to > build the Xilinx libraries using > > compxlib -s mti_se -f all -l all -o c:\modeltech_5.7b\xilinx_libs -p > c:\Modeltech_5.6b\win32 I can see three modelsim version numbers (5.7d, 5.7b, 5.6b) in the above four lines. Could this be a problem? Jim Wu jimwu88NOOOSPAM@yahoo.com http://www.geocities.com/jimwu88/chipsArticle: 59763
Rickman, In article <3F4D6661.707572C8@yahoo.com>, spamgoeshere4@yahoo.com says... > Using the MSB of a prescale counter to use as a 312.5 kHz enable will > not work. This pulse will be true for half the period and will enable > some 64 system clock pulses each time it is true. You want a pulse that > is one clock wide. You can either use a AND function to detect the > count of 127 (which may end up being implemented in the carry chain) or > use a FF to delay the MSB by one clock and an AND gate and inverter to > generate a pulse one clock wide on each rising edge of the MSB. This > 312.5 kHz signal can then be AND'd with the output of the MUX to drive > your counter enable. Thanks for the suggestion! Best regards. -- Jay.Article: 59764
Kolja Sulimma wrote: > > John Williams <jwilliams@itee.uq.edu.au> wrote in message news:<bigoij$bs8$1@bunyip.cc.uq.edu.au>... > > Jean Nicolle wrote: > > > my manager said it couldn't be done. So just to prove him wrong :-) > > > > There is no better reason! :-) > > > > > http://www.fpga4fun.com/PWM_DAC.html > > > > > > Well, pretty simple stuff anyway. > > > > Nice work Jean, it's a great thing you're doing with that site. > > I agree. > But for better audio quality with little extra effort have a look at this: > http://www.xilinx.com/apps/xappsumm.htm#xapp154 > > Kolja Sulimma I never wrote it up in any way, but I once used a PC timer chip which drives the internal speaker to reproduce signalling tones using PWM. I don't remember this being part of my job, I think I was just playing around with the idea and tested it at work since they had some sampled sound files. A manager was walking by and recognized the sound. When he found out that I did it without a sound card, he wanted me to add it to their signal software package. This was in the days when DOS was still around and not many PCs had much more than the internal beep-boop speaker. He never got it funded so I didn't add it to the product. But my little test program worked suprizingly well. -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAXArticle: 59765
Jay wrote: > > Hello all, > > I have a slightly interesting problem here, and I wanted to know if my > approach has any hazards which I should be aware of. My design is for a > CPLD, if that matters. > > I have a binary synchronous counter, I call Master_Counter, that I want > to clock at 312.5kHz (1/128th my system clock of 40MHz). I generate my > 1/128 Prescale_CLK by picking off the MSB of a 7-bit counter which is > clocked at Sys_CLK frequency(40MHz). > > In my design, Master_Counter usage is multiplexed -- it will be used to > time four separate signals (which are synchronous to the 40MHz Sys_CLK) > all 26kHz or below. To be able to select which signal is timed, I route > my 4 signals into a 4:1 MUX. > > My current approach is to use Prescale_CLK to gate the ENABLE on the > counter, with Master_Counter getting clocked from the 40MHz Sys_CLK. > > Since I need to time one of the four signals, I am actually ANDing the > output of the 4:1 MUX with the Prescale_CLK and that feeds the ENABLE > pin on Master_Counter. > > From reading the c.a.fpga archives, I *think* this is the correct > approach since I've read the CLK input itself should never be gated, > only the ENABLE but I would appreciate any commentary. > > My other problem is dealing with reset/clear logic which could get > complicated, since I need to make sure the counter is reset/ENABLED > properly when the MUX is switched (which occurs asynchronous to the four > signals). I have seen Mr. Alfke's circuit that allows you to switch > asynchronous clocks, I'll look at that again for ideas. I got your email, but I thought I would reply here. CPLD vs. FPGA does not matter as far as I know. If I understand what you are doing, you have a system clock of 40 MHz, but want to use a 312.5 kHz clock to time one of four inputs which switch synchronously with your system clock. Using the MSB of a prescale counter to use as a 312.5 kHz enable will not work. This pulse will be true for half the period and will enable some 64 system clock pulses each time it is true. You want a pulse that is one clock wide. You can either use a AND function to detect the count of 127 (which may end up being implemented in the carry chain) or use a FF to delay the MSB by one clock and an AND gate and inverter to generate a pulse one clock wide on each rising edge of the MSB. This 312.5 kHz signal can then be AND'd with the output of the MUX to drive your counter enable. -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAXArticle: 59766
In article <3F4D5682.AA13889@yahoo.com>, rickman <spamgoeshere4@yahoo.com> wrote: >I understand how the resolution time affects the failure rate. I also >understand that the timing window is so small that it is very hard to >hit even if you try. My point is that the analysis has been done >assuming a random distribution of timing which is not valid for this >case. If you have an MTBF of 100 years with the standard model, you may >well see an MTBF of an hour or less with this situation. I will be >using a half clock cycle (10 ns) minus some 5 ns of delay which should >give me lots of room for settling. But unless I acutally know something >about my timing distribution it will be hard to say what my expected >MTBF is. Then add random jitter into your CLOCK, and now you are back into the randomized model, no? -- Nicholas C. Weaver nweaver@cs.berkeley.eduArticle: 59767
Philip Freidin wrote: > > Maybe the following would help some people: > > http://www.fpga-faq.com/FAQ_Pages/0017_Tell_me_about_metastables.htm > > Let me be dogmatic: > > Flip flops may go metastable when input signals do not meet the setup > and hold specifications with regard to the clock signal. These inputs > include D, CE, CLR, PRE, S, R, T, J, K. > > There is no cure for metastability. What you can do is trade latency > of your system for higher MTBF. > > People that have found a cure are wrong. > > Circuits that purport to solve metastability through hysteresis fail > because the hysteresis circuit itself can go metastable > > Circuits that purport to solve metastability with injected noise fail > because the noise is as likely to push a non-metastable event into > being a metastable event as it is to helping to resolve such an > event. > > Just because current flip flops are better than stuff of a few years > ago, and the probability and resolution time of metastable events > is better, does not mean you can ignore this stuff. If someone > says that things are so good now that "you almost don't have to > worry about this anymore", what it means is that you absolutely > need to understand it and design for it. If you don't, you will > have unreliable systems. > > Nothing improves the MTBF of a metastable synchronizer better than > just waiting longer. Not clocking the intermediate signal on the > negative clock edge. Not voting. Not threshold testing. Not adding > noise. Not fancy SPICE simulations. Not predicting circuits. Not > circuits designed to bias the outcome to either 1 or 0. Not > clocking it twice as fast through twice as many flip flops. > Nothing. > > From Thomas Cheney, October 1979: > > "In closing, there is a great deal of theoretical and experimental > evidence that a region of anomalous behavior exists for every device > that has two stable states. The maturity of this topic is now such that > papers making contrary claims without theoretical or experimental support > should not be accepted for publication". > > Philip Freidin Very well put. I think it is so well said that it sould be added to the FPGA FAQ. There is a comp.arch.fpga FAQ, right? -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAXArticle: 59768
I'm using Spartan-II XC2s50 with platform flash Prom XCF01s. I've to implement a 32x1 FIFO (with 16 bits for data of channel I and 16 for channel Q). I'm thinking to implement it in the Block RAM (Is there any other method which is more efficient than this one in SpartanII?). The dual RAM ports of Spartan-II are configurable to any size from 4Kx1 to 256x16. (In the XAPP173 "Using Block Select Ram+ Memory in Spartan-II" of Xilinx, there is a table1 which don't have port aspect ratios for 32x1) Can I implement FIFO of 32x1 in this BlockRam of Spartan-II? Regards AtifArticle: 59769
Can anyone please tell me is Xilinx Platform Flash PROM an Electrically erasable? If no, which technology it uses? Regards AtifArticle: 59770
How about not just music out of an FPGA pin, but a complete shortwave receiver using just a SpartanII FPGA
and an AtoD converter? See the block diagram on my website. I'll be demo'ing it in two weeks at the
MAPLD conference, as well as discussing the design in the 6 hour tutorial seminar on DSP for FPGAs I will
be doing on the Monday of the conference. The demo is on an Insight spartanII board containing an
XC2S100. The only mods to the board are an RC filter between the FPGA pin and the speaker jack, the
speaker jack and two blue jumpers to make the ADC demo board plug onto one connector. It actually works
without a filter in front of the ADC demo board if the SNR is high enough (I was able to receive BBC from
Rhode Island with the antenna connected directly to the ADC board). Adding a tunable antenna preamp makes
it a usable for AM and SSB reception over DC to 20MHz. The ADC is external because it is sampling at
40MHz, 12 bits. The DAC for the speakers is a stereo sigma-delta DAC implemented in the FPGA.
rickman wrote:
> Kolja Sulimma wrote:
> >
> > John Williams <jwilliams@itee.uq.edu.au> wrote in message news:<bigoij$bs8$1@bunyip.cc.uq.edu.au>...
> > > Jean Nicolle wrote:
> > > > my manager said it couldn't be done. So just to prove him wrong :-)
> > >
> > > There is no better reason! :-)
> > >
> > > > http://www.fpga4fun.com/PWM_DAC.html
> > > >
> > > > Well, pretty simple stuff anyway.
> > >
> > > Nice work Jean, it's a great thing you're doing with that site.
> >
> > I agree.
> > But for better audio quality with little extra effort have a look at this:
> > http://www.xilinx.com/apps/xappsumm.htm#xapp154
> >
> > Kolja Sulimma
>
> I never wrote it up in any way, but I once used a PC timer chip which
> drives the internal speaker to reproduce signalling tones using PWM. I
> don't remember this being part of my job, I think I was just playing
> around with the idea and tested it at work since they had some sampled
> sound files. A manager was walking by and recognized the sound. When
> he found out that I did it without a sound card, he wanted me to add it
> to their signal software package. This was in the days when DOS was
> still around and not many PCs had much more than the internal beep-boop
> speaker.
>
> He never got it funded so I didn't add it to the product. But my little
> test program worked suprizingly well.
>
> --
>
> Rick "rickman" Collins
>
> rick.collins@XYarius.com
> Ignore the reply address. To email me use the above address with the XY
> removed.
>
> Arius - A Signal Processing Solutions Company
> Specializing in DSP and FPGA design URL http://www.arius.com
> 4 King Ave 301-682-7772 Voice
> Frederick, MD 21701-3110 301-682-7666 FAX
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 59771Hi all, What is the price for a maximux of 50K system gates, IO counts is not an issue, with more than 100K volumn per year? We look at cyclone and spartan series because Xilinx and Altera claimed they are cheap. 100K is the minimum. Thanks, JohnArticle: 59772
I need to comunicate with a DSP in serie. Is there a way that any one know of?Article: 59773
"Simone Winkler" <simone.winkler@gmx.at> wrote in message news:<1062000650.772797@news.liwest.at>... > Hello! > > I am a newbie trying to perform a simulation with ModelSim... > I did a (very small) project with the Xilinx downloadable webpack - and as i > wanted to simulate it with modelsim, modelsim closed after the following > line: > > #vsim -lib work -t 1ps -L xilinxcorelib testbench > > the transcript file shows the following: > > # Reading D:/Programme/Modeltech_5.5d/win32/../tcl/vsim/pref.tcl > > my modelsim version is 5.5d - but i also tried 5.5e. Didn't work! > They always crash after the same line. > I already tried to reinstall everything - no change. I don't know what to do > anymore...please help me!!!! > > Thanx, > Simone Take a look to the file "transcript" in D:\Programme\Modeltech_5.5d\examples: before crashing some messages should have been written in it by the program, clarifying the cause of the crash. Hope this helps, G. GiachellaArticle: 59774
We are debugging a pci board and met some difficulties. The main chip is, the local device is SJA1000. We used 8-bit local bus(LAD[7:0]) as data-address multiplex mode, and using this local bus for PCI to communicate with SJA1000. The difficulty I met is I can¡¯t read the register of SJA1000. I want to know the possible cause and how to solve it. And I want to know how to configure the ¡°Local Address Space (0~1) Bus Region Descriptor Register Description¡±, maybe there is some wrong with the timing between the PCI9052 and SJA1000. Thanks for your time, lynch
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