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I had the identical problem. This tells you how to fix it: http://www.xup.msu.edu/solutions/xurc4.htm Basically copy the CD to your HD and overwrite the Java installer with version 1.22. Adam "Seba" <sduszyk@poczta.fm> wrote in message news:bin8b4$dhm$1@atlantis.news.tpi.pl... > Hi all, > > I have a problem. While trying to install old Xilinx Foundation Series F2.1i > on Windows 2000, just at the beginning of installation I got the message: > "The exception unknown software exception (0xe06d7363)occured in > the application at location 0x77eab2f0". > and the installation is ending. > I know that this version of Xilinx enviroment was not designed for the Win2k > but I saw once that one guy had it working on Win2k (I don't know how they > done this on Win2k and don't have the contact with this people). > Also I know, that Xilinx uses Java for installation. So I've tried to > install Java Development kit v.1.1.8 but it doesn't helped. > Do you know of any solutions for this, how to install this version on Win2k > ??? > Regards > Sebastian > >Article: 59851
> This is the classic defense of otherwise indefensible ideas. "They > said that a flying machine was impossible." "They said that Einstein > was crazy." Statements like these ignore certain realities, namely: > > (a) Much of what was said to be impossible still is, and shows every > sign of remaining so. If you believe that there are laws of physics, > even laws that are somewhat at odds with the ones we now hold true, > then those laws must say that certain things can happen and others > cannot. If they don't, they aren't laws. > Hi Bob, Which laws? Classical physics laws, like every other, have a domain where they give better approximations. We are still trying to find the Theory Of Everything. Peter has mentioned the "Heisenberg's Uncertainty Principle", but I read somewhere, althought we can't know where a particle is in a momentum, we can know where it is not, so, we can infer where it is. If we take the electron spin, there is no metastability. It changes it's direction in one "fundamental" clock cycle (time is not continuous). I think there is also no metastability problems in Single Electron Devices. So, Virtex436 possibly will not have metastability problems. > (b) In all of human history, most of the people "they" called crazy > were, in fact, crazy. > > Luiz, it's fine with me if you want to believe that metastability can > be prevented. But for all of you folks who have been reading this > thread and wondering just what to do about metastability in your > designs, just read Philip Freidin's excellent summary and follow the > link he pointed to for more information. > > Do we really want to keep repeating the same old mistakes? Woudn't it > be more fun to make some new ones? > > Bob Perlman > Cambrian Design Works Bob, I know that everything I said don't help us with our today metastability problems. I spent a lot of time trying to defend my opion about something that is not related to the topic, fruitless! I'll try to not repeat the same mistake. I agree with you about Philip, it really looks like he knows a lot. Thanks to everybody, I learned a lot about metastability. Luiz CarlosArticle: 59852
> there is one BADTHING the current ProAsic+ do require +16,5 and -13,5 power > supplies during programming ! (programming is JTAG stapl) if it is supplied by the programmer than it's not a problem. However, I've read in the data sheet that they are only programmable about 100 times (far too less for development). As I can see, the internal memory can not be loaded with default data. And no flash for user data on the chip. Still far away from a SoC solution. So, nice device, but Cyclone or Spartan are still more interesting. MartinArticle: 59853
Thanks very much !!!!!!!!!!!! Best regards Sebastian "Adam" <1@1.com> wrote in message news:veJ3b.27071$lk1.22718@twister.nyroc.rr.com... > I had the identical problem. This tells you how to fix it: > http://www.xup.msu.edu/solutions/xurc4.htm > > Basically copy the CD to your HD and overwrite the Java installer with > version 1.22. > > Adam > > "Seba" <sduszyk@poczta.fm> wrote in message > news:bin8b4$dhm$1@atlantis.news.tpi.pl... > > Hi all, > > > > I have a problem. While trying to install old Xilinx Foundation Series > F2.1i > > on Windows 2000, just at the beginning of installation I got the message: > > "The exception unknown software exception (0xe06d7363)occured in > > the application at location 0x77eab2f0". > > and the installation is ending. > > I know that this version of Xilinx enviroment was not designed for the > Win2k > > but I saw once that one guy had it working on Win2k (I don't know how they > > done this on Win2k and don't have the contact with this people). > > Also I know, that Xilinx uses Java for installation. So I've tried to > > install Java Development kit v.1.1.8 but it doesn't helped. > > Do you know of any solutions for this, how to install this version on > Win2k > > ??? > > Regards > > Sebastian > > > > > >Article: 59854
On 27 Aug 2003 23:55:31 -0700, catfist2003@yahoo.com (John Lee) wrote: >Hi all, > >What is the price for a maximux of 50K system gates, IO counts is not >an issue, with more than 100K volumn per year? We look at cyclone and >spartan series because Xilinx and Altera claimed they are cheap. > >100K is the minimum. > >Thanks, >John for this volume you will obviously need to contact the disti/factory but for the Cyclone the quantity 50K pricing from the disti as below. better deals may be found I suspect if the volume goes up a bit and in 2004 ... EP1C3 $5 , EP1C4 $11 , EP1C6 $13 , EP1C12 $27 , EP1C20 $60Article: 59855
Stefan Philipp wrote: > Hi Allan > > under "edit->preferences->process" you can switch to "advanced property > mode" > than you can change it > > happy coding > stefan Thanks. It works now. Allan. > "Allan Herriman" <allan.herriman.hates.spam@ctam.com.au.invalid> schrieb im > Newsbeitrag news:3f4f4d0b@dnews.tpgi.com.au... > >>Hi, >> >>I'm using ISE 5.2.03, using XST Verilog flow. >> >>I can't turn keep_hierarchy on in the Project Manager. There is no >>field to do so in the Process - Properties - Synthesis Options dialog >>(which is where the documentation says it should be). >> >>My problem is that my RLOCs don't work because XST flattens the >>hierarchy and puts all my macros into the one HSET! I would like to try >>with keep_hierarchy on, but the *&(#$% GUI won't let me. >> >>Help! >>Allan. >> > > >Article: 59856
"Antti Lukats" <antti@case2000.com> wrote in message news:80a3aea5.0308282129.5f483d78@posting.google.com... <snip> > I guess the smallest spartan III and cyclone devices should also come down > below 10$ but then S3-50 does not have BRAM and both Spartan and Cyclone > do require config memory to be present what may add significant amount to > the final price (both money as board estate, etc) </snip> It's only the engineering samples of the S3-50 that doesn't have BRAM (or DCMs for that matter) but the production version will be fully outfitted. Check the Xilinx site for the latest info. If the system already includes a controller and flash and can get by without a programmed FPGA for a short time, the flash can take the place of the config memory by allowing the controller (processor, whatever) to program the device.Article: 59857
> <snip> > > I guess the smallest spartan III and cyclone devices should also come down > > below 10$ but then S3-50 does not have BRAM and both Spartan and Cyclone > > do require config memory to be present what may add significant amount to > > the final price (both money as board estate, etc) > </snip> > > It's only the engineering samples of the S3-50 that doesn't have BRAM (or > DCMs for that matter) but the production version will be fully outfitted. > Check the Xilinx site for the latest info. > > If the system already includes a controller and flash and can get by without > a programmed FPGA for a short time, the flash can take the place of the > config memory by allowing the controller (processor, whatever) to program > the device. > > The cheapest way for the configuration is using a standard flash and a small PLD (like max7032 or max7064) and you can use the rest of the flash for other data (like program for a soft core cpu). Martin -- ---------------------------------------------- JOP - a Java Processor core for FPGAs: http://www.jopdesign.com/Article: 59858
The smallest Spartan3 part, the -50 came out without BlockRAM and DCMs, but only in its rushed "early silicon" a.k.a. "engineering samples" form. The real part, coming later this year, will have BRAMs and DCMs, just like all its larger brothers do. Peter Alfke ================ Antti Lukats wrote: > > ><snip> I guess the smallest spartan III and cyclone devices should also come down > below 10$ but then S3-50 does not have BRAM and both Spartan and Cyclone > do require config memory to be present what may add significant amount to > the final price (both money as board estate, etc) > > anttiArticle: 59859
Uwe Bonnes wrote: > > Peter, > > what happens if this setup time is violated? Will the BUFGMUX stall (no more > output clock until some reset), will it produce a runt ( some clock pulse > smaller than any of both input clocks) or will it switch clocks only > delayed? I didn't find anything in the datasheet. I don't know off-hand,. Will look into this when I am back from the European FPL2003 conference, i.e. Sept 8. Peter Alfke > > Nye > -- > Uwe Bonnes bon@elektron.ikp.physik.tu-darmstadt.de > > Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt > --------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------Article: 59860
Hi,
Before I start, metastability is like death and taxes,
unavoidable! That said, I've read the latest metastability thread. I
thought these points were interesting.
Firstly, A quote from Peter, who has carried out a most thorough
experimental investigation :-
"I have never seen strange levels or oscillations ( well, 25 years ago
we had TTL oscillations). Metastability just affects the delay on the
Q output."
Secondly, from Philip's excellent FAQ :-
"Metastable outputs can be
1) Oscillations from Voh to Vol, that eventually stop.
2) Oscillations that occur (and may not even cross) Voh and Vol
3) A stable signal between Voh and Vol, that eventually resolves.
4) A signal that transitions to the opposite state of the pre
clock
state, and then some time later (without a clock edge)
transitions
back to the original state.
5) A signal that transitions to the oposite state later than the
specified clock-to-output delay.
6) Probably some more that I haven't remembered. "
So, this got me thinking on the best way to mitigate the effects of
metastability. If Peter is correct in his analysis of his experimental
data, and I've no reason to doubt this, then Philip's option 5) is the
form of metastability appearing in Peter's Xilinx FPGA experiments.
So, bearing this in mind, a thought experiment. We have an async
input, moving to a synchronising clock domain at (say) 1000MHz. Say we
have a budget of 5ns of latency to mitigate metastability. The sample
is captured after the metastability mitigation circuit (MMC) with a FF
called the output FF.
My first question is, which of these choices of MMC is least likely
to produce metastability at the output FF?
1) The MMC is a 4 FF long shift register clocked at 1000MHz.
MMC1 : process(clock)
begin
if rising_edge(clock) then
FF1 <= input;
FF2 <= FF1;
FF3 <= FF2;
FF4 <= FF3;
output <= FF4;
end if;
end process;
2) The MMC is 4 FFs, each clock enabled every second clock.
MMC2 : process(clock)
begin
if rising_edge(clock) then
toggle <= not toggle;
if toggle = '1' then
FF1 <= input;
FF3 <= FF1;
output <= FF3;
else
FF2 <= input;
FF4 <= FF2;
output <= FF4;
end if;
end if;
end process;
Option 1) offers extra stages of synchronization between the input
and output, but the 1ns gap between FFs means that metastability is
more likely to propagate. Option 2) waits 2ns for the sample FFs to
make up their mind, vastly decreasing the metastability probability.
My second question is, does the type of metastability, i.e. the
things in Philip's list, affect which is the better choice? For
instance, if the first FF in the MMC exhibits oscillations in
metastability, then the second FF in the MMC would have several
chances, as its input oscillates, to sample at the 'wrong' time. This
might favour MMC option 2). If, however, the first FF in the MMC goes
into option 5) metastability, then there's only one chance for the
second FF to sample at the 'wrong' time. This might confer an
advantage on MMC option 1).
Anyway, I'm still thinking about this. I think the clock frequency
may decide which is better for a given FF type. Any comments?
Cheers, Syms.
Article: 59861David, It's better for you not using the Architecture Wizard and instantiate the DCM by yourself. I guess it was just developped and has some bugs. For another example the jitter calculator also could not work fine. "David Lamb" <gretzteam_nospam@yahoo.com> 写入消息新闻 :bill3u$852$1@home.itg.ti.com... > Hi, > I'm using a virtexII and I'm trying to use the Architecture wizard to divide > a clock by 5. However, the divided clock rising edge is aligned with the > falling edge of my input clock. Is this normal or I'm doing something wrong > in the Architecture wizard? How can I have both rising edge aligned? > > Here are the parameters I use > Input clock: 26Mhz, External > Divide by 5 > Feedback: internal, 1X > Duty cycle correction: yes > Phase shift: none. > > Thank you very much > David > >Article: 59862
Peter, So you mean this circuit is better than the BUFGMUX? "Peter Alfke" <peter@xilinx.com> ??????:3F4E7B2D.CFBD1D0D@xilinx.com... > Click at > http://www.xilinx.com/xcell/xl24/xl24_20.pdf > > This circuit allows totally asynchronous selection between two clock sources. > But remember: both clock must be wiggling (however slowly). You cannot > use this circuit to enable/disable a clock, which is actually a far > simpler problem. > The BUFGMUX in Virtex is not quite this clever, it has a set-up time > requirement on the S control input. :-( > Glad that someone found this old tidbit useful... > Peter Alfke > ============================= > Marten wrote: > > > > "David Lamb" <gretzteam_nospam@yahoo.com> wrote in message > > news:bilfne$sel$1@home.itg.ti.com... > > > Hi all, > > > I have a vhdl component with a "clock_in" input. Depending on the mode of > > > operation, I want to switch between two different clock signals. I will > > > never switch on the fly though. Can I use a mux in front of the clock_in > > > input? I'm afraid it might glitch. > > > Thanks > > > David > > > > > > > > > > David, > > > > Do a query for 'clock sources' in the category 'XCELL Journals' on the > > Xilinx web site. This will provide you with a link called 'XCELL 24 - > > Trouble-Free Switching Between Clocks (Q1 97)', which, in turn will lead you > > to xl24_20.pdf, a neat little circuit that hopefully will ease your worries > > :) > > > > Keep in mind that whatever you put in the clock path will affect the setup > > and hold time requirements for the particular component. > > > > Take care, > > > > Marten > > > > ] remove the obvious to repy by e-mail [Article: 59863
In article <a2214fd40dcc30b0380a43f3441e0804@news.teranews.com>, Rene Tschaggelar wrote: > Yes. > I'd get the peche melba by saving my time by not spending a > few hours on the internet looking for free samples of 4$ parts. Could someone tell me what is price of Altera Cyclone devices ? In Poland EP1C3T100C7 costs about 30$ (When I want to buy only 1 piece). I think it's to expensive. Thank you, PawelArticle: 59864
Dear all, I want to design an arithmatic datapath unit for digital signal processing using VHDL and/or Verilog. The input are 5 elements(either sequential or parallel) each having 8 bits. It needs to multiply each of these 5 inputs with a predefined constant matrix(10x10, floating point scaled and round to integer). The output will be a 10x10 matrix summing the above five matrices up, each element having 12 bits). So for each element of the matrix, I can have a MAC unit. The internal computation will be 16 bits. Hence for each 5 inputs x1, x2, x3, x4, x5, the output matrix Y=x1*C1+x2*C2+x3*C3+x4*C4+x5*C5 where Y, C1, C2, C3, C4, C5 are matrices; If I put an MAC for each element, I will have a purely parallel architecture, but I need 100 16bits MAC units, which will be too resource consuming. I am considering to make a parallel-serial architecture, at each time, it outputs one row, which will be 10x12 bits... so the output will be row-by-row. I also need to consider to streamlize the datapath operation. Since there will be a stream of 5 elements input in a non-stop fashion, the output will also be non-stop streaming. So after one row is outputted, that row can be used for computation/storage of the results for the next 5 input elements. I am ok so far in thinking... but further thinking makes me confused and perplexed... how to do sequential timing control(how to what to do at which cycle)? do I need to pipelining? how to design the architecture? I mean, I know pipelining theoratically from one semester course, but now I am going to implement one, I am totally lost... Finally, how to program this? Is there any examples for this? Please help me! Thanks a lot, -WalalaArticle: 59865
Hi, I am working on a project of a dc-dc converter wherein we require to generate hardware implementations from z-transform equations. My fellow researchers are using system generator and simulink to generate hardware implementation from the z-transform equations on FPGAs.(that is they get differential equation in terms of z^-1, z^-2 etc. for e.g. they realize 1.8*z^-2 using a constant element, a multiplier and two Z^-1 delay elements) However, I need to implement those z-transform equations on CPLDs. I wonder if i could use system generator for that. but nowhere in xilinx website or system generator documentation is there any mention of CPLDs. everywhere it says that DSP implementation can be done by system generator on FPGAs. however one thing that intrigues me is that if all system generator does is to generate vhdl code for the hardware implementation from the z-transform equation(xilinx blocks) then why can't we use that vhdl code and generate the same hardware on cpld. if someonce could throw any light on this issue i'd be highly obliged. or if you know someone who you think might be able to guide me on this please pass me his email address. sincere regards, vishal shahArticle: 59866
Luiz Carlos wrote: > > > This is the classic defense of otherwise indefensible ideas. "They > > said that a flying machine was impossible." "They said that Einstein > > was crazy." Statements like these ignore certain realities, namely: > > > > (a) Much of what was said to be impossible still is, and shows every > > sign of remaining so. If you believe that there are laws of physics, > > even laws that are somewhat at odds with the ones we now hold true, > > then those laws must say that certain things can happen and others > > cannot. If they don't, they aren't laws. > > > > Hi Bob, > Which laws? > Classical physics laws, like every other, have a domain where they > give better approximations. We are still trying to find the Theory Of > Everything. > Peter has mentioned the "Heisenberg's Uncertainty Principle", but I > read somewhere, althought we can't know where a particle is in a > momentum, we can know where it is not, so, we can infer where it is. > If we take the electron spin, there is no metastability. It changes > it's direction in one "fundamental" clock cycle (time is not > continuous). I think there is also no metastability problems in Single > Electron Devices. So, Virtex436 possibly will not have metastability > problems. If you think there is no uncertanty in measuring the spin of an electron, you need to go back to school. You also need to learn the effect of measuring things like spin and other sub-atomic properties, namely changing the state of the quantity being measured. That is what the uncertanty principle is about. When you make a measurement, you change the quantity being measured. Many quantities interact, such as velocity and position, so that measuring one more accurately interferes with measuring the other. The bottom line is that it was quantum mechanics that taught us the limits of measurement. Even though quantum properties are discreet, there is still uncertainty in any measurement. BTW, the position of an electron can be measured, but it really is not in one place like a book. It has a finite probability of being pretty much anywhere and the total of this probability over all space sums to 1. There is a non-zero probability of it being anywhere. So you can't measure "where it is not". -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAXArticle: 59867
Glen Herrmannsfeldt wrote: > > "Richard Iachetta" <iachetta@us.ibm.com> wrote in message > news:MPG.19b83b577df3e40d989823@ausnews.austin.ibm.com... > > In article <rzt3b.288788$uu5.63948@sccrnsc04>, gah@ugcs.caltech.edu > says... > > > I used to hear stories, though I am not sure that I believe them, of > people > > > seeing metastability effects on the PDP-10 (KA10), which used self timed > > > logic. Supposedly they could see it stop processing, and then start > again > > > with no ill effect. How they know it wasn't in I/O wait, or some other > such > > > state, I have no idea. > > > > Sorry for being skeptical, but they "saw" it stop processing for > approximately > > 10 to 100 ns that the metastability would resolve and then they saw it > start > > again? > > Well, I am skeptical, too, but logic was somewhat slower in those days, and > the resolving time may be much longer. Not that logic speed and resolution > time are proportional. Also, the metastability pathways in self-timed > logic are somewhat different. I am no expert in async logic, but I have never heard of a circuit that can even detect metastability. I also thought that async logic did not "measure" the time it took for a calculation, it simply allowed different times for different calculations. The control path for a given circuit has a longer delay than the data path and would be dependant on the calculation being performed. How exactly would a circuit detect when an async calculation is complete? -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAXArticle: 59868
Luiz Carlos wrote: > > But I remember people saying CMOS is slow, copper can't be used as > metal layer, and a better example: "We are reaching the silicon > physical limits"! > > This is a kind of religion, I don't believe in "not possible", only in > "I don't know how to do". This has nothing to do with the problem. There is nothing you can do with gates or noise or voltage to solve it. But to understand that, you need to go beyond these things and consider the problem from a theoretical viewpoint. Take a look at a graph of energy (or voltage) levels of a bi-stable function. If you analyze the behavior of varying amount of energy being applied, you will find that the time it takes to return to one of the minimum energy level states is indeterminate. There is nothing you can do to add gates or noise or voltage, this is a basic property of bi-stable systems... even quantum mechanical ones! -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAXArticle: 59869
Yes, but the 5 volt tolerance is limited to 64 pins. This may or may not be an issue with a given design. John Dimtsios wrote: > > Acutally Lattice does have parts larger that the XCR3512XL. If you > are looking for 256 fpBGA you can get up 768 macrocells in that > package using their ispXPLD family. Not only that but each logic > block can alternately be made into a large memory element so you will > have plenty of room to spare. > > "Neeraj Varma" <neerajNOSPAMM@cg-coreel.com> wrote in message news:<3f2dc715@shknews01>... > > Cypress is anyway getting out of the PLD business... > > http://www.eet.com/semi/news/OEG20030730S0063 > > > > > > "rickman" <spamgoeshere4@yahoo.com> wrote in message > > news:3F2A84FE.20106575@yahoo.com... > > > Marc Randolph wrote: > > > > > > > > rickman <spamgoeshere4@yahoo.com> wrote in message > > news:<3F29C212.EC74896B@yahoo.com>... > > > > > I have been given a very good price on the Coolrunner XCR3512XL, but > > > > > even with 512 macrocells, including small FIFOs (8 bits x 16 words, > > two > > > > > FIFOs) uses up half the chip. > > > > ^^^^^^^^^^^^^ > > > > Unless the design is complete and you can verify that it fits AND you > > > > have a pinout, this would scare the hell out of me. I have to admit > > > > not having used the Coolrunnner, but over the past six years, we have > > > > had an absolutely horrible time making very minor changes to > > > > moderately full 95xxx series Xilinx CPLD's. Again, this may not apply > > > > as much to the Coolrunner, since it is a completely different family - > > > > but I'd still verify it first. > > > > > > > > I agree with the other poster - what about the Cypress or Lattice > > > > devices? I realize that gets you away from your "all Xilinx" board, > > > > but is there really a good reason for desiring that (except maybe you > > > > can get all parts from one distributor)? > > > > > > No, sticking with Xilinx is not a strong desire since the software is > > > not common anyway. But Lattice has nothing that will fit this socket > > > and I have not been able to get a decent price on a Cypress part. I > > > guess that is also part of my goal to use Xilinx. I have gotten some > > > really great pricing on the parts I have discussed with them. They are > > > working with me, so it makes me want to work with them. > > > > > > But I agree that using the XCR3512XL is scaring me as well. That is why > > > I am asking about other Xilinx alternatives. > > > > > > I am sure I looked at the Cypress parts. I need about 170+ IOs in a 256 > > > FBGA. The insides are not real important since that many IOs almost > > > always means a larger part than what I need, say 20,000 gates or 1000 > > > LUT/FF. The memory is optional since with that many FFs I can make my > > > own FIFOs easily. Any idea of what a real price in a Cypress part would > > > run? I don't really see much that will fit the socket unless I am > > > missing something. > > > > > > -- > > > > > > Rick "rickman" Collins > > > > > > rick.collins@XYarius.com > > > Ignore the reply address. To email me use the above address with the XY > > > removed. > > > > > > Arius - A Signal Processing Solutions Company > > > Specializing in DSP and FPGA design URL http://www.arius.com > > > 4 King Ave 301-682-7772 Voice > > > Frederick, MD 21701-3110 301-682-7666 FAX -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAXArticle: 59870
All you need to answer these questions is the equation that describes your metastability. That is contained in most of the references that have been given. The settling time is found in an exponent, so using two FFs with half the time of a single FF will make the problem worse, not better. The best (and only) way to resolve metastability is to provide more time. The probability never goes to zero, but you can get arbitrarily close. Symon wrote: > > Hi, > Before I start, metastability is like death and taxes, > unavoidable! That said, I've read the latest metastability thread. I > thought these points were interesting. > > Firstly, A quote from Peter, who has carried out a most thorough > experimental investigation :- > "I have never seen strange levels or oscillations ( well, 25 years ago > we had TTL oscillations). Metastability just affects the delay on the > Q output." > > Secondly, from Philip's excellent FAQ :- > "Metastable outputs can be > > 1) Oscillations from Voh to Vol, that eventually stop. > 2) Oscillations that occur (and may not even cross) Voh and Vol > 3) A stable signal between Voh and Vol, that eventually resolves. > 4) A signal that transitions to the opposite state of the pre > clock > state, and then some time later (without a clock edge) > transitions > back to the original state. > 5) A signal that transitions to the oposite state later than the > specified clock-to-output delay. > 6) Probably some more that I haven't remembered. " > > So, this got me thinking on the best way to mitigate the effects of > metastability. If Peter is correct in his analysis of his experimental > data, and I've no reason to doubt this, then Philip's option 5) is the > form of metastability appearing in Peter's Xilinx FPGA experiments. > > So, bearing this in mind, a thought experiment. We have an async > input, moving to a synchronising clock domain at (say) 1000MHz. Say we > have a budget of 5ns of latency to mitigate metastability. The sample > is captured after the metastability mitigation circuit (MMC) with a FF > called the output FF. > My first question is, which of these choices of MMC is least likely > to produce metastability at the output FF? > 1) The MMC is a 4 FF long shift register clocked at 1000MHz. > MMC1 : process(clock) > begin > if rising_edge(clock) then > FF1 <= input; > FF2 <= FF1; > FF3 <= FF2; > FF4 <= FF3; > output <= FF4; > end if; > end process; > > 2) The MMC is 4 FFs, each clock enabled every second clock. > MMC2 : process(clock) > begin > if rising_edge(clock) then > toggle <= not toggle; > if toggle = '1' then > FF1 <= input; > FF3 <= FF1; > output <= FF3; > else > FF2 <= input; > FF4 <= FF2; > output <= FF4; > end if; > end if; > end process; > > Option 1) offers extra stages of synchronization between the input > and output, but the 1ns gap between FFs means that metastability is > more likely to propagate. Option 2) waits 2ns for the sample FFs to > make up their mind, vastly decreasing the metastability probability. > My second question is, does the type of metastability, i.e. the > things in Philip's list, affect which is the better choice? For > instance, if the first FF in the MMC exhibits oscillations in > metastability, then the second FF in the MMC would have several > chances, as its input oscillates, to sample at the 'wrong' time. This > might favour MMC option 2). If, however, the first FF in the MMC goes > into option 5) metastability, then there's only one chance for the > second FF to sample at the 'wrong' time. This might confer an > advantage on MMC option 1). > > Anyway, I'm still thinking about this. I think the clock frequency > may decide which is better for a given FF type. Any comments? > Cheers, Syms. -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAXArticle: 59871
Hi, have anyone successfully installed Xilinx Foundation Series 2.1i on Linux? I've tried doing so, but without success. This is what I have done. cd /mnt/cdrom wine setup.exe With the above command executed, a new window with the Xilinx logo appeared and disappeared without doing any installation. The specs of my comp. are as follow: Pentium 3 500 MHz Mandrake 9.1 Thank you.Article: 59872
I think you'd probably be better off just writing the HDL directly from = your Z-transforms. It would be faster and you'd have more control. But = that's a different matter. If you look at the HDL you can tell it it will port to CPLDs. If it is = just RTL source, it should port fine. Most likely, though, it will = instantiate a lot of primitives that aren't available on a CPLD, which = may be another reason to write the source directly. I can't imagine = that SystemGenerator code is highly portable, or it would be portable to = a competitor's part. The main problem you are going to have, though, is that the CPLD just = won't have enough gates to do what you want. The Virtex-II parts have = embedded multipliers for DSP operations, and the other families have = families have hardware to make implementing multipliers easier. = Multipliers may not be feasible on a CPLD. You might only have room for = the smallest of operations. -Kevin "vishal shah" <vishal.shah@asu.edu> wrote in message = news:ee7f822.-1@WebX.sUN8CHnE... Hi,=20 I am working on a project of a dc-dc converter wherein we require to=20 generate hardware implementations from z-transform equations.=20 My fellow researchers are using system generator and simulink to=20 generate hardware implementation from the z-transform equations on=20 FPGAs.(that is they get differential equation in terms of z^-1, z^-2 = etc. for e.g. they realize 1.8*z^-2 using a constant element, a = multiplier and two Z^-1 delay elements)=20 However, I need to implement those z-transform equations on CPLDs.=20 I wonder if i could use system generator for that.=20 but nowhere in xilinx website or system generator documentation is=20 there any mention of CPLDs. everywhere it says that DSP=20 implementation can be done by system generator on FPGAs.=20 however one thing that intrigues me is that if all system generator=20 does is to generate vhdl code for the hardware implementation from=20 the z-transform equation(xilinx blocks) then why can't we use that=20 vhdl code and generate the same hardware on cpld.=20 if someonce could throw any light on this issue i'd be highly obliged. = or if you know someone who you think might be able to guide me on=20 this please pass me his email address.=20 sincere regards,=20 vishal shahArticle: 59873
You don't mention a very important parameter--speed. Depending upon the bandwidth you require you can probably timeslice the MACs, saving hardware. -Kevin "walala" <mizhael@yahoo.com> wrote in message news:bipbje$51c$1@mozo.cc.purdue.edu... > Dear all, > > I want to design an arithmatic datapath unit for digital signal processing > using VHDL and/or Verilog. > > The input are 5 elements(either sequential or parallel) each having 8 bits. > It needs to multiply each of these 5 inputs with a predefined constant > matrix(10x10, floating point scaled and round to integer). The output will > be a 10x10 matrix summing the above five matrices up, each element having 12 > bits). So for each element of the matrix, I can have a MAC unit. The > internal computation will be 16 bits. > > Hence for each 5 inputs x1, x2, x3, x4, x5, the output matrix > > Y=x1*C1+x2*C2+x3*C3+x4*C4+x5*C5 where Y, C1, C2, C3, C4, C5 are matrices; > > If I put an MAC for each element, I will have a purely parallel > architecture, but I need 100 16bits MAC units, which will be too resource > consuming. > > I am considering to make a parallel-serial architecture, at each time, it > outputs one row, which will be 10x12 bits... so the output will be > row-by-row. > > I also need to consider to streamlize the datapath operation. Since there > will be a stream of 5 elements input in a non-stop fashion, the output will > also be non-stop streaming. So after one row is outputted, that row can be > used for computation/storage of the results for the next 5 input elements. > > I am ok so far in thinking... but further thinking makes me confused and > perplexed... how to do sequential timing control(how to what to do at which > cycle)? do I need to pipelining? how to design the architecture? I mean, I > know pipelining theoratically from one semester course, but now I am going > to implement one, I am totally lost... > > Finally, how to program this? Is there any examples for this? > > Please help me! > > Thanks a lot, > > -Walala > >Article: 59874
Hello! I am using the WebPack ( VHDL ) and the 9500 family CPLD. I would like to make a SPI interface. So now I need a VHDL description of an 8 bit parallel-in serial-out shift register with MSB shifting out first. So far I haven't had any luck so I am asking you for help. I thank you in advance for your efforts. Best regards George Mercury
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