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Actually, the xilinx structure can make a very efficient cross bar. One way is
to do a partial reconfiguration to switch the crossbar connections, in which
case it uses mostly just the routing resources, not CLBs. If partial
reconfiguration is not your cup of tea, you can make efficient 4:1 muxes using
SRL16's. These take 16 clocks to reroute, and require a simple loader which can
be shared among many bits, but they are compact and fast.
Glen Herrmannsfeldt wrote:
> "Mario Trams" <Mario.Trams@informatik.tu-chemnitz.de> wrote in message
> news:bj70hb$3j3$1@anderson.hrz.tu-chemnitz.de...
>
> (snip)
>
> > > I see that devices are sold in terms of their gate count. How
> > > efficient is a typical design? For instance, if I want to make a 16 by
> > > 16 CPU controlled crosspoint how many FPGA gates will I need? I can
> > > see that I need 16 OR gates each with 16 AND array inputs for the
> > > output terms, 64 latches to store the selection and some more gates to
> > > do the latch address decoding. Is there any easy way to choose the
> > > right part?
> >
> > That is very difficult to answer. This issue has been discussed sometimes
> > in this newsgroup already, and will probably be discussed again and again.
> >
> > You should never ever draw some conclusions from the gate-count
> > given by the manufacturers. This is just a marketing number.
> > I started with Lucent (now Lattice) ORCA FPGAs and got a feeling
> > what can be put inside. Then I turned to Xilinx Virtex FPGAs (because
> > of the free development software) and got rather shocked how much
> > less one can put into such an FPGA with a comparable gate count.
>
> Well, some designs fit the FPGA model better than others. My guess is that
> a crossbar switch is one that doesn't fit very well, but that is a guess.
>
> > For instance, they include internal RAM-Blocks in the official
> > gate-count number. That gives a shiny value, but is nonsense if
> > you ask me.
> > My guess is that the Xilinx people that are around here in this
> > newsgroup think similar because they are more engineers rather than
> > marketing people.
> > But apart from that, the Xilinx FPGAs are not bad ones.
>
> The traditional CMOS definition for gate count is the number of transistors
> divided by four. It takes four to make a CMOS 2 input NAND gate. RAM
> arrays are included in that count.
>
> (snip)
>
> > Once you got some design software, you might also try to synthesize
> > your design (provided it has been finished already) and try to fit
> > it into different FPGA types. There you will also see how much of
> > the FPGAs' capacity would be used.
>
> This is probably the best way. First, the manufacturer given gate count is
> a maximum, and you should expect somewhat less. There may be a wide
> variation on how much you actually get.
>
> -- glen
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 60076Glen, Do not see why not. The downside is that you need to reconfigure the interconnect to change a cross point, so the update rate is slow. For most traffic bearing circuit switch applications, a few ms to change the x-point is not an issue, but for a packet system it would not be fast enough. A barrel shifter seems like something you would want to update very quickly, and for that, you would probably rather use the multiplier as a barrel shifter. Austin Glen Herrmannsfeldt wrote: > "Austin Lesea" <Austin.Lesea@xilinx.com> wrote in message > news:3F5782D1.746E1D51@xilinx.com... > > All, > > > > I beg to differ. We have not only a good solution, but a great solution: > > > > http://www.xilinx.com/prs_rls/end_markets/02151crossbar.htm > > > > The worlds first FPGA cross bar switch that uses the programmable > interconnect > > as....well, as a corss bar switch! Extremely efficient (able to do > 1024x1024 in > > a 2V6000 at 155 Mbs each wire, non-blocking). > > > > For a really small cross bar, one could use the ICAP with the microblaze > for > > control, and a bram for the patterns....and perhaps only 16 CLBs for a > 16X16 > > non-blocking cross point switch..... > > That does sound pretty neat. I was thinking of it in terms of > synthesizable logic using CLB's. > > Can you do a barrel shifter for floating point > prenormalization/postnormalization that way, too? > > -- glenArticle: 60077
Ralph, Since the virtex architecture is fully buffered (patented), there is no such thing as a bididrectional connection. Austin Ralph Mason wrote: > "Brian Fairchild" <spam.spam@spam.com> wrote in message > news:jhcclv0p5n1628t9s1cdfpthac60ltjub4@4ax.com... > > > efficient is a typical design? For instance, if I want to make a 16 by > > 16 CPU controlled crosspoint how many FPGA gates will I need? I can > > see that I need 16 OR gates each with 16 AND array inputs for the > > output terms, 64 latches to store the selection and some more gates to > > do the latch address decoding. Is there any easy way to choose the > > Just as an academic thing for myself. > > Is a bi-directional crosspoint switch able to be produced with a FPGA? My > understanding is they are a matrix of fets each one having a memory cell to > store it's setting. > > So I would say that it was impossible. Even a fully digital one would still > require that an an I/O pin can be used for input and output at the same > time. > > Can anyone confirm or deny? > > Thanks > RalphArticle: 60078
On a sunny day (Thu, 04 Sep 2003 07:41:43 -0700) it happened Austin Lesea <Austin.Lesea@xilinx.com> wrote in <3F574F27.75C87433@xilinx.com>: >Luiz, > >We have done this, and it works. The question is how well? The answer is that we have never >actually used this in a system where other things are going on as well, and then measured the S/N >of the ADC, resolution, THD, etc. Let us know how it turns out. Better than using Vref and the >input would be to use an LVDS input buffer (as was already pointed out) differentially. You will >only get a good 1V to 1.5V span (where the comparator works the fastest and best), but the >differential input leads to less noise. So with say 10 mV and a 1 V span, is 1 in 100, and that speed, put a R2R on some 8 output pins, and do succesive aproximation to create a video ADC? For a span of 2.5 V you would get 8 bits... That would be usable. At 400Mbs / s in 8 steps would be 50 MHz Do I understand this right? (Non linearity could be corrected in software, maybe the gamma would be good hehe:-) ?Article: 60079
"Ralph Mason" <masonralph_at_yahoo_dot_com@thisisnotarealaddress.com> wrote in message news:<5TL5b.137460$JA5.3292926@news.xtra.co.nz>... > "Brian Fairchild" <spam.spam@spam.com> wrote in message > news:jhcclv0p5n1628t9s1cdfpthac60ltjub4@4ax.com... > > > efficient is a typical design? For instance, if I want to make a 16 by > > 16 CPU controlled crosspoint how many FPGA gates will I need? I can > > see that I need 16 OR gates each with 16 AND array inputs for the > > output terms, 64 latches to store the selection and some more gates to > > do the latch address decoding. Is there any easy way to choose the > > Just as an academic thing for myself. > > Is a bi-directional crosspoint switch able to be produced with a FPGA? My > understanding is they are a matrix of fets each one having a memory cell to > store it's setting. > > So I would say that it was impossible. Even a fully digital one would still > require that an an I/O pin can be used for input and output at the same > time. > > Can anyone confirm or deny? Deny. Crossbars are uni-directional. Now, the REAL relay crossbars used by the telcos upto the 1970s ARE bi-directional.Article: 60080
Jan, You could resolve finer than 10 mV (offset does not equal resolvable step size), so that the resolution is limited more by the noise, and response time. And all of the self-calibraing tricks used in modern ADCs could be used here as well to improve the linearity and the response. Austin Jan Panteltje wrote: > On a sunny day (Thu, 04 Sep 2003 07:41:43 -0700) it happened Austin Lesea > <Austin.Lesea@xilinx.com> wrote in <3F574F27.75C87433@xilinx.com>: > > >Luiz, > > > >We have done this, and it works. The question is how well? The answer is that we have never > >actually used this in a system where other things are going on as well, and then measured the S/N > >of the ADC, resolution, THD, etc. Let us know how it turns out. Better than using Vref and the > >input would be to use an LVDS input buffer (as was already pointed out) differentially. You will > >only get a good 1V to 1.5V span (where the comparator works the fastest and best), but the > >differential input leads to less noise. > So with say 10 mV and a 1 V span, is 1 in 100, and that speed, put a R2R on some 8 output pins, > and do succesive aproximation to create a video ADC? > For a span of 2.5 V you would get 8 bits... That would be usable. > At 400Mbs / s in 8 steps would be 50 MHz > Do I understand this right? > (Non linearity could be corrected in software, maybe the gamma would be good hehe:-) > ?Article: 60081
Hi Austin, Does Xilinx apply hysteresis (as Alvin said) on CLPLD/FPGA inputs (when they are configured as LVTTL, CMOS,... etc, i.e., they don't use that input comparators)? Sorry about the parentheses, I'm trying hard to keep them at just one level! Luiz Carlos.Article: 60082
Tom, Although the x-bar relays were bi-directional, they were only used in a uni-directional fashion for toll switching (full duplex four wire). The only bidirectional metallic stage was the first level concentrator for the phone lines to the subscribers with the x-bar 5 WeCo Class 5 office. After that, the circuits were separated into transmit and receive. The older Strowger step by step relays were bidirectional switching from subsrciber to subscriber, and four wire for toll circuits. Telco lore bonus question: why is positive ground battery used in telecom? Inter-office tie trunk tivia: a revertive dial trunk line would dial the foreign office by initiating the call, and telling the foreign office to start dialing. When the foreign office had dialed the right number of digits, the local office would signal it to stop, and go on to the next digit. Extra point question: which class 5 local electronic office switch was demanded by a PUC/PSC to be removed from service due to incredibly poor performance? What state's PUC/PSC? Austin Tom Seim wrote: > "Ralph Mason" <masonralph_at_yahoo_dot_com@thisisnotarealaddress.com> wrote in message news:<5TL5b.137460$JA5.3292926@news.xtra.co.nz>... > > "Brian Fairchild" <spam.spam@spam.com> wrote in message > > news:jhcclv0p5n1628t9s1cdfpthac60ltjub4@4ax.com... > > > > > efficient is a typical design? For instance, if I want to make a 16 by > > > 16 CPU controlled crosspoint how many FPGA gates will I need? I can > > > see that I need 16 OR gates each with 16 AND array inputs for the > > > output terms, 64 latches to store the selection and some more gates to > > > do the latch address decoding. Is there any easy way to choose the > > > > Just as an academic thing for myself. > > > > Is a bi-directional crosspoint switch able to be produced with a FPGA? My > > understanding is they are a matrix of fets each one having a memory cell to > > store it's setting. > > > > So I would say that it was impossible. Even a fully digital one would still > > require that an an I/O pin can be used for input and output at the same > > time. > > > > Can anyone confirm or deny? > > Deny. > > Crossbars are uni-directional. Now, the REAL relay crossbars used by > the telcos upto the 1970s ARE bi-directional.Article: 60083
Jim Granville wrote:
> Very interesting account
Yes. Great story.
My old story involves *missing* a synchronizer
rather than having failures *in* a synchronizer.
At least I didn't have to wait two months
for symptoms to occur in that case :)
-- Mike Treseler
Article: 60084soar2morrow@yahoo.com (Tom Seim) writes: > > I have seen very few references in the literature to the sliding FFT; > if anyone is interested I can send the copy > > of an IEEE paper about it. > > What is the IEEE reference (i.e. journal, date & title)? > > Tom Farhang-Boroujeny, B and Y C Lim, .A comment on the computational complexity of sliding FFT.. IEEE Transactions on Circuits and Systems, 39, no. 12 (December 1992): 875-876. Farhang-Boroujeny, B and S Gazor, .Generalized sliding FFT and its application to implementation of block LMS adaptive filters.. IEEE Transactions on Signal Processing (March 1994): 532-538. These papers can be downloaded from the author's web page at http://www2.elen.utah.edu/~farhang I have seen an EDN article (also cited in the first paper above) cited several times, but the EDN web site does not carry it. -ArrigoArticle: 60085
Luiz, All I know is that Virtex II and II Pro both have hysteresis on the LVCMOS/LVTTL single ended input buffer. It is always there, and can not be turned off. It is about 100 mV. I know that in some of our CPLDs you have an attribute you can turn on and off for hysteresis..... The comparators in VII, VII Pro do not have hysteresis (SSTL. HSTL, LVDS). Don't remember the answers for Virtex, Virtex E, Spartan II or Spartan IIE, a search of the answers database might turn them up Austin Luiz Carlos wrote: > Hi Austin, > > Does Xilinx apply hysteresis (as Alvin said) on CLPLD/FPGA inputs > (when they are configured as LVTTL, CMOS,... etc, i.e., they don't use > that input comparators)? > > Sorry about the parentheses, I'm trying hard to keep them at just one > level! > > Luiz Carlos.Article: 60086
Austin Lesea wrote: > > All, > > I beg to differ. We have not only a good solution, but a great solution: > > http://www.xilinx.com/prs_rls/end_markets/02151crossbar.htm > > The worlds first FPGA cross bar switch that uses the programmable interconnect > as....well, as a corss bar switch! Extremely efficient (able to do 1024x1024 in > a 2V6000 at 155 Mbs each wire, non-blocking). > > For a really small cross bar, one could use the ICAP with the microblaze for > control, and a bram for the patterns....and perhaps only 16 CLBs for a 16X16 > non-blocking cross point switch..... So this partial reconfig, is clever enough that a portion of the FPGA can keep running, while the rest is respun - or would what you describe above need two FPGA ? -jgArticle: 60089
"Ralph Mason" <masonralph_at_yahoo_dot_com@thisisnotarealaddress.com> wrote in message news:<5TL5b.137460$JA5.3292926@news.xtra.co.nz>... > "Brian Fairchild" <spam.spam@spam.com> wrote in message > news:jhcclv0p5n1628t9s1cdfpthac60ltjub4@4ax.com... > > > efficient is a typical design? For instance, if I want to make a 16 by > > 16 CPU controlled crosspoint how many FPGA gates will I need? I can > > see that I need 16 OR gates each with 16 AND array inputs for the > > output terms, 64 latches to store the selection and some more gates to > > do the latch address decoding. Is there any easy way to choose the > > Just as an academic thing for myself. > > Is a bi-directional crosspoint switch able to be produced with a FPGA? My > understanding is they are a matrix of fets each one having a memory cell to > store it's setting. > > So I would say that it was impossible. Even a fully digital one would still > require that an an I/O pin can be used for input and output at the same > time. > > Can anyone confirm or deny? > > Thanks > Ralph But thats exactly what an FPGA is only the latch data that control the cross switches are in your bit file. For the particular crossbar mentioned, the whole device would have to be fully or partially reprogrammed on the fly. if the lines stay connected for long enough, the difficulty of reconfiguring is justifed. If this RC approach hadn't been available ie fused/eeprom FPGA etc, then the density & speed would be orders lowers. Probably the single sneakiest best use of RC I heard of so far. JJArticle: 60091
On Thu, 04 Sep 2003 14:32:15 -0700, Austin Lesea <Austin.Lesea@xilinx.com> wrote: >Tom, > >Although the x-bar relays were bi-directional, they were only used in a uni-directional fashion for toll switching (full duplex four wire). >The only bidirectional metallic stage was the first level concentrator for the phone lines to the subscribers with the x-bar 5 WeCo Class 5 >office. After that, the circuits were separated into transmit and receive. > >The older Strowger step by step relays were bidirectional switching from subsrciber to subscriber, and four wire for toll circuits. > >Telco lore bonus question: why is positive ground battery used in telecom? The voltage is negative with respect to ground to help reduce corrosion problems. -48V is the standard voltage used in phone exchanges. (Actually it's more like -52V when float charging, but you get the idea.) (ETSI standard ETS 300 132-2 says -40,5 to -57,0 Vdc at the equipment input. A "slight degradation in performance" may exist for voltages in the range -40,5 to -44,0 Vdc. Telcordia will have similar specs.) The magnitude of the voltage is 48V because that voltage is a good compromise between a number of factors, one major one being the ability to drive enough power down a long (high resistance) line to the phone. Really old phone exchanges needed a certain loop current to activate the hook relay. ISDN lines are usually biased at a higher voltage which can be up to 120V (max allowable for TNV), as the ISDN equipment needs more power. Note that some areas use -60V (= 5 x 12V) for POTS. Regards, Allan. >Inter-office tie trunk tivia: a revertive dial trunk line would dial the foreign office by initiating the call, and telling the foreign >office to start dialing. When the foreign office had dialed the right number of digits, the local office would signal it to stop, and go on >to the next digit. > >Extra point question: which class 5 local electronic office switch was demanded by a PUC/PSC to be removed from service due to incredibly >poor performance? What state's PUC/PSC? > >Austin > >Tom Seim wrote: > >> "Ralph Mason" <masonralph_at_yahoo_dot_com@thisisnotarealaddress.com> wrote in message news:<5TL5b.137460$JA5.3292926@news.xtra.co.nz>... >> > "Brian Fairchild" <spam.spam@spam.com> wrote in message >> > news:jhcclv0p5n1628t9s1cdfpthac60ltjub4@4ax.com... >> > >> > > efficient is a typical design? For instance, if I want to make a 16 by >> > > 16 CPU controlled crosspoint how many FPGA gates will I need? I can >> > > see that I need 16 OR gates each with 16 AND array inputs for the >> > > output terms, 64 latches to store the selection and some more gates to >> > > do the latch address decoding. Is there any easy way to choose the >> > >> > Just as an academic thing for myself. >> > >> > Is a bi-directional crosspoint switch able to be produced with a FPGA? My >> > understanding is they are a matrix of fets each one having a memory cell to >> > store it's setting. >> > >> > So I would say that it was impossible. Even a fully digital one would still >> > require that an an I/O pin can be used for input and output at the same >> > time. >> > >> > Can anyone confirm or deny? >> >> Deny. >> >> Crossbars are uni-directional. Now, the REAL relay crossbars used by >> the telcos upto the 1970s ARE bi-directional.Article: 60092
Jim Granville wrote: > Austin Lesea wrote: > >>All, >> >>I beg to differ. We have not only a good solution, but a great solution: >> >>http://www.xilinx.com/prs_rls/end_markets/02151crossbar.htm >> >>The worlds first FPGA cross bar switch that uses the programmable interconnect >>as....well, as a corss bar switch! Extremely efficient (able to do 1024x1024 in >>a 2V6000 at 155 Mbs each wire, non-blocking). >> >>For a really small cross bar, one could use the ICAP with the microblaze for >>control, and a bram for the patterns....and perhaps only 16 CLBs for a 16X16 >>non-blocking cross point switch..... > > > So this partial reconfig, is clever enough that a portion of the FPGA > can keep running, while the rest is respun - or would what you describe > above > need two FPGA ? As far as I'm aware this FPGA cross bar requires an external controller, not even an FPGA I think they use a PC running JBITS and so on. the fun starts when you have a microblaze on the FPGA that is controlling the dynamic reconfig of the rest of the chip while it keeps running.... ICAP makes this possible. one of my crazier ideas now that I have uclinux running on microblaze is to include a java virtual machine running under uclinux (already done on non-microblaze targets, minimal porting effort required) then you could run JBits on the microblaze, and use it to reconfigure itself..... so many ideas, so little time! :) johnArticle: 60093
Jon Elson <elson@pico-systems.com> wrote in message news:<3F56CE61.5010802@pico-systems.com>... > peterzhu wrote: > > >Due to a chip bug, I have to extend a pulse width(negative)from 10ns > >to 100ms in CPLD(Altera 7128). But the difficult is that I have no any > >clock into the CPLD, so the CPLD is pure combination logic. how to > >extend it in such case? > > > >Help me! > > > > > I have delayed strobe signals several hundred nS with an external series > resistor, and used the input capacitance of the chip as the C of the RC > network. For mS, you will need an external capacitor, of course. if you > want the delay to be asymmetric (like a one-shot), you might need to > put a diode in parallel with the R. You feed the signal out one pin, > through a series R, to a pin loaded with a cap to ground, and then take > the signal in from that pin. This may cause multiple pulses with a > delay this long, however. So, you might end up using a 74HC4538 > or similar one shot, or a 74HC14 Schmitt trigger to prevent the > pulses as the output of the RC crosses the threshold. > > Jon The board is in production, so I can not change the SCH and PCB, all things should be done in CPLD. PeterArticle: 60094
thankx for the help, but you got it wrong. I dont want a configuration solution, I'm looking for something in which I can store my application data/parameters which will be overwritten if changed and stored for further use. That means I want a device which I can read from and write to without loosing the data on power down. Hope this makes my problem clear. I'm looking for suggestions of any particular manufacturer/family of devices for the same. Thanks and regards RamArticle: 60095
"Ray Andraka" <ray@andraka.com> wrote in message news:3F579ECC.D5C92BF@andraka.com... > Actually, the xilinx structure can make a very efficient cross bar. One way is > to do a partial reconfiguration to switch the crossbar connections, in which > case it uses mostly just the routing resources, not CLBs. If partial > reconfiguration is not your cup of tea, you can make efficient 4:1 muxes using > SRL16's. These take 16 clocks to reroute, and require a simple loader which can > be shared among many bits, but they are compact and fast. A subject that comes up reasonably often is doing floating point arithmetic in FPGA's. For example, as a systolic array. The prenormalization/postnormalization for floating point add/subtract, using barrel shifters in CLB's are so big that it is just about impractical. I was considering the crossbar switch as an array of muxes, which would also be huge. I do believe that reconfiguration is too slow for floating point normalization, but maybe the SRL16's. There is something called block floating point (I have never used it) where you have a whole array that has one characteristic but different mantissa for each element. (Apparently very useful for some algorithms.) In that case, the 16 clocks to load the SRL16's might be fast enough for a whole array of numbers. Post normalization could still be a problem, though. -- glenArticle: 60096
You could take two cascaded flip-flops, feed the first with '1' and use your 10 ns strobe as async reset for both. Take a 100 ms (10 Hz) clock or clock enable signal for the FFs and combine both outputs to a 100 ms strobe. Regards, Stephan FlockArticle: 60097
"Yves Deweerdt" <yves@news.be> wrote in message news:3F57018B.7010303@news.be... > Hello Brian, > > Take a look at these: > http://www.digilentinc.com/Catalog/digilab_2e.html > http://www.digilentinc.com/Catalog/peripheral_boards.html > > To start experimenting you'll need a System Board and one of the > peripheral boards. > The Spartan2e on this board has 200K gates, for your design it should be > way too big... to give you an idea of what you can get into it, take a > look at the list of applications they give at the Xilinx ip center. > > Good luck > > Yves I have Digilab 2E lying around that I use for prototyping. It's nice because there isn't a lot of fluff, just some programming hardware, voltage regulators, oscillator, EEPROM socket, and easy-access connectors around the whole board. It may be tempting to just poke wires into the connectors...don't! I got away with it for quite a while, until one of my unbuffered/isolated wires crossed a power supply and toasted the Spartan. I had to desolder it and plunk on a new one this week. Fortunately that particular chip costs only $25 from Digikey. Better than $120 for a new Digilent board! They do use a 2.5V supply for the 1.8V chip, fortunately the supply range is fairly flexible.Article: 60098
Hi, What FPGA architecture is more suitable for the Robots, which involves Pattern recognition (also partial configuration & more than 150k) and lot of control logic generation. Or, Is DSP prefferable for this? Regards, Valli.Article: 60099
Thanks for the response Antti. In article <80a3aea5.0309042231.94b72c@posting.google.com>, antti@case2000.com says... > solutions: for Flex 6K, use cheap serial eeprom (ISSI or other) and cheap > 8 pin microcontroller to boot up the serial eeprom, hmm for some smaller > densities some serial eeproms could be used without that micro also, > there was a mailing about this here some time ago Yes, I guess I'll have to investigate those more indepth. > > use parallal flash and cheap pld to config > use some micro with enough internal flash to get the config Phyiscal space is a big problem in this case, otherwise a cheap FlashROM and uC would do the trick perfectly. > use some other part - this is probably best solution. > there are many FPGAs in tqfp 100 and some should be cheap as well > APA075 is 17USD qty one (non volatile FPGA, no confi mem) > small XC2S are about 9USD qty 1 > hm not sure if cyclone comes in tqgp100 > > but really if there is no special reason to use flex 6k DO NOT USE it I am limited by two factors: 1. FPGA must *run* on 3.3V (not just be 3.3V compliant) 2. FPGA should be in 100-pin TQFP or smaller (smaller the better, without resorting to BGA / CSP) While most of the FPGAs have 3.3V I/O, they run on <=2.5V , which I can't accomodate. The APA075 looks good but it also needs a 2.5V VDD. As an aside, are the software design tools for the APA075 free/cheap , and what distributor did you get the pricing from? Thanks! Jay.
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