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"GB" <donotspam_grantbt@jps.net> wrote in message news:<GFJ6b.2610$PE6.1782@newsread3.news.pas.earthlink.net>... > "hamilton" <hamilton@deminsional.com> wrote in message > news:3f5b561c_3@omega.dimensional.com... > > > What image sensor chip are you looking at ??? > > > > That's another undecided at this time, but CMOS most likely. > > GB Until recently I was under the impression that CMOS sensors were junk and were of low resolution & quality typically 320.240 used in $0-50 cameras. I have an old Connectix webcam device thats is all green that demonstrates that. Recently though a Micron engineer persuaded me that CMOS is looking very much up and showed me some upcoming sensors for both high resolution & higher quality still not quite as good as CCD but far cheaper to make & potentially far easy to integrate with externl interfaces. If the quality is there, I would expect USB2/FW to end up on chip. I will wait and see if they show up in the mid range cameras coming soon. But check out their imaging division for specs if you care.Article: 60201
Uwe Bonnes <bon@elektron.ikp.physik.tu-darmstadt.de> wrote in message news:<bjg8q5$lh3$1@news.tu-darmstadt.de>... > rider <shabana_rizvi@yahoo.com> wrote: > : Hi! > : I have to redesign a TTL based design of discere components into an > : FPGA. I have selected spartan 2 xc2s150. I have a few queries > : regarding the board design. > > : 1) I want my Inputs to be 5V tolerant..which input standard should i > : use...LVTTL or PCI_5V ? How to select any of these standards as both > : require VCCO=3.3V and No Vref or VTT...? > > LVTTL > > : 2)If any of my xc2s150 ouput pin is an open collector, can i pull it > : up externally by 5V through a resistor? > > Yes. > > For speed reasons, use it as tri-state totem pole. First pull it up > internally, then switch to tristate to activate the 5V pull-up resistor. > There's a Xilinx appnote out there about that. > > : 3)I am intending to use a Level shifter IC(3.3V to 5V) at some FPGA > : outputs..is it OK to do so? > > If 2) isn't enough, you can do so. > > : 4)I dont have a global set/reset in the design, can it create problems > : at startup? > You don't need to use it, if you don't need the functionality > > : 5)What should i do of un-used pins of FPGA...can i keep them > : unconnected? > > Define them as inputs with the "keeper" attribute, leave them > unconected. That will make reuse easier. > > : Thanks for everyone's support. > > You're welcome Thanks Uwe! I am using the JTAG-Master Serial Mode for FPGA configuration(Platform Flash). However i want to keep an other programming option. Can you suggest me some third party PROM which is DIP(so that i can program it with my HI-LO ALL 11 programmer)and is compatible to XC2S150 (i.e. supports the Master serial mode with appropriate pins?). I would be grateful. RiderArticle: 60202
I want to start with Xilinx FPGA's. How does one start cheap? I see a development kit from Digilent for $99 US. It is for a Spartan IIE. But then I see there is a Spartan III but no development kit for this. What are the options. Can the Spartan IIE 200K gate do a lot of designs. Is that enough gates? -- Yours sincerely, Bobi Mageroski Practel Pty. Ltd. Tel: 61 2 9957 1797 Fax: 61 2 9957 2892 e-mail: bobi.mageroski@practel.com.au www.practel.com.au ----------------------------------------------------------------- Important Notice: This email is for the named recipient only. Its contents are confidential. If you are not the authorised recipient you must not use, disclose or copy any of these contents. If you receive this email in error please contact us immediately and delete the email from your system. -----------------------------------------------------------------Article: 60203
Hi Mr. Elson, I'd like to assure you that the Spartan XCSxxx FPGAs are very much in full volume production and available through various Xilinx sales partners. Based on your return E-mail, I'm guessing that you are based in the U.S. I checked the web sites for two of our three U.S. distributors and the two I checked showed that they had stock of the devices that you mentioned. The pricing through some of these folks is high for small quantity (< 10). Also, you might find better availability of the -4 speed grade instead of the -3. Xilinx North American Distributors http://www.xilinx.com/company/sales/na_disti.htm I also checked DigiKey (www.digikey.com), which also offers some Xilinx devices. They have the XC3S10-3PC84s but it looks like they have a minimum order of 30. It also appears that they have the XC3S30s, but on in the -4 speed grade. Spartan XCSxxx FPGAs are an older product line so not every part/package/speed grade combination may be in distributor inventory. But, if they don't have it in stock, they can easily obtain it with relatively short leadtimes. If you are still having sourcing problems, please let me know. I can put you in touch with our local sales team. I just need to know your location. -------------------------------- Steven K. Knapp Applications Manager, Xilinx Inc. Spartan-3/II/IIE FPGAs http://www.xilinx.com/spartan3 --------------------------------- Spartan-3: Make it Your ASIC "Jon Elson" <elson@pico-systems.com> wrote in message news:3F58C665.4070503@pico-systems.com... > Hello, > > What is the status of the old, 5V Spartan family from Xilinx? > I have 2 current products that use them. (XCS10-3PC84 and > XCS30-3TQ144) I suddenly noticed all the distributors either > no longer list these parts or indicate they are special order. > Newark has a part that matches the part number, but lists > the manufacturer as Mux-Lab Inc, and the price is outrageous, > $42.48, with no discount at any quantity. I got them just a couple > of months ago for $16 in small quantity. > > I was assured by somebody at Xilinx, possibly Peter Alfke, that > the 5 V Spartan line would continue to be available for a long > time. I suppose if they sold off the masks to an obsolete chip > supplier, that is "still available". > > Jon >Article: 60204
You might try the Microchip web site (www.microchip.com). The closest newsgroup is probably comp.arch.embedded. --------------------------------- Steven K. Knapp Applications Manager, Xilinx Inc. Spartan-3/II/IIE FPGAs http://www.xilinx.com/spartan3 --------------------------------- Spartan-3: Make it Your ASIC "Peter Scheuter" <peter3@mindspring.com> wrote in message news:34N6b.2903$Yt.1101@newsread4.news.pas.earthlink.net... > Hello, > Is this a group for getting help for programming PIC's (16F84A) > Thanks > Peter > >Article: 60205
The worst-case delay in a 18-bit x18-bit =36-bit multiply is from bit 0 of the input to bit 35 of the product. Using the -4 speed grade, which is the slowest, this delay is reported as 7.98 ns. If your application can tolerate a few clock cycles of extra latency, then you can fully pipeline the multiplier (registered input, pipelined multiplier, registered output) and operate at ~150 MHz using the techniques described in application note XAPP636. Here are two application note references that may be of interest. XAPP467: Using Embedded Multipliers in Spartan-3 FPGAs http://www.xilinx.com/xapp/xapp467.pdf XAPP636: Optimal Pipelining of the I/O Ports of Virtex-II Multipliers http://www.xilinx.com/xapp/xapp636.pdf --------------------------------- Steven K. Knapp Applications Manager, Xilinx Inc. Spartan-3/II/IIE FPGAs http://www.xilinx.com/spartan3 --------------------------------- Spartan-3: Make it Your ASIC "Theron Hicks" <hicksthe@egr.msu.edu> wrote in message news:bjfpov$278v$1@msunews.cl.msu.edu... > Hello, > Can anyone give me an approximate time for an 18 by 18 multiply using > the spartan3. I cannot seem to find a specification for this in the data > sheet. I realize that the time is a function of the number of bits. Also, > I assume that this multiplier is not clocked. In otherwords, does the value > eventually ripple through to the output, or is this system in some fashion > clocked. An input latch is quite acceptable, I just would rather not deal > with a clocked delay through the multiplier. > Thanks, > Theron > >Article: 60206
"bobi" <bobi@nospam.com> wrote in message news:bjgu0n$2i9j$1@otis.netspace.net.au... > I want to start with Xilinx FPGA's. How does one start cheap? I see a > development kit from Digilent for $99 US. > It is for a Spartan IIE. But then I see there is a Spartan III but no > development kit for this. > > What are the options. Can the Spartan IIE 200K gate do a lot of designs. Is > that enough gates? For starting out, that's a more than adequate number of gates. It'll work out for most mid-range tasks as well. Only when you need to develop designs requiring very large amounts of bandwidth and processing will you need to move to a Virtex-type system, and by then you'll probably be able to afford the price tag. Note that the Spartan II family is currently about the limit to the devices supported by the free Xilinx development tools, in order to work with the full range of Virtex devices you'll spend up to $2,000 per year to license the software. The Digilent kit is a good investment, for the price. I have one of those exact boards, actually. Good for random tasks and concept designs. Pay attention to the interfacing so you don't burn the FPGA out. If you want to wait for the Spartan III dev boards to come out, then you can. But there isn't going to be a fundamental difference in the way you program it, or even the way it performs. Just about any FPGA board you can get your hands on will be a useful learning tool, even if it's 50,000 gates.Article: 60207
Hello Daniel, it sounds like you forgot to lock the LUT with the LOCK_PINS constraint in the ucf file. Without that NgdBuild or the Mapper replaces your LUT with its 'own' global logic. ChristianArticle: 60208
Jay <se10110@yahoo.com> writes: > Hi Martin, > > Thanks for your response. > > In article <uy8x3ya5r.fsf@trw.com>, martin.j.thompson@trw says... > > Jay <se10110@yahoo.com> writes: > > > > > I'm investigation configuration PROMs for a EPF6010A (FLEX 6K). It looks > > > like the default choice is the EPC1441 which is not ISP or Flash. > > > > > > Altera makes the EPC2 which is Flash/ISP but for some reason it's not > > > compatible with FLEX6K. Anyone know why? Any way to get it to work with > > > the EPF6010A? > > > > > > > I used one a long time ago with a 6016A, worked fine. What makes you > > think they won't work? > > Are you sure it was an EPC2? > Yep, I reprogrammed it and everything! > They make mention several times not to use it on the Flex 6K family: > > http://www.altera.com/literature/ds/dsconf.pdf , page 9, note 1: > > "Do not use EPC2 devices to configure FLEX 6000 devices." , and again on > page 12, etc. > So they do, I hadnot noticed that! I was going on the fact that they "seemed" to be compatible with the older EPC1x series in terms of pinout and timing. Indeed, table 5 is entitled "Table 4. APEX 20K, FLEX 10K & FLEX 6000 Timing Parameters using EPC2 Devices at 3.3 V" > I'm wondering why the Altera guys haven't followed up in the NG, they > seem to be pretty attentive as of late. > Yeah, they would have the "right" answer, but I can certainly say it worked for us. We made a few of these boxes, and some of them ended up on the front of cars, and I never had any complaints. > > The Altera ones were about 20UKP last time I bought them. :-( > > That doesn't sound too promising. How much were you paying for the > EPF6016As, if I might ask? > Sorry, Ijust poked around our Purchase database and can't find any record of them. I think we must have bought them from a different supplier to usual :-( The EPC2s were there though, 18UKP. Hope you get some official answers! Cheers, Martin -- martin.j.thompson@trw.com TRW Conekt, Solihull, UK http://www.trw.com/conektArticle: 60209
Jay <se10110@yahoo.com> writes: > Just to follow up a bit on my own thread, the "cheap" ISP alternative > wasn't from ISSI, it was from SST. Here's the Google thread: > > http://tinyurl.com/mbjl > Just in case tinyurl ever goes away, here's the very long link split over sveral lines, for the benfit of future generations :-) http://www.google.com/groups?hl=en&lr=&ie=UTF-8&oe=UTF-8& threadm=pan.2003.03.17.13.09.48.115606.23961%40 freeby.mesanet.com&rnum=8&prev=/groups%3Fq%3DEEPROM%2B group:comp.arch.fpga%26hl%3Den%26lr%3D%26ie%3DUTF-8%26oe%3D UTF-8%26selm%3Dpan.2003.03.17.13.09.48.115606.23961 %2540freeby.mesanet.com%26rnum%3D8 -- martin.j.thompson@trw.com TRW Conekt, Solihull, UK http://www.trw.com/conektArticle: 60210
"Peter Scheuter" <peter3@mindspring.com> wrote in message news:34N6b.2903$Yt.1101@newsread4.news.pas.earthlink.net... > Hello, > Is this a group for getting help for programming PIC's (16F84A) No, you should join the PIClist; http://www.piclist.com/techref/piclist/index.htm LeonArticle: 60211
Hi all,
I am doing a project and using Altera Nios Development kit with Stratix
Edition. I need to connect a serial/PS/2 mouse to that board . But the board
can't get any signal from the mouse, anyone has this experience can share
with me?I have already set the UART 2 to 1200 baud rate.
Thank you very much.
San
Article: 60212When programming an XC18V04 I get a red "Programming Failed" indicator at the end of the process. The device is connected to an XC2V1000 in SelectMAP mode. I tried disabling "FPGA Load" but nothing changed. I should mention that the boards come-up just fine, in other words, it seems that the programming of the PROM is successful every single time, despite the message. The log file doesn't have any useful information. Can anyone suggest where I might look to figure this out? Thanks, -- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ Martin Euredjian To send private email: 0_0_0_0_@pacbell.net where "0_0_0_0_" = "martineu"Article: 60213
Hello, i looking for a SJA1000 or compatible IP-Core for an Spartan-II. There are other's Sources as Xilinx-Core program or Opencores? thanks, DanielArticle: 60214
hi, I'm looking for something in which I can store my application data/parameters which will be overwritten if changed and stored for further use. That means I want a device which I can read from and write to without loosing the data on power down. I'm looking for suggestions of any particular manufacturer/family of devices for the same. Thanks and regards RamArticle: 60215
"bobi" <bobi@nospam.com> wrote in message news:<bjgu0n$2i9j$1@otis.netspace.net.au>... > I want to start with Xilinx FPGA's. How does one start cheap? I see a > development kit from Digilent for $99 US. > It is for a Spartan IIE. But then I see there is a Spartan III but no > development kit for this. Memec had Spartan III S50J kits but those are all sold out :( also notice that did use "J" version with only 2.5 IO and no BRAM more S3 kits from Memec are exptected but timeline unknown > What are the options. Can the Spartan IIE 200K gate do a lot of designs. Is > that enough gates? thats a lot and pretty much enough :) anttiArticle: 60216
I went around the irregularity issue by having sub-multiplier block architecture that has have fixed interface to the routing and have fixed (yet reasonable) area. Therefore, when the coefficients are changed, no place and route is required and the latency remains the same (unless you change the number taps). The generation of coefficients can done at reconfiguration time thanks to symmetry in the FPGA used (Atmel 40K40). Naturally, there is the problem of hassling with run-time reconfiguration and everything that comes with that... As part of this work we looked also into common subexpression sharing in that particular FPGA family and found it very unlikely that benefits could be obtained with similar multiplier-block architecture. This is mainly due the fact that it is different story to be able to generate the most useful common subexpressions that it is to really use them before the routing becomes congested. http://www.doc.ic.ac.uk/~tpr/papers/rissa_FPT02.pdf T.Rissa Ray Andraka <ray@andraka.com> wrote: > I agree the multiplier block style filters are more efficient area-wise. It > sounds like you have addressed the irregularity issues by using a program > to do the generation, which I think is pretty much a necessity. As I thought > I alluded to, the biggest problem with multiplier block filters is that the > layout/size is not a constant if you change the coefficients. This means that > the fiter coefficients have to be constant and known earlier in the design > cycle, and necessitates a rerun of synthesis, place and route for any filter > changes. Depending on the implementation, it may also mean a change in the > filter's pipeline latency. These factors can make them difficult to use on > some projects. The filters typically used in my projects often need to be > adjusted by the customer or late in the project to accommodate minor > requirements changes. I prefer to use a filter with reloadable coefficients > for that reason. > Ken wrote: >> Ray, >> >> I sent this to Michael via email and he suggested the group would be >> interested also... >> >> My PhD (now drawing to the end) has been on implementing full-parallel >> Transpose FIR filters using multiplier blocks that you mention (I use >> techniques/algorithms that exceed the efficiency of CSD in terms of FPGA >> area). >> >> The upshot of my work is that I have written a C++ program that will >> generate RTL VHDL given the quantised filter coefficients, the type of >> filter required (singlerate, interpolation, decimation etc.) and the >> appropriate parameters (input width, signed/unsigned input, number of >> channels, rate-change factor etc.) >> >> The VHDL my program generates exceeds the functionality (at a lower >> cost) of that provided by Xilinx's Distributed Arithmetic core and Altera's >> FIR Compiler (also DA). In fact, my program allows interpolation and >> decimation factors up to the number of filter coefficients and any number of >> data channels (for interpolation/decimation filters also). >> >> The main point is that, once synthesised and mapped to a specific FPGA, the >> filters my program generates require far less FPGA area (slices/logic cells) >> than those generated using Distributed Arithmetic. The critical path in my >> filters is just the longest adder carry chain so very high speeds are >> possible. E.g. 154MHz for a singlerate filter (25 bit output) in a Xilinx >> xc2v3000-fg676-5 - obviously the speed will depend on the device >> family/speed grade and the longest carry chain. The facility for multiple >> channels in interpolation/decimation filters (not supported by Xilinx) >> allows lower than full-parallel sampling rates to be efficiently processed >> in one filter. >> >> As Michael points out in his post, this technique would be very suitable for >> a >> Xilinx Spartan-IIE and indeed any FPGA - there are many cases where these >> filters would be useful even on devices with dedicated multipliers (when >> they are all in use for example! ;-) ). >> >> You can find out more at http://www.dspec.org/rsg.asp - there are also >> datasheets here that provide comparisons with Xilinx and Altera and >> demonstrate the output of another application (written in java) that >> generates schematic representations of the filters for use in reports, >> meetings and thesises! :-) >> >> I hope this information is of use to you - please contact me if you have any >> questions, >> >> Thanks for your time, >> >> Ken >> >> -- >> To reply by email, please remove the _MENOWANTSPAM from my email address. >> >> "Ray Andraka" <ray@andraka.com> wrote in message >> news:3F54F936.5E694FD1@andraka.com... >> > The problem with the multiplier block approach is that the >> > construction is predicated on the specific coefficients. As >> > a result it is considerably harder to use for an arbitrary >> > set of coefficients. It may reduce area over a straight FIR >> > filter running at the same clocks per sample, but at a >> > considerable cost in design time and flexibility. You also >> > give up regularity in the structure, which may reduce the >> > overall performance. Essentially what the block multiplier >> > and distributed arithmetic approaches are is a rearrangement >> > of the bitwise product terms. The mutliplier block takes >> > advantage of duplicate terms by adding the inputs before >> > they are multiplied by the term. >> > >> > Michael Spencer wrote: >> > >> > > Hello, >> > > >> > > Has anyone compared FPGA implementations of full-rate >> > > digital FIR filters based on the use of Multiplier Blocks >> > > vs. traditional FIRs with constant coefficient >> > > multipliers? By full rate, I mean: one output result per >> > > clock cycle and no interpolation or decimation. >> > > >> > > For anyone not familiar, a multiplier block is a network >> > > of shifters and adders that performs multiplications by >> > > several coefficients efficiently by exploiting common >> > > sub-expressions. The multiplier block can be exploited in >> > > FIR filters by transposing the standard filter so that the >> > > products of all the coefficients with the current >> > > input-sample are required simultaneously. >> > > >> > > Also, by representing the coefficients in the >> > > Canonical-Signed-Digit number system (a small number of >> > > +1 and -1's) along common sub-expression sharing the >> > > multiplier block can get even smaller. >> > > >> > > For example, the multiplier block for a 100 tap FIR filter >> > > (fp=0.10 and fs=0.12) can be realized with only 61 adds >> > > (zero explicit multiplications). See filter example #4 in >> > > "FIR Filter Synthesis Algorithms for Minimizing the Delay >> > > and the Number of Adders," >> > > http://ics.kaist.ac.kr/~dk/papers/TCAD2001.pdf >> > > If the adder depth is constrained to a maximum of four, >> > > then the authors' algorithm can do the multiplier block in >> > > 69 additions. >> > > >> > > It would seem that this approach would be very efficient >> > > in a target such as the Xilinx Spartan-IIE (with no >> > > dedicated multipliers). >> > > >> > > Another question: If we only need one result per K clock >> > > periods (K ~= 1000 for audio applications), could a >> > > multiplier block approach realized with, say, bit-serial >> > > addition be more efficient than some other approach such >> > > as distributed arithmetic? >> > > >> > > Comments welcome. Thanks. >> > > >> > > -Michael >> > > ______________________ >> > > Michael E. Spencer, Ph.D. >> > > President >> > > Signal Processing Solutions, Inc. >> > > Web: http://www.spsolutions.com >> > >> > -- >> > --Ray Andraka, P.E. >> > President, the Andraka Consulting Group, Inc. >> > 401/884-7930 Fax 401/884-7950 >> > email ray@andraka.com >> > http://www.andraka.com >> > >> > "They that give up essential liberty to obtain a little >> > temporary safety deserve neither liberty nor safety." >> > -Benjamin >> > Franklin, 1759 >> > >> > > -- > --Ray Andraka, P.E. > President, the Andraka Consulting Group, Inc. > 401/884-7930 Fax 401/884-7950 > email ray@andraka.com > http://www.andraka.com > "They that give up essential liberty to obtain a little > temporary safety deserve neither liberty nor safety." > -Benjamin Franklin, 1759Article: 60217
"GB" <donotspam_grantbt@jps.net> writes: > "rickman" <spamgoeshere4@yahoo.com> wrote in message > news:3F5B4FAC.41D84F7B@yahoo.com... > > > I don't think the micro should be in the data path. A micro can be used > > for control and management, but the data path should be pure hardware > > for maximum throughput. If you look around, you will find that there > > are USB chips with integrated micros (many are 8051s). But the USB 2.0 > > chips typically have a DMA engine for the data path. > > From what I understand, the image size is 1-2 MB (only need 8-bit depth) > large and the USB packets are quite small in comparison. So there needs to > be some smarts for setting up what part of the data gets DMA'd to the > USB endpoint buffers for any given transfer? Or does the FPGA > implementation just point to the image data stored in RAM (assuming image > frame captured to some local RAM buffer) and never move the data from > image_buffer -> to_endpoint -> to_USB (essentially skipping the middle > man by just using a pointer of sorts)? > > It's just a still picture (not a movie). Doesn't this seem like a somewhat > common function -- meaning wouldn't there be standard chips or > implementations that do this? One suggestion is to use a fairly decent "microcontroller" such as Intel Xscale (low power per MIPS) device. USB means stack. An USB stack couldd be bought from SoftConnex, for instance. A fitting device might be found from Transdimension. Homann (Yes a relation exists) -- Magnus Homann, M.Sc. CS & E d0asta@dtek.chalmers.seArticle: 60218
I have spent the last 60 days trying to get an answer from Xilinx on their new S3 devices. During a review, it was stated that the new S3s were very sensitive to transients on the I/O pins. Because they made a point to mention this during the review, I posed the following question to Xilinx: "If we look at the incident versus reflected energy and tune the stub (trace) for a worst case match is it possible the driver could be damaged or the chip lock up due to the reflected energy?" "The circuit would be as follows: Spartan III Output ------------------------------ Tunable Stub" I wonder if anyone in this group has asked this question and what was the responce from Xilinx?Article: 60219
Daniel Köthe <d.koethe@colour-control.com> wrote in message news:<bjhlnr$k7j$1@news.eastlink.de>... > Hello, > i looking for a SJA1000 or compatible IP-Core for an Spartan-II. > There are other's Sources as Xilinx-Core program or Opencores? there are lots of sources, but ASFAIK the only free CAN-IP is at opencores, and unfortunatly current version makes Xilinx XST to fail with fatal error, both vhdl and verilog versions, see my email at fpga newsgroup about this. so if you want to use the free CAN get it from opencores and fix the problem anttiArticle: 60220
Sorry for the missing data. Probably a very important piece. The price of the board is $199US + shipping. thanks, hamilton <hamilton@deminsional.com> wrote in message news:<3f5b531d_2@omega.dimensional.com>... > Very nice, but the web site does not show a price. > > Please share. > > jjl wrote: > > Everybody, > > > > (Excuse my sales pitch at this forum.. > > but lots of folks are asking about where to > > start with FPGAs..) > > > > A new FPGA Development Board is out at: > > > > http://www.cmosexod.com/fnd.htm > > > > This board is ideal for: > > > > - Novice or everyone else just wanting to start out > > exploring FPGAs. > > > > - SW engineers wishing to get into HW > > ( no need to mess with solder and irons > > and plug-in boards - unless you > > want to ) > > > > - HW engineers wishing for a low-cost and yet > > capable and expandable development board > > which can be turned into a permanent board. > > ( no need to design another board > > after your FPGA design is completed. Use > > this board to permanently house your design. ) > > > > > > - The board is specially design to have the most > > needed features. You won't be buying an expensive > > "everything board" just to use 1 or 2 features > > of the board. Similarly, if you need features > > not present on the board, you can plug in your > > own board. > > > > This is a low-cost (relatively speaking), complete with > > most frequently used peripherals. Lots of expansion connectors > > allows cascading several boards or add your own "daughter" board. > > > > YOU GET A BOARD AND A COMPUTER: > > =============================== > > The Board comes with a complete Computer System core, so > > it works right out of the box. It shows the potentials > > of the board. Plug in a VGA monitor a keyboard and mouse > > and start writing your own application. > > The Computer core is yours to keep. The bitstream image of > > it is included in the CD, so you can always reload the > > board with it.Article: 60221
You may want to check out www.opencores.org for vga IP in verilog. Also, a very goodprimer of vga HS/VS at: http://www.xess.com/appnotes/vga.pdf Finally, a non-free (for cost) comple VGA core with DMA engine and SDRAM controller (32bit data path) in multi-clock domain at: http://www.cmosexod.com/fnd.htm hope this helps, "Abby" <abhigayl@hotmail.com> wrote in message news:<pqD6b.37758$R32.1195475@news2.tin.it>... > "cfk" <cfk_alter_ego@pacbell.net> ha scritto nel messaggio news:L8t6b.10410 > > > Thank you very much Charles!!! > I will try to search for some of titles you said to me. > I hope to solve my problem.Article: 60222
Hi just got XCF02S and XCF04S soldered in and it instantly worked, well I did choose erase first in iMpact and then it was frozen for 10 seconds during erase time (I was already afraid something is not OK) but after programming the FPGA board did come alive, first time without jtag cable attached, and said hello from MicroBlaze program. XCF0xS devices are really nice, the package is smaller then SO14, smaller than DIP8 and only slightly bigger than SO8, and they are very low priced (below 7EUR) so if somebody has to choose xilinx config memory then Platform Flash is defenetly there and available! antti http://www.graphord.com/forumArticle: 60223
Hi Fellow, I want to send data to FPGA and store in register in FPGA sequentially. In my design it is required to take 12 input from the data bus in 12 different clock pluse one by one then I have to start processing data in FPGA and then the result after performing calculations is to be taking out of FPGA. The problem which I am facing is syncronization of clock. B/C I am downloading data using C code. In FPGA I have defined 100 MHz clock frqeuency and my processor is working on 2 GHz. SO if I have to send 12 data signals to FPGA then it will be taking input much slowly as compared to PC speed. And in my design Clock cycle is important because I am using clock cycle count's to do different things. Could any body please tell me how to synchronize the PC and FPGA internal clock. Do I need to use SLEEP command in C program to do that . And one thing more that C instruction also uses more then one clock cycle to perform particular task. Any help in this regards would be appreciated. Regards IsaacArticle: 60224
> Is this a group for getting help for programming PIC's (16F84A) alt.microcontrollers.8bit "PIC's and others"
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