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Hi Martin, Thanks for the info. I'll keep the group apraised of what I do. Right now it looks like one of those SST parts with a uC helper. I really don't see why a config ROM should cost so much (more than an FPGA?) Still no word from Altera (via e-mail or NG) though. Thanks, Jay. In article <uekyrk9ji.fsf@trw.com>, martin.j.thompson@trw.com says... > Jay <se10110@yahoo.com> writes: > > > Hi Martin, > > > > Thanks for your response. > > > > In article <uy8x3ya5r.fsf@trw.com>, martin.j.thompson@trw says... > > > Jay <se10110@yahoo.com> writes: > > > > > > > I'm investigation configuration PROMs for a EPF6010A (FLEX 6K). It looks > > > > like the default choice is the EPC1441 which is not ISP or Flash. > > > > > > > > Altera makes the EPC2 which is Flash/ISP but for some reason it's not > > > > compatible with FLEX6K. Anyone know why? Any way to get it to work with > > > > the EPF6010A? > > > > > > > > > > I used one a long time ago with a 6016A, worked fine. What makes you > > > think they won't work? > > > > Are you sure it was an EPC2? > > > > Yep, I reprogrammed it and everything! > > > They make mention several times not to use it on the Flex 6K family: > > > > http://www.altera.com/literature/ds/dsconf.pdf , page 9, note 1: > > > > "Do not use EPC2 devices to configure FLEX 6000 devices." , and again on > > page 12, etc. > > > > So they do, I hadnot noticed that! I was going on the fact that they > "seemed" to be compatible with the older EPC1x series in terms of > pinout and timing. Indeed, table 5 is entitled "Table 4. APEX 20K, > FLEX 10K & FLEX 6000 Timing Parameters using EPC2 Devices at 3.3 V" > > > I'm wondering why the Altera guys haven't followed up in the NG, they > > seem to be pretty attentive as of late. > > > > Yeah, they would have the "right" answer, but I can certainly say it > worked for us. We made a few of these boxes, and some of them ended > up on the front of cars, and I never had any complaints. > > > > The Altera ones were about 20UKP last time I bought them. :-( > > > > That doesn't sound too promising. How much were you paying for the > > EPF6016As, if I might ask?Article: 60226
Martin Euredjian wrote: > When programming an XC18V04 I get a red "Programming Failed" indicator at > the end of the process. The device is connected to an XC2V1000 in SelectMAP > mode. I tried disabling "FPGA Load" but nothing changed. I should mention > that the boards come-up just fine, in other words, it seems that the > programming of the PROM is successful every single time, despite the > message. > > The log file doesn't have any useful information. Can anyone suggest where > I might look to figure this out? > > Thanks, > > Is your JTAG chain including both SPROM and FPGA, or just your SPROM? ------------ And now a word from our sponsor ------------------ Do your users want the best web-email gateway? Don't let your customers drift off to free webmail services install your own web gateway! -- See http://netwinsite.com/sponsor/sponsor_webmail.htm ----Article: 60227
Rick, I was counting what we count as "gates". And the number was for the largest part. Forget it. The price quote is where the rubber hits the road. Sorry I confused everyone. But plotting the price per gate is an interesting academic exercise that does show a huge price per gate reduction in the last 5 years. Austin rickman wrote: > Austin Lesea wrote: > > > > Jon, > > > > Still in production, still shipping to customers. > > > > Contact your local sales rep to talk about stocking and pricing. The > > fact that the newer parts cost a lot less is because they are smaller > > die for the same functionality. If you think about it, the $ per FPGA > > gate has been dropping pretty drastically now for many years. In > > Spartan 3, we are now down to ~100 uCents per gate range. The XCS30 can > > no hope to compete for this being in such an old technology. Seven > > years ago, ~$40 for 30K "gates" was a great price.... > > Austin, > > I'm not tryin to quibble, I just want to understand what your dollar (or > cents) figure means. At 0.0001 cents per gate, I get $0.40 for the > XC3S400. That is a lot less than the quote I got a few weeks ago. Were > you counting "real" gates instead of "user" gates? > > -- > > Rick "rickman" Collins > > rick.collins@XYarius.com > Ignore the reply address. To email me use the above address with the XY > removed. > > Arius - A Signal Processing Solutions Company > Specializing in DSP and FPGA design URL http://www.arius.com > 4 King Ave 301-682-7772 Voice > Frederick, MD 21701-3110 301-682-7666 FAXArticle: 60228
Both. "Amontec Team, Laurent Gauch" <laurent.gauch@amontecDELETEALLCAPS.com> wrote in message news:3f5cbfb7$1@news.vsnet.ch... > Martin Euredjian wrote: > > When programming an XC18V04 I get a red "Programming Failed" indicator at > > the end of the process. The device is connected to an XC2V1000 in SelectMAP > > mode. I tried disabling "FPGA Load" but nothing changed. I should mention > > that the boards come-up just fine, in other words, it seems that the > > programming of the PROM is successful every single time, despite the > > message. > > > > The log file doesn't have any useful information. Can anyone suggest where > > I might look to figure this out? > > > > Thanks, > > > > > Is your JTAG chain including both SPROM and FPGA, or just your SPROM? > > ------------ And now a word from our sponsor ------------------ > Do your users want the best web-email gateway? Don't let your > customers drift off to free webmail services install your own > web gateway! > -- See http://netwinsite.com/sponsor/sponsor_webmail.htm ----Article: 60229
When using Spartan-3 FPGAs in an 3.3V LVTTL or LVCMOS application, the output voltage, VCCO, must be within the "narrow" voltage range defined in the EIA/JEDEC JESD8-B specification, namely 3.15V to 3.45V, with a nominal 3.3V value. The primary consideration on Spartan-3 I/Os is to keep the voltage at the pin below the 3.75V absolute maximum specification. Going above 3.75V doesn't immediately destroy the device, but prolonged exposure degrades device lifetime. If the voltage remains below 3.75V, there is no degradation. So, if VCCO should be below 3.45V, how can the voltage at the pin possible reach 3.75V? Mismatched impedance can cause overshoot and undershoot, raising the voltage on the pin by hundreds of millivolts. Properly terminating a trace eliminates or reduces the over/undershoot to acceptable limits. Application note XAPP659 describes some of the techniques to guarantee that signals stay under 3.75V. Although written for the Virtex-II Pro family, these same techniques apply to Spartan-3 FPGAs. Using 3.3V I/O Guidelines in a Virtex-II Pro Design. http://www.xilinx.com/bvdocs/appnotes/xapp659.pdf I hadn't seen this question coming in from our FAE team, so my apologies on not receiving an answer before this time. Should you have any other questions, please feel free to contact me directly. Just be sure to remove the "NOSPAM" from my return E-mail address. --------------------------------- Steven K. Knapp Applications Manager, Xilinx Inc. Spartan-3/II/IIE FPGAs http://www.xilinx.com/spartan3 --------------------------------- Spartan-3: Make it Your ASIC "lecroy" <lecroy7200@chek.com> wrote in message news:9297c711.0309080520.260aa01b@posting.google.com... > I have spent the last 60 days trying to get an answer from Xilinx on > their new S3 devices. During a review, it was stated that the new S3s > were very sensitive to transients on the I/O pins. Because they made a > point to mention this during the review, I posed the following > question to Xilinx: > > "If we look at the incident versus reflected energy and tune the stub > (trace) > for a worst case match is it possible the driver could be damaged or > the > chip lock up due to the reflected energy?" > > "The circuit would be as follows: > Spartan III Output ------------------------------ Tunable Stub" > > I wonder if anyone in this group has asked this question and what was > the responce from Xilinx?Article: 60230
Here are my 2 cents worth, the way I explained it at FPL2003 in Europe last week: When I joined Xilinx in 1988, we charged about one dollar per flip-flop/LUT combination. Today that price in Virtex is about one cent, and in 2004 in Spartan3 in high volume it is heading towards 0.2 cents. Size, package, speed-grade and purchase volume do of course change these numbers considerably... Peter Alfke, just back from Lisbon. I gladly missed all the discussions on how to "eliminate" metastability. What a waste of engineering effort and internet bandwidth... =================== Austin Lesea wrote: > > Rick, > > I was counting what we count as "gates". And the number was for the largest > part. > > Forget it. The price quote is where the rubber hits the road. Sorry I > confused everyone. But plotting the price per gate is an interesting academic > exercise that does show a huge price per gate reduction in the last 5 years. > > Austin > > rickman wrote: > > > Austin Lesea wrote: > > > > > > Jon, > > > > > > Still in production, still shipping to customers. > > > > > > Contact your local sales rep to talk about stocking and pricing. The > > > fact that the newer parts cost a lot less is because they are smaller > > > die for the same functionality. If you think about it, the $ per FPGA > > > gate has been dropping pretty drastically now for many years. In > > > Spartan 3, we are now down to ~100 uCents per gate range. The XCS30 can > > > no hope to compete for this being in such an old technology. Seven > > > years ago, ~$40 for 30K "gates" was a great price.... > > > > Austin, > > > > I'm not tryin to quibble, I just want to understand what your dollar (or > > cents) figure means. At 0.0001 cents per gate, I get $0.40 for the > > XC3S400. That is a lot less than the quote I got a few weeks ago. Were > > you counting "real" gates instead of "user" gates? > > > > -- > > > > Rick "rickman" Collins > > > > rick.collins@XYarius.com > > Ignore the reply address. To email me use the above address with the XY > > removed. > > > > Arius - A Signal Processing Solutions Company > > Specializing in DSP and FPGA design URL http://www.arius.com > > 4 King Ave 301-682-7772 Voice > > Frederick, MD 21701-3110 301-682-7666 FAXArticle: 60231
> I managed to transmit and receive traffic on a 10BASE-T network using some > simple Verilog code and 4 pins of an FPGA connected almost directly to the > wires. > > Most microcontrollers require an external Ethernet MAC, but it seems that we > can do without if we limit ourselves to IP/UDP. > I think that there are potentially plenty of interesting applications. > > The project is working well already, so I documented a good chunk of it. > http://www.fpga4fun.com/10BASE-T.html > > Comments are welcome! > Jean > Cool project. Have you coded the ethernet stuff by yourself or used an ip block? You have one small misstake: The splitting in RX and TX lines on RJ45 does not prevent contention! It is still possible. Some time ago I was also thinking about an ethernet inteface in an FPGA. I thought, like you, now with RJ45 it's easier since contention detection is one of the hard parts. However, if you read carefully the doc's it's still there ;-( Martin -- ---------------------------------------------- JOP - a Java Processor core for FPGAs: http://www.jopdesign.com/Article: 60232
Peter Alfke wrote: > > Here are my 2 cents worth, the way I explained it at FPL2003 in Europe > last week: > > When I joined Xilinx in 1988, we charged about one dollar per > flip-flop/LUT combination. > Today that price in Virtex is about one cent, and in 2004 in Spartan3 in > high volume it is heading towards 0.2 cents. > Size, package, speed-grade and purchase volume do of course change these > numbers considerably... > > Peter Alfke, just back from Lisbon. > I gladly missed all the discussions on how to "eliminate" metastability. > What a waste of engineering effort and internet bandwidth... Peter, I would like to know how you came to this number for the Spartan3 parts. If I use this number for the XC3S400, I get 7168 x $0.002 = $14.336. For the XC3S5000 I get 66,560 x $.002 = $133.12. Are these realistic prices at all? What assumptions did you use? I understand that your .2 cents figure is only a rough rule of thumb, but to be at all useful an understanding of the basis is needed. BTW, the discussion on metastability may appear to be a waste of "bandwidth", but it is an important discussion since most people seem to learn about it here rather than in school or elsewhere. I know there were a great many things that were never even mentioned in school that turned out to be essential to designing good circuits in the "real world". -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAXArticle: 60233
"Martin Euredjian" <0_0_0_0_@pacbell.net> writes: > When programming an XC18V04 I get a red "Programming Failed" indicator at > the end of the process. The device is connected to an XC2V1000 in SelectMAP > mode. I tried disabling "FPGA Load" but nothing changed. I should mention > that the boards come-up just fine, in other words, it seems that the > programming of the PROM is successful every single time, despite the > message. > > The log file doesn't have any useful information. Can anyone suggest where > I might look to figure this out? You might have a problem in your jtag chain. If your tdo does not propagate through the XC2V1000 or to the final tdo pin (connected to your programmer), your sprom could be programmed but the output check fails. Petter -- A: Because it messes up the order in which people normally read text. Q: Why is top-posting such a bad thing? A: Top-posting. Q: What is the most annoying thing on usenet and in e-mail?Article: 60234
Hi Brian, Taking a step back from FPGAs, I would investigate specific programmable cross-point switches that Lattice offers for this kind of funtionality. Check out the ispGDX family from Lattice - you might be surprised! http://www.latticesemi.com/products/digin/ispGDX/index.cfm Anil "Brian Fairchild" <spam.spam@spam.com> wrote in message news:jhcclv0p5n1628t9s1cdfpthac60ltjub4@4ax.com... > Hi > > I'm an embedded systems designer who feels that it's about time he > started to learn about using FPGAs. I'm happy using PLDs, designed in > something like CUPL but don't know where to start on bigger devices. > > I only have a small budget for development tools and I'm in the UK. > > From what I can see my best choice of manufacturer is probably down to > Xilinx or Altera. > > Can anyone suggest an evaluation board that would get me started? > > I see that devices are sold in terms of their gate count. How > efficient is a typical design? For instance, if I want to make a 16 by > 16 CPU controlled crosspoint how many FPGA gates will I need? I can > see that I need 16 OR gates each with 16 AND array inputs for the > output terms, 64 latches to store the selection and some more gates to > do the latch address decoding. Is there any easy way to choose the > right part? > > Thanks > > Brian > -- > Brian Fairchild > B dot Fairchild at Dial dot Pipex dot Com > > "But apart from that Mrs Lincoln, how did you enjoy the play?"Article: 60235
I created an compiled a project to create bit file using the microblaze EDK 3.2. I can successfully create the bit file combining both the HW/SW streams and download it onto my XSV-800 board. I have a couple of questions: * However after I download the design onto the board, all output pins continuously go high. Specifically I redirected the output on one of one of the pushbuttons and even this pin is perpetually high. Does anybody seen anything like this before. * When I look up the ncd file generated on an fpga-editor, I notice that the clock distribution does not take place over the clock-distribution network on the fpga, but instead on the long and short signal nets. Why is this the case? Any help is greatly appreciated. Thanks, -BhanuArticle: 60236
You may want to consider askign your question to the Xilinx University Newsgroup: http://www.xilinx.com/univ/xup/course.htm#ug Student/University questions are probably best handled by this forum (thanks to MIT). Austin "Bhanu Nagendra P." wrote: > I created an compiled a project to create bit file using the microblaze > EDK 3.2. I can successfully create the bit file combining both the HW/SW > streams and download it onto my XSV-800 board. > I have a couple of questions: > > * However after I download the design onto the board, all output pins > continuously go high. Specifically I redirected the output on one of > one of the pushbuttons and even this pin is perpetually high. Does anybody seen > anything like this before. > > * When I look up the ncd file generated on an fpga-editor, I notice that > the clock > distribution does not take place over the clock-distribution network on > the fpga, but instead on the long and short signal nets. Why is this the > case? > > Any help is greatly appreciated. > Thanks, > -BhanuArticle: 60237
Followup to: <bjhgdo$1li7$1@justice.itsc.cuhk.edu.hk> By author: "clsan" <clsan@cuhk.edu.hkk> In newsgroup: comp.arch.fpga > > Hi all, > > I am doing a project and using Altera Nios Development kit with Stratix > Edition. I need to connect a serial/PS/2 mouse to that board . But the board > can't get any signal from the mouse, anyone has this experience can share > with me?I have already set the UART 2 to 1200 baud rate. > Thank you very much. > Most mice need a particular combination of the control signals in order to enter serial mode (as opposed to PS/2 mode.) This probably means you need to use the CONSOLE port as opposed to the DEBUG port, and drive the proper signals. You'd also need a null modem cable in between, since the NDK board is wired as a DCE instead of a DTE (a mistake in my opinion.) -hpa -- <hpa@transmeta.com> at work, <hpa@zytor.com> in private! If you send me mail in HTML format I will assume it's spam. "Unix gives you enough rope to shoot yourself in the foot." Architectures needed: ia64 m68k mips64 ppc ppc64 s390 s390x sh v850 x86-64Article: 60238
Hi, I am running a study of configuration bitstreams targetted at Celoxica's RC1000. Mediabench has an implementation of JPEG image compression and decompression written in C. I wish to target this implementation namely, the two demo programs, cjpeg and djpeg, on the RC1000. To do this I probably need to implement or port the C code over to HandelC or some other suitable language to eventually generate a bitstream from. Would anyone know of where I can obtain such code from? Thanks for any help offered. :)Article: 60239
Martin, about the contention, in the current IEEE spec (IEEE 802.3-2002), section "4.2.3.2.6 Full duplex transmission" states: "In full duplex mode, there is never contention for a shared physical medium." That's the beauty of it. Twice the bandwidth, and much easier to implement. So my code is only intended to be connected to a full-duplex capable device only (i.e. a switch or directly to another computer). Your remark is true for half-duplex (which is much harder to implement!). Hope that convinces you. Jean "Martin Schoeberl" <martin.schoeberl@chello.at> wrote in message news:AJ47b.216558$2k4.2477739@news.chello.at... > > I managed to transmit and receive traffic on a 10BASE-T network using some > > simple Verilog code and 4 pins of an FPGA connected almost directly to the > > wires. > > > > Most microcontrollers require an external Ethernet MAC, but it seems that > we > > can do without if we limit ourselves to IP/UDP. > > I think that there are potentially plenty of interesting applications. > > > > The project is working well already, so I documented a good chunk of it. > > http://www.fpga4fun.com/10BASE-T.html > > > > Comments are welcome! > > Jean > > > > Cool project. Have you coded the ethernet stuff by yourself or used an ip > block? You have one small misstake: The splitting in RX and TX lines on RJ45 > does not prevent contention! It is still possible. Some time ago I was also > thinking about an ethernet inteface in an FPGA. I thought, like you, now > with RJ45 it's easier since contention detection is one of the hard parts. > However, if you read carefully the doc's it's still there ;-( > > Martin > -- > ---------------------------------------------- > JOP - a Java Processor core for FPGAs: > http://www.jopdesign.com/ > > > >Article: 60240
john jakson <johnjakson@yahoo.com> wrote: > "GB" <donotspam_grantbt@jps.net> wrote in message news:<GFJ6b.2610$PE6.1782@newsread3.news.pas.earthlink.net>... >> "hamilton" <hamilton@deminsional.com> wrote in message >> news:3f5b561c_3@omega.dimensional.com... >> >> > What image sensor chip are you looking at ??? >> > >> >> That's another undecided at this time, but CMOS most likely. >> >> GB > > Until recently I was under the impression that CMOS sensors were junk > and were of low resolution & quality typically 320.240 used in $0-50 > cameras. I have an old Connectix webcam device thats is all green that > demonstrates that. I believe all present digtal cameras use CMOS. That includes monsters in the 16Mpixel range. -- Sander +++ Out of cheese error +++Article: 60241
Hi all, I have managed to get the Xilinx command line tools running on linux under wine, however last night while trying to program my device I hit a bit of a wall. After reading the archives of this group, I see that that the iMPACT tool won't run under linux. I have a home made parallel III cable and am trying to program an XC9536 CPLD. How are other people doing this? Thanks so much for any help/advice you can provide, regards, James FitzsimonsArticle: 60242
There are very few applications where any FPGA brand is "the only" solution to the problem. Most designs are gates and flops, and they all do that pretty well. Most engineers, myself included, end up using what they know and trust and feel they have the best chance of success with -- whether it is parts or design methodology etc. Perhaps the simplest way to compare X's to A's is to look at the "logic cell" count. This would be the number of 4-input lookup-tables that feed flops. The X datasheets are a bit obtuse in this area, and you have to be careful when you go from family to family. For example, the Virtex2 parts describe one CLB as containing 4 "slices", and each "slice" has 2 LUT + FF. So, one CLB has 8 LUT + FF. But, they don't list how many CLBs are in the parts -- they show "slices". An XC2V250 has 250K "gates", comprising 1536 "slices", or a tad over 3000 flops. This is about the same size as a Cylcone 1C3, which is advertised as having 2910 flops. As for Spartan 2E, the 2S300E has 6912 "logic cells" and 1536 CLBs. Here's where you have to pay attention to their inconsistent language. In S2E's, one CLB = 4 "logic cells" and each LC = LUT + FF. So, you have 4 FF per CLB, not 8 like in V2/2Pro. What's more strange is that 1536 x 4 = 6144, not the 6912 they advertise. They are counting other elements in the design as "logic cells" beyond the 6144 that are in each CLB. Not sure what that's all about. You certainly should have at least 6144 flops in the 2S300. This is about equal to a 1C6 Cyclone part, which has 5980 flops. I don't have any pricing numbers on the X parts, but a 1C3 can be had for about $17 in quantity 1 pricing, and the 1C6 starts at about $27. X and A differ on the types of I/O each family of devices will support, so you have to pay close attention to that too. If you have large internal memory requirements, you need to move to the more costly Stratix parts from Altera, or the Virtex2/2PRO parts from Xilinx. X and A have differing memory architectures too, and both companies' high-end parts have dedicated hardware for implementing DSP functions. Once Spartan 3 comes into full, qualfied production, those parts have the promise of low cost and DSP stuff -- Cyclone parts don't include DSP hardware, so you'd have to roll your own. Different vendors also have different power consumption, which may or may not be a factor. Both companies' newer parts can run amazingly fast. The cheapest, smallest, slowest Cyclone parts can handle OC-48 SONET rates without breathing hard, and I expect Spartan 3 can do the same. Pushing into the fastest speed grade parts can accomodate in excess of 35 Gbps pipelined processing on 128-bit wide buses. You can "get serious" with parts from either vendor, even in the low-cost families. I have never had difficulties migrating old designs into newer part families, so portability works out well too. Hope this helps. "John K." <INVALIDANTISPAM@aol.com> wrote in message news:bjg5tb$iffkb$1@ID-50260.news.uni-berlin.de... > Hi Alex Gibson (alxx@ihug.com.au), you wrote: > > > in project navigator > > ->new source ->schematic type in the name of the file for it to create > > click okay > > ecs (xilinx schematic editor) will start up and you > > can start drawing up your schematic. > > Maybe it's because I'm using the v5.2.03i of the free WebPack, but > I can't find any schematic option in the New Source window. :( > > I can see only: > > User Document > BMM File > MEM File > Implementation Constraints File > > > > with webpack the major hassle is simulating a schematic design. > > You have to convert your design to vhdl or verilog so > > modelsim can load your design. > > > > Altera's software is much better for simulating schematics than > > xilinx's. > > Yup, I'm thinking to dump Xilinx and go with Altera instead. But > it's very confusing for me to find the right target device. What > would be a rough equivalent of the Spartan 2E 300? Altera has so > many families that it's very confusing (at least for me). > > Moreover, what about programmers and development boards? My former > choice for Xilinx was motivated by the large (till 10 millions of > equivalent (fake, I know) gates!) rich choice of sizes, the low > cost development boards (like the ones from Digilent and Burched) > with integrated programmer. I need cheap, for the moment. > > One thing, though, that puzzled me is why similar designs to the > one I have in mind, i.e. the C-One and XGameStation, both use > Altera devices. No, I won't ask if they're superior than Xilinx > (or inferior, for the matter :) ) to avoid to cause a possible > very boring flamewar here. ;) > What I really ask is instead if Altera devices are suitable for > low budget development (just to get confident with the FPGA world) > using schematic entry and simulation, and if then they will offer > the power to do serious stuff, without having to dump it all and > change brand/family of chips. Moreover, why not Actel or Lattice/ > Vantis, or why not Lucent or QuickLogic (just to name those that > I heard the existance of and visited thousands times the website > of, without much results anyway)? > Moreover, if I go with Altera, which are the families roughly > equivalent in specs to the Spartan 2E and Virtex of Xilinx? > > Thanks a lot for all your big patience and help! > > Greets, > John >Article: 60243
xilinx has released the native linux version. "James" <jamesf@intergen.co.nz> wrote in message news:842dc172.0309081906.10d2085b@posting.google.com... > Hi all, > I have managed to get the Xilinx command line tools running on linux > under wine, however last night while trying to program my device I hit > a bit of a wall. After reading the archives of this group, I see that > that the iMPACT tool won't run under linux. > > I have a home made parallel III cable and am trying to program an > XC9536 CPLD. > > How are other people doing this? > > Thanks so much for any help/advice you can provide, > regards, > James FitzsimonsArticle: 60244
> xilinx has released the native linux version. Could you give me a link? > "James" <jamesf@intergen.co.nz> wrote in message > news:842dc172.0309081906.10d2085b@posting.google.com... >> Hi all, >> I have managed to get the Xilinx command line tools running on linux >> under wine, however last night while trying to program my device I >> hit a bit of a wall. After reading the archives of this group, I see >> that that the iMPACT tool won't run under linux. >> >> I have a home made parallel III cable and am trying to program an >> XC9536 CPLD. >> >> How are other people doing this? >> >> Thanks so much for any help/advice you can provide, >> regards, >> James Fitzsimons > > >Article: 60245
Jean, there is still a problem. If you use a point to point connection (with a cross over cabel) it can be possible that both stations transmit without a contention. However, Ethernet is still a bus. Imagine following situation: Three stations (A,B,C) connected via a hub. Station A and B are sending at the same time. Which message will arrive at C? This IS a contention. On A and B perhaps you will not see a contention on the TX lines, however you have to listen to the RX line while sending and abort your transmit, enter the random timeout and retransmit. And I'm not shure if a simple hub will support full duplex mode. Sorry, I'm not convinced Martin > Martin, > > about the contention, in the current IEEE spec (IEEE 802.3-2002), section > "4.2.3.2.6 Full duplex transmission" states: > "In full duplex mode, there is never contention for a shared physical > medium." > > That's the beauty of it. Twice the bandwidth, and much easier to implement. > So my code is only intended to be connected to a full-duplex capable device > only (i.e. a switch or directly to another computer). > > Your remark is true for half-duplex (which is much harder to implement!). > Hope that convinces you. > Jean > > "Martin Schoeberl" <martin.schoeberl@chello.at> wrote in message > news:AJ47b.216558$2k4.2477739@news.chello.at... > > > I managed to transmit and receive traffic on a 10BASE-T network using > some > > > simple Verilog code and 4 pins of an FPGA connected almost directly to > the > > > wires. > > > > > > Most microcontrollers require an external Ethernet MAC, but it seems > that > > we > > > can do without if we limit ourselves to IP/UDP. > > > I think that there are potentially plenty of interesting applications. > > > > > > The project is working well already, so I documented a good chunk of it. > > > http://www.fpga4fun.com/10BASE-T.html > > > > > > Comments are welcome! > > > Jean > > > > > > > Cool project. Have you coded the ethernet stuff by yourself or used an ip > > block? You have one small misstake: The splitting in RX and TX lines on > RJ45 > > does not prevent contention! It is still possible. Some time ago I was > also > > thinking about an ethernet inteface in an FPGA. I thought, like you, now > > with RJ45 it's easier since contention detection is one of the hard parts. > > However, if you read carefully the doc's it's still there ;-( > > > > Martin > > -- > > ---------------------------------------------- > > JOP - a Java Processor core for FPGAs: > > http://www.jopdesign.com/ > > > > > > > > > >Article: 60246
"Petter Gustad" <newsmailcomp5@gustad.com> wrote in message news:87smn79gch.fsf@zener.home.gustad.com... > "Martin Euredjian" <0_0_0_0_@pacbell.net> writes: > > > When programming an XC18V04 I get a red "Programming Failed" indicator at > > the end of the process. The device is connected to an XC2V1000 in SelectMAP > > mode. I tried disabling "FPGA Load" but nothing changed. I should mention > > that the boards come-up just fine, in other words, it seems that the > > programming of the PROM is successful every single time, despite the > > message. > > > > The log file doesn't have any useful information. Can anyone suggest where > > I might look to figure this out? > > You might have a problem in your jtag chain. If your tdo does not > propagate through the XC2V1000 or to the final tdo pin (connected to > your programmer), your sprom could be programmed but the output check > fails. > I can program the FPGA (in the same chain) without any problems whatsoever. -- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ Martin Euredjian To send private email: 0_0_0_0_@pacbell.net where "0_0_0_0_" = "martineu"Article: 60247
Hi. I have a xc2v8000 design (70% utilization). With the same EDIF netlist the Xilinx routability changes dramatically with frequency: Clock constraint: 25 MHz -> routed design Clock constraint: 50 MHz -> 1200 un-routed wires Clock constraint: 100 MHz -> 60000 un-routed wires Unfortunately 100 MHz is my target frequency... Is there a flag that tells the Xilinx P&R to prefer routing over timing at the first phase, and do speed optimization only afterwards? ThankX, JohnArticle: 60248
On Tue, 09 Sep 2003 06:39:16 GMT, "Martin Schoeberl" <martin.schoeberl@chello.at> wrote: >Jean, > >there is still a problem. If you use a point to point connection (with a >cross over cabel) it can be possible that both stations transmit without a >contention. However, Ethernet is still a bus. Imagine following situation: >Three stations (A,B,C) connected via a hub. Jean is only supporting full duplex mode on point to point links, which disallows the use of a hub. Regards, Allan.Article: 60249
http://www.xilinx.com/ise/marketing/new.htm "James Fitzsimons" <jamesfit@nospam.paradise.net.nz> wrote in message news:20030909182654617+1200@news.paradise.net.nz... > > > xilinx has released the native linux version. > > Could you give me a link? > > > "James" <jamesf@intergen.co.nz> wrote in message > > news:842dc172.0309081906.10d2085b@posting.google.com... > >> Hi all, > >> I have managed to get the Xilinx command line tools running on linux > >> under wine, however last night while trying to program my device I > >> hit a bit of a wall. After reading the archives of this group, I see > >> that that the iMPACT tool won't run under linux. > >> > >> I have a home made parallel III cable and am trying to program an > >> XC9536 CPLD. > >> > >> How are other people doing this? > >> > >> Thanks so much for any help/advice you can provide, > >> regards, > >> James Fitzsimons > > > > > >
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