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On 24 Sep 2003 18:14:12 -0700, Eric Smith <eric-no-spam-for-me@brouhaha.com> wrote: >Allan Herriman <allan.herriman.hates.spam@ctam.com.au.invalid> writes: >> 1. Allow multiple installations of (different versions of) Xilinx >> software on the same machine. Drop the use of the XILINX environment >> variable - it's a PITA. > >Conflicting requirements. The XILINX environment variable is what >ALLOWS multiple installations. That's how the pieces of an installation >find the other related pieces, rather than some other version. (Say) the value of XILINX is c:\xilinx42, which points to the ISE 4.2 installation. Now run the 5.2 FPGA Editor Start|Programs|Xilinx ISE 5|Accessories|FPGA Editor It bombs 'cause it tries to use the wrong version of a library. It doesn't have to bomb (since it can know where it is installed, and doesn't need to look at an environment variable to find out), but that's the way Xilinx wrote it. > The XILINX environment variable is what ALLOWS multiple installations. Could you explain that (using my example) more fully please? (BTW, I have used the XILINX variable in the past to select different versions within scripts, so I know what you mean, but I still think it needs to be improved.) Regards, AllanArticle: 60926
Jon Elson <jmelson@artsci.wustl.edu> wrote in message news:<3F7208C4.3050506@artsci.wustl.edu>... > James Williams wrote: > > >Is there one with the IEEE 1284 Core VHDL that is in english? > > > > > I poked around a while and found the VHD file, which seems readable. > I haven't tried to UNDERSTAND it yet, however - that is different. > > http://www.nahitech.com/nahitafu/fpgavhdl/ieee1284_2/ieee1284main-ver01.vhd good, come alone and you all will learn japanese as god as I ;) I dont understand nothing in japanese. And this is how I read japanese HDL/FPGA pages: 1 check pictures 2 check all hyperlinks, even if page is japanese the línks may have english page names :) 3 download all HDL files and all archive files, check whats inside the link what you found seems to be full IEEE1284 peripheral core with plug and play support (there is screenshot of the plug and play enumeration so I assume it is working and verified on FPGA) the design does synthesise out of box for Xilinx XST 256 Slices or 60% of XC95 144 for Actel APA075 its 25% the design is larger than commercial IEEE1284 cores, but it has plug and play enumaration built in (what you can easily comment out if needed) anttiArticle: 60927
Isaac wrote: Hi Isaac, > I am trying to read 36 signal one by one from FPGA using different > addresses and these signal are of 3 bits length. My address bus is > bidirectional (32 bit length)and it's on tristate while not performing > read operations. > I am using PCI API fucntion to perform open , read and write > operations as it is PCI FPGA reconfigurable board having XCV600 > device. The values are being read by using SRAM in the board and I am > using addresses which are properly mapped to PCI bus and Onboard > Memory. Now the problem is that I delebrately make a loop to read the > sequence of signal again and again in order to make sure I am reading > the correct output every time. But the thing is that in different > iteration the values of different signal are not the same. it means > that the signal which is being read is changing all the time. But > according to simulated desing this is not the case , I must have been > reading the correct output everytime . > Is there is any design constraint ? My desing has internal clock as > well is this is affecting the signal. But in simulation this is not > the case . Your problem is almost impossible to be solved from remote. You say that it is working well in simulation. Do you mean functional simulation (i.e. pure VHDL code) or back-annotated simulation (i.e. simulation of the synthesized design including estimated delays etc.)? Are you also sure that you meet all timing parameters when accessing the RAM? > Also one thing more does the VHDL coding style effect the read from > FPGA or not. Because in my other desing I have state machine and > number of different states in the Process (desing is synchronous) and > I am using CASE statement to move from one state to another. When I > download this into the chip and when I perform read operation after > writing data into the chip I am getting nothing from FPG. > If any one can tell me how to stabilize particular signal so that it > could to read oout from FPGA. Absolutely! VHDL coding style might have heavy impact on the result. To give an example effect I once encountered with Synopsys: When you have a clocked process with asynchronous reset and a couple of registers inside, and you forget to include one signal in the reset clause, then Synopsys created a register where the output is feed back and is ORed at the input. As a result, once the register turns to '1', it can never turn to '0' again. But in functional simulation you do not see that effect (exept from the fact that the register is not initialized during reset). That's another reason why it is important to simulate the synthesized design. Regards, MarioArticle: 60928
Allan, thank you for your explanation ; now i will have no more regret to use all those registers ! Julien .Article: 60929
Hi Javi, The memory RAM and RAM managment will be more important feature for your next portable computer. Make sure your DDRAM is not shared with Video Card !!! Make sure to have a minimum 512MB DDRAM. FOR synth and Place and Route the RAM is very important. Regards, Laurent Gauch _________________________ www.amontec.com Provides new low cost JTAG Solution (for Xilinx, Altera, All ARM processors, PPC, coldfire, ...) javid wrote: > Hello, > > I would like to know if someone have evaluated the performance with > FPGA software tools of the new Intel Centrino Processors compared with > the Intel Mobile Pentium 4. I would like to buy a portable and I don't > know which processor is better (more performance for EDA Tools). I > would appreciate any recommendation on Processors and Portable > Manufacturers. > > Thanks a lot and best regards, > > JaviArticle: 60930
On Thu, 25 Sep 2003 15:55:52 +1000, Allan Herriman <allan.herriman.hates.spam@ctam.com.au.invalid> wrote: >On 24 Sep 2003 18:14:12 -0700, Eric Smith ><eric-no-spam-for-me@brouhaha.com> wrote: > >>Allan Herriman <allan.herriman.hates.spam@ctam.com.au.invalid> writes: >>> 1. Allow multiple installations of (different versions of) Xilinx >>> software on the same machine. Drop the use of the XILINX environment >>> variable - it's a PITA. >> >>Conflicting requirements. The XILINX environment variable is what >>ALLOWS multiple installations. That's how the pieces of an installation >>find the other related pieces, rather than some other version. > >(Say) the value of XILINX is c:\xilinx42, which points to the ISE 4.2 >installation. > >Now run the 5.2 FPGA Editor >Start|Programs|Xilinx ISE 5|Accessories|FPGA Editor > >It bombs 'cause it tries to use the wrong version of a library. It >doesn't have to bomb (since it can know where it is installed, and >doesn't need to look at an environment variable to find out), but >that's the way Xilinx wrote it. > >> The XILINX environment variable is what ALLOWS multiple installations. > >Could you explain that (using my example) more fully please? To make it more interesting, try to run both 4.2 and 5.2 fpga editors at the same time (yes, I have wanted to do this), both run from the start menu, without using Start|Programs|Control Panel|System|Advanced|Environment Variables to change the value of XILINX. Well written software would do this without a hitch. The only reason Xilinx software doesn't do it is because customers don't complain enough. Well, I'm complaining. Allan.Article: 60931
javid wrote: > Hello, > > I would like to know if someone have evaluated the performance with > FPGA software tools of the new Intel Centrino Processors compared with > the Intel Mobile Pentium 4. I would like to buy a portable and I don't > know which processor is better (more performance for EDA Tools). I > would appreciate any recommendation on Processors and Portable > Manufacturers. > > Thanks a lot and best regards, > > Javi > Hello Javid, I recently bought a new laptop, centrino 1.5GHz, 512MB DDR and it works great with the Xilinx Webpack 5.2. I notice some performance difference with my desktop pc (P4 2.8GHz, 768MB DDR) but nothing to worry about, for me at least, since I only do designs for the Spartan IIe 200k on it ;-) As synthesis and route and place algorithms coonsume a lot of memory, I think that would be your major concern, depending on the designs you do, you may be better of with a centrino and 1024MB RAM than with a P4 3.06GHz with only 512MB... Kind regards, YvesArticle: 60932
fpga_uk@yahoo.co.uk (Isaac) wrote in message news:<889eb3fb.0309240705.2bb5e86c@posting.google.com>... > Hi Guys > > I am trying to read 36 signal one by one from FPGA using different > addresses and these signal are of 3 bits length. My address bus is > bidirectional (32 bit length)and it's on tristate while not performing > read operations. > I am using PCI API fucntion to perform open , read and write > operations as it is PCI FPGA reconfigurable board having XCV600 > device. The values are being read by using SRAM in the board and I am > using addresses which are properly mapped to PCI bus and Onboard > Memory. Now the problem is that I delebrately make a loop to read the > sequence of signal again and again in order to make sure I am reading > the correct output every time. But the thing is that in different > iteration the values of different signal are not the same. it means > that the signal which is being read is changing all the time. But > according to simulated desing this is not the case , I must have been > reading the correct output everytime . > Is there is any design constraint ? My desing has internal clock as > well is this is affecting the signal. But in simulation this is not > the case . > > > Also one thing more does the VHDL coding style effect the read from > FPGA or not. Because in my other desing I have state machine and > number of different states in the Process (desing is synchronous) and > I am using CASE statement to move from one state to another. When I > download this into the chip and when I perform read operation after > writing data into the chip I am getting nothing from FPG. > If any one can tell me how to stabilize particular signal so that it > could to read oout from FPGA. > > Cheers > Help would be appreciated. > > Rgds > > Isaac Without seeing your code it is not possible to make an exact diagnosis (maybe I couldn't even if I did see it), but I do have suggestions. Any signal that is an input to the FPGA synchronous logic should be internally synchronized with the logic's clock using 2 d flip-flops. The bus data need not be synchronized in this manner if the transfer logic (handshake) is synchronized. The read operation should have some sort of handshake to ensure that the output data is stable before it is read and that the FPGA logic "knows" when new data is requested. Does PCI protocol involve a handshake? If so, have you implemented it on the FPGA side? A typical handshake would be: The reader asserts data_request; the FPGA logic puts the data on the bus and asserts data_ready. The reader sees data_ready, reads the data, and unasserts data_request (this lets the FPGA logic know that the data has been read and it unasserts data_ready and). There are a number of variations on this, but without some sort of handshake it is quite likely that there will be missed data, multiple reads of the same data, etc. CharlesArticle: 60933
afocacci@yahoo.com (Virtex_User) wrote in message news:<ce6ef594.0309230942.6c8a22df@posting.google.com>... > I'm using a Xilinx 18V04 prom and find that it occasionaly loses it's > program. I can program the prom without a problem. I use it for > months, and then one dy when I turn on the board, some of the bits on > the prom are incorrect. See also Xilinx Answer Record 14444 "XC18V00/XC1700 - PROM frozen after the power cycling test, configuration fails after power-on reset/initial power up" BrianArticle: 60934
Hello All
OK Im a bit confused.
the verilog code
always @(posedge CLK or posedge CLR)
begin
if (CLR)
Q <= 20'b0;
else
if (CE) // Is counter Enabled.
begin
Q<=Q+1;
end
end
produces a ripple counter? Yes, No?
When I look at my simulation results I see glitches in the count output
leading me to assume that I have implemented a ripple counter.
IS it possible to remove the glitches with a synchronous Binary counter?
If yes what is the verilog code?
Ive read about Gray counters but as Im using the counter to step through
SRAM addresses I dont want to loose storage locations in my SRAM just because
my counter doesnt count through all possible binary counts.
Thanks in advance for all suggestions.
Denis
Article: 60935Steven K. Knapp wrote: > Just FYI, the free WebPack 6.1i is now available and supports the Spartan-3 > XC3S50, XC3S200, and the XC3S400. Also, the XC3S50 supported in WebPack > 6.1i has four 18K block RAMs, four 18x18=36 hardware multipliers, and two > Digital Clock Managers (DCMs) > > Xilinx WebPack 6.1i > http://www.xilinx.com/xlnx/xil_prodcat_landingpage.jsp?title=ISE+WebPack > > Devices Supported in WebPack 6.1i > http://www.xilinx.com/ise/products/webpack_config.htm > > --------------------------------- > Steven K. Knapp > Applications Manager, Xilinx Inc. > General Products Division > Spartan-3/II/IIE FPGAs > http://www.xilinx.com/spartan3 > --------------------------------- > Spartan-3: Make it Your ASIC > > > Hi Steven, I've noticed that the WebPack software only runs on a Windows system. Is there any chance that it will be released for Linux some day? I usually don't work on de Windows platform, so it is annoying me like hell, being forced to use it... Thanks. Kind regards, YvesArticle: 60937
Hi , my question is about using/modifiying ChipScope Pro: I have a direct access to the jtag pins through my own device driver. Now I wanna use this pins with the chipscope pro software. I thought about adding a filter driver ontop of the xilinx driver and redirect all access to my pci card. But before I try this workaround, I wanna ask some guys who might have been done such crazy things. thanks in advance, thomasArticle: 60938
I know about the various algorithms to draw lines, circles, etc. All of these pretty much rely on painting onto a frame buffer that is later used to scan out to a CRT. Does anyone know of any algorithms to draw primitives that work without the intermediate frame buffer step. In other words, the algorithm's input would be the current x,y pixel being painted on the screen and the desired shape's parameters. Horizontal and vertical lines (and rectangles), of course, are easy. But, how do you do curves or diagonal lines? It seems to me that you'd take y and solve for x, which could produce multiple results (say, a line near 0 degrees). You'd have to save the results for that y coordinate in a temporary buffer that would then be used to compare to x. That's as simple as I can come up with. -- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ Martin Euredjian To send private email: 0_0_0_0_@pacbell.net where "0_0_0_0_" = "martineu"Article: 60939
Eric Smith wrote: > > Allan Herriman <allan.herriman.hates.spam@ctam.com.au.invalid> writes: > > 1. Allow multiple installations of (different versions of) Xilinx > > software on the same machine. Drop the use of the XILINX environment > > variable - it's a PITA. > > Conflicting requirements. The XILINX environment variable is what > ALLOWS multiple installations. That's how the pieces of an installation > find the other related pieces, rather than some other version. That may be the way it is implemented, but I believe Allan is asking that they change the implementation. I know that I can have separate versions of Netscape, Visio, MS Office and many other packages running on the same machine. All I have to do is double click on the icon to run them. No changes to environment variables or other system wide changes. Surely this could be done with CAD tools if the vendor really wanted to make the change. -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAXArticle: 60940
Quartus II 4.0 contains several improvements to make it easier to use, for Max+Plus II users. We are interested in testing these usability changes on existing Max+Plus II users, who have had limited exposure to Quartus II. The only requirement is that the respondents be in the Bay area and be willing to visit the Altera Office in San Jose (near Montague and First Street). It should take no more than one hour and the participants will be suitably compensated. If you are interested, please reply to this email, along with times that will work for you. Thanks - Subroto Datta Altera Corp.Article: 60941
Trenz Electronic GmbH has extended its series of Spartan-IIE FPGA prototyping boards, providing an ideal platform for FPGA developers to evaluate, implement, test, and extend custom designs using high-density Xilinx Spartan-IIE FPGAs. The TE-XC2SE development board is equipped with a XC2S400E 400k gates Spartan-IIE FPGA in FT256 package. Especially tailored to system implementation as (SoC projects using processor IP cores, such as MicroBlaze), the board features 16Mbit Flash and 4 Mbit SRAM. Rich communication interfaces include RS-232, VGA output, USB. LEDs, switches and a liquid crystal display are integrated for easy user diagnostics. Up to 100 of the Spartan's most comprehensive programmable I/O's are available on a robust VG96 connector to the user. The TE-XC2SE development boards are available now. For more Information visit http://www.trenz-electronic.de or go directly to the shop at http://www.te-shop.deArticle: 60942
Rick, Get off that horse: 'typical' ringing is not the issue here. Have said it a number of times: overshoot and undershoot is bad (period), and is a sign of a bad board design. The fact that if you have 1) 85C Tj AND 2) you have a power supply at 3.6 volts AND 3) you have crappy SI over long t-lines (which store more energy -- like 12 - 24") MAY lead to exceeding the Abs Max spec. The point is that you have to simulate to get good SI, so do so. While you are at it, if the SI is terrible, fix it. If you can't fix it, then make sure you are within the Abs Max specs. Austin rickman wrote: > Austin Lesea wrote: > > > > Rick, > > > > Fight it as long as you can, but everyone else is using the more advanced > > tools, and simulating everything (at the companies where they want to be > > successful on the first pcb turn -- as for the others, I don't hear from > > them often anymore....). > > Funny. But I doubt it is very accurate. I have worked at some of the > larger companies making telecom test equipment and I have yet to meet a > board designer who simulates all of the traces. The ones I spoke with > only simulate the clock lines or other signal lines when the timing is > tight with no time for settling. > > Like I said, this is the first time I have heard a chip maker claim that > typical ringing and undershoot can cause chip damage. Of course an > absurdly designed trace and create excessive swings. But the typical > amount of ringing is normally listed in data sheets as being within spec > for chips. > > > And yes, if you do not pay attention now, you will cause ground bounce (50 - > > 60 mA of reflection current per IO is possible), > > Under what conditions is this "possible"? I would expect this to be an > extreme case. The analyis listed here indicated much lower currents > (~35 mA) and only for the brief time (< 1 ns) of the overshoot. If the > device can't handle these low currents without ground bounce, how can it > possibly provide the much larger currents (> 55 mA) for the initial > level change without ground bounce? > > > and with the Virtex II Pro, > > and Spartan 3 if the IOs are operated at 3.3V, you may exceed the Abs Max > > data sheet limits if you do not pay attention to what you are doing. And > > that will cause a reduction in the 20 year projected lifetime. Below 3.0V, > > there are no reliability issues to consider, as the clamp diodes are > > sufficient to protect the IOs. Smaller, faster, less expensive technology > > from the foundries has some drawbacks: leakage current, and IO robustness > > at voltages greater than 3.75 volts being two of them. > > > > The new tools allow for extraction of all pcb parameters, and easy > > simulation of all tracks/traces. You can also create a design that is > > correct by construction: use DCI or series or parallel termination, and > > make 50 ohm (or whatever) traces. Then you do not have to simulate > > everything. > > So the DCI in the S3 chips will allow matching of the chip IO impedance > to the trace, right? > > > Or use a standard: HSTL, SSTL, PCI. Then you also don't have to think. > > But I also simulate to make sure I haven't missed anything. > > I only wish standards really did preclude the "thinking". I have worked > with RS-232 and many others too long to beleive that. > > -- > > Rick "rickman" Collins > > rick.collins@XYarius.com > Ignore the reply address. To email me use the above address with the XY > removed. > > Arius - A Signal Processing Solutions Company > Specializing in DSP and FPGA design URL http://www.arius.com > 4 King Ave 301-682-7772 Voice > Frederick, MD 21701-3110 301-682-7666 FAXArticle: 60943
Allan, For your point 2, it's already implemented in ISE6.1i with the <project>.cmd_log file. :) Again, thanks for the suggestions. And it's best for you to open a case with the Xilinx support for the feature enhancement requests to make sure we capture the requests with a actual case. Regards, Wei Xilinx Applications Allan Herriman wrote: > On Wed, 24 Sep 2003 14:05:29 -0600, Chen Wei Tseng > <chenwei.tseng@xilinx.com> wrote: > > >>Hi Marc, >> >>Xilinx do welcome user inputs on improving the tools. You're more than >>welcomed to let me know or open hotline cases for change requests on >>Xilinx software tools. We all benefits from specific constructive >>suggestions! >> >>Best Regards, Wei >>Xilinx Applications > > > Ok, here are my suggestions for today. > > 1. Allow multiple installations of (different versions of) Xilinx > software on the same machine. Drop the use of the XILINX environment > variable - it's a PITA. > > 2. Add a "save project as script" command to the project manager. > This allows a user to use the GUI to set up their project options, > then save a shell script or batch file and then never use the GUI > again. > > Regards, > AllanArticle: 60944
Last post: See below, Austin rickman wrote: > Symon wrote: > > > > Hi Rick, > > OK, I suppose 'MUST' isn't strictly accurate, you might not care > > whether the design works or not! How about 'SHOULD' instead? ;-) Those > > signals bouncing back and forth may not affect the circuits functional > > operation, but what are you gonna do when it happens on a 5 inch, 32 > > bit data bus and you can't pass the CE/FCC mark tests? Sell it in > > Elbonia, I guess! > > Is there a good market there? If a 5 inch 32 bit data bus without > termination precludes passing CE/FCC RFI tests, then no PC would ever be > sold. Few RFI issues are solved purely at the PC board level. In US > commercial markets, the requirements are very different than consumer > markets as well. Yes, you can sell garbage. I don't think that we are talking about that here: even game toys have to have just about every government and safety lab certification known.... > > > As for ground bounce, if those diodes are dumping energy, be sure > > you've decoupled the Rx IC as well as the Tx one! Generally, it's > > better not to have to rely on the diodes, don't you think? You end up > > trading decoupling capacitors for termination resistors. > > That is assuming that the diodes would be triggered. I seem to recall > that the basic analysis done here showed that this was unlikely. They are triggered at the receive end. Remember the low drive impedance, high terminate impedance t-line case tries to as much as double the voltage at the receive end. Remember Howard running across the room with his pointer and banging into the wall (if you have been to one of his great performances)? Instructive. > > > > I'm not saying simulate every trace. Simulate one, and layout the > > rest accordingly, as I think Austin says in a parallel post. Check the > > PCB layout very carefully, watching out for traces that don't comply > > with your SI design. I like Austin's idea of adopting a standard > > (HSTL, SSTL, PCI), makes it easy. > > That is the part I am not clear about. These traces are all individual > circuits. If you have the luxury of a lot of open board space to route > straight lines here and there, then sure, you can make each one very > similar. On a small, tight board it will be very difficult to make them > that similar. If the signal is critical enough to require a simulation, > then I expect I would need to simulate each of them. Yes. > I am surprized that the Spartan 3 chips are so sensitive to over and > undershoot that this has become a major issue. I have seen lots of high > speed boards and none had FPGAs or any other chips that needed this > degree of analysis to prevent damage. Get off the horse. It is tired already. See my other post. If you are going to have really bad SI, at 3.6V Vcco, AND 85C Tj, then you may have to consider the abs max specs.....so do a good SI job, and you will never get there. In previous families, there were Abs Max specs, and you could go past them, too, with poor SI. This is only different because the numbers are tighter, and the Vccint is now 1.2 volts, and bad SI will make the design fail to function a long time before any IO will fail. Why not encourage designers to be successful (hey, what a concept! if the design works, then we sell more chips!).Article: 60945
What part of it can be commented out. Does the PC care that it is a plug and play connection? Will it fit on a CPLD 95xxx? Regards, James "Antti Lukats" <antti@case2000.com> wrote in message news:80a3aea5.0309242225.6c35065f@posting.google.com... > Jon Elson <jmelson@artsci.wustl.edu> wrote in message news:<3F7208C4.3050506@artsci.wustl.edu>... > > James Williams wrote: > > > > >Is there one with the IEEE 1284 Core VHDL that is in english? > > > > > > > > I poked around a while and found the VHD file, which seems readable. > > I haven't tried to UNDERSTAND it yet, however - that is different. > > > > http://www.nahitech.com/nahitafu/fpgavhdl/ieee1284_2/ieee1284main-ver01.vhd > > good, come alone and you all will learn japanese as god as I ;) > > I dont understand nothing in japanese. > And this is how I read japanese HDL/FPGA pages: > 1 check pictures > 2 check all hyperlinks, even if page is japanese the línks may have > english page names :) > 3 download all HDL files and all archive files, check whats inside > > the link what you found seems to be full IEEE1284 peripheral core with > plug and play support (there is screenshot of the plug and play > enumeration > so I assume it is working and verified on FPGA) > > the design does synthesise out of box for > Xilinx XST 256 Slices > or 60% of XC95 144 > for Actel APA075 its 25% > > the design is larger than commercial IEEE1284 cores, but it has > plug and play enumaration built in (what you can easily comment out if > needed) > > anttiArticle: 60946
Jim Granville wrote: >Steve Lass wrote: > > >>Our limited testing has show Linux to be about 10% faster than Windows >>running PAR. Linux >>also uses less memory. The average is about 6% less and a few really >>big designs that run out >>of memory on Windows XP run fine under Linux. >> >>Steve >> >> > >Do they have the same ceiling ? > Yes, both Windows XP and Linux can address 3G. As far as I know, Windows 2000 will only address 2G. >ISTR comments on (some versions?) of windows only being able to >access 2GB RAM, because MS decided the other 2GB was for them, >not for you. ( and who would want > 2GB anyway.... :) > >Any tests of Linux/AMD 64 bit CPUs P&R ? > Not yet. Steve > >-jg > >Article: 60947
A properly designed Gray counter steps through all binary addresses. It's just the sequence that differes from a binary counter. A normal Linear Shift register counter (LFSR) skips one code, but additional logic can remedy that also. Just for the record... Peter Alfke, Xilinx Applications Denis Gleeson wrote: > > > Ive read about Gray counters but as Im using the counter to step through > SRAM addresses I dont want to loose storage locations in my SRAM just because > my counter doesnt count through all possible binary counts. > > >Article: 60948
I found that it did synthesise into an XC95144, however is does not fit into the device use the fitter of the ISE. Regards, James "Antti Lukats" <antti@case2000.com> wrote in message news:80a3aea5.0309242225.6c35065f@posting.google.com... > Jon Elson <jmelson@artsci.wustl.edu> wrote in message news:<3F7208C4.3050506@artsci.wustl.edu>... > > James Williams wrote: > > > > >Is there one with the IEEE 1284 Core VHDL that is in english? > > > > > > > > I poked around a while and found the VHD file, which seems readable. > > I haven't tried to UNDERSTAND it yet, however - that is different. > > > > http://www.nahitech.com/nahitafu/fpgavhdl/ieee1284_2/ieee1284main-ver01.vhd > > good, come alone and you all will learn japanese as god as I ;) > > I dont understand nothing in japanese. > And this is how I read japanese HDL/FPGA pages: > 1 check pictures > 2 check all hyperlinks, even if page is japanese the línks may have > english page names :) > 3 download all HDL files and all archive files, check whats inside > > the link what you found seems to be full IEEE1284 peripheral core with > plug and play support (there is screenshot of the plug and play > enumeration > so I assume it is working and verified on FPGA) > > the design does synthesise out of box for > Xilinx XST 256 Slices > or 60% of XC95 144 > for Actel APA075 its 25% > > the design is larger than commercial IEEE1284 cores, but it has > plug and play enumaration built in (what you can easily comment out if > needed) > > anttiArticle: 60949
"Denis Gleeson" <dgleeson-2@utvinternet.com> wrote in message news:184c35f9.0309250354.763cf662@posting.google.com... > Hello All > > OK Im a bit confused. > > the verilog code > > always @(posedge CLK or posedge CLR) > begin > if (CLR) > Q <= 20'b0; > else > if (CE) // Is counter Enabled. > begin > Q<=Q+1; > end > end > > produces a ripple counter? Yes, No? I prefer structural verilog, but I would have thought it would be a synchronous counter. > When I look at my simulation results I see glitches in the count output > leading me to assume that I have implemented a ripple counter. > > IS it possible to remove the glitches with a synchronous Binary counter? > If yes what is the verilog code? Even a synchronous counter will glitch, but they should be shorter. The outputs might have different rise and fall times, for example. I don't know if the simulation would show that, though. > Ive read about Gray counters but as Im using the counter to step through > SRAM addresses I dont want to loose storage locations in my SRAM just because > my counter doesnt count through all possible binary counts. Gray counters should count through all possible counts. I do hope you are not changing the address on the SRAM with write enable active. -- glen
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