Site Home   Archive Home   FAQ Home   How to search the Archive   How to Navigate the Archive   
Compare FPGA features and resources   

Threads starting:
1994JulAugSepOctNovDec1994
1995JanFebMarAprMayJunJulAugSepOctNovDec1995
1996JanFebMarAprMayJunJulAugSepOctNovDec1996
1997JanFebMarAprMayJunJulAugSepOctNovDec1997
1998JanFebMarAprMayJunJulAugSepOctNovDec1998
1999JanFebMarAprMayJunJulAugSepOctNovDec1999
2000JanFebMarAprMayJunJulAugSepOctNovDec2000
2001JanFebMarAprMayJunJulAugSepOctNovDec2001
2002JanFebMarAprMayJunJulAugSepOctNovDec2002
2003JanFebMarAprMayJunJulAugSepOctNovDec2003
2004JanFebMarAprMayJunJulAugSepOctNovDec2004
2005JanFebMarAprMayJunJulAugSepOctNovDec2005
2006JanFebMarAprMayJunJulAugSepOctNovDec2006
2007JanFebMarAprMayJunJulAugSepOctNovDec2007
2008JanFebMarAprMayJunJulAugSepOctNovDec2008
2009JanFebMarAprMayJunJulAugSepOctNovDec2009
2010JanFebMarAprMayJunJulAugSepOctNovDec2010
2011JanFebMarAprMayJunJulAugSepOctNovDec2011
2012JanFebMarAprMayJunJulAugSepOctNovDec2012
2013JanFebMarAprMayJunJulAugSepOctNovDec2013
2014JanFebMarAprMayJunJulAugSepOctNovDec2014
2015JanFebMarAprMayJunJulAugSepOctNovDec2015
2016JanFebMarAprMayJunJulAugSepOctNovDec2016
2017JanFebMarAprMayJunJulAugSepOctNovDec2017
2018JanFebMarAprMayJunJulAugSepOctNovDec2018
2019JanFebMarAprMayJunJulAugSepOctNovDec2019
2020JanFebMarAprMay2020

Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z

Custom Search

Messages from 60825

Article: 60825
Subject: Re: Xilinx S3 I/O robustness question
From: Austin Lesea <Austin.Lesea@xilinx.com>
Date: Tue, 23 Sep 2003 07:52:13 -0700
Links: << >>  << T >>  << A >>
Symon,

The line was 440 ps long.

I will send the simulation to you directly, as posting it here bothers the folks that have to
archive the newsgroup (no graphics or html, text only).

Austin

Symon wrote:

> Hi Austin,
>        Agreed, the simulation is best way! My fag-packet calculation
> was a worst case scenario, but still didn't exceed the specification.
> Just wanted to confirm to myself there's no problem at the driver end,
> and that this talk of using 3V VCCO instead of 3.3V was not needed to
> be heeded! (At least for driver pin reasons.)
>        I imagine your simulation gets a lower value for the reflection
> amplitude because the IBIS model includes rise time information and
> chip capacitance, rather than variation of the transistors' impedance.
> (But I'm willing to be shot down in flames!!) My calculation assumed
> instant (worst case) rise time. How long was your lossless t-line? Was
> the flight time longer than the rise time of the signal? (Time for
> signal travel is about 180ps/in, typically.)
>        So, thanks for doing the simulation, I don't suppose you'd
> publish the results just to put this one to bed for good?
>             cheers, Syms
>
> Austin Lesea <Austin.Lesea@xilinx.com> wrote in message news:<3F6F5B7D.7059DDE5@xilinx.com>...
> > Symon,
> >
> > As if often the case, if you do not run a simulation, you will not get results that are
> > even close to the truth (by guessing at what is happening).
> >
> > With a driver impedance of 8.8 ohms (from IBIS simulation), the overshoot/undershoot back
> > at the driver is less than 100 mV (no pcb or t-line losses, IBIS done with Hyperlynx).
> >
> > Why does this not scale exactly as you state?  Because the ON resistance of the
> > transistors is not very linear, and they are less than 8.8 ohms near Vcc or ground.
> >
> > So, unless you simulate the actual circuit, you will not get the actual result.
> >
> > Austin
> >
> > Symon wrote:
> >
> > > Hi Peter,
> > >       If the pin has 10 Ohms of drive impedance the initial sent pulse
> > > will be less than 3.3V, in fact 3.3V * 50/(10+50) = 2.75V, as the 10
> > > Ohms driver drives a 50 Ohm line. The reflected signal from the
> > > unterminated far end is then 2* 2.75V = 5.5V. This reflected pulse
> > > then increases the voltage at the pin to 3.667, as it's driven from 50
> > > Ohms into a 10 Ohm impedance to VCC = 3.3V. This is less than the
> > > absolute maximum rating of 3.75V. Hooray!
> > >       As you say, this calculation disregards the attenuation due to
> > > the trace propagation function, which will further reduce the
> > > amplitude of the pulse as it travels back and forth down the
> > > transmission line(pcb trace). This is caused by skin effect and stuff.
> > > I guess you could also reduce the drive strength of the pin from the
> > > default 12mA, to increase the source impedance.
> > >        The receiver pin is the one that gets the big hit.
> > >         cheers, Symon.
> > >


Article: 60826
Subject: Re: Xilinx S3 I/O robustness question
From: Austin Lesea <Austin.Lesea@xilinx.com>
Date: Tue, 23 Sep 2003 08:03:08 -0700
Links: << >>  << T >>  << A >>
Hal,

Simulation includes a receiver at the end of a 2ns line, and you are correct, it
makes things better.

Why simulate a driver drving nothing?  Unless of course that is a possibility in
a system....not a very useful system, though....

Austin

Hal Murray wrote:

> >       The receiver pin is the one that gets the big hit.
>
> So how bad is that hit?  How good are the protection diodes?
>
> If the clamp diodes are any good they will reduce the reflection
> and make things easier back at the transmitter.
>
> --
> The suespammers.org mail server is located in California.  So are all my
> other mailboxes.  Please do not send unsolicited bulk e-mail or unsolicited
> commercial e-mail to my suespammers.org address or any of my other addresses.
> These are my opinions, not necessarily my employer's.  I hate spam.


Article: 60827
Subject: Re: Xilinx S3 I/O robustness question
From: Austin Lesea <Austin.Lesea@xilinx.com>
Date: Tue, 23 Sep 2003 08:04:19 -0700
Links: << >>  << T >>  << A >>
Austin,

Did both a 440 ps and a 2ns line.  Not to confuse.

Austin

Austin Lesea wrote:

> Hal,
>
> Simulation includes a receiver at the end of a 2ns line, and you are correct, it
> makes things better.
>
> Why simulate a driver drving nothing?  Unless of course that is a possibility in
> a system....not a very useful system, though....
>
> Austin
>
> Hal Murray wrote:
>
> > >       The receiver pin is the one that gets the big hit.
> >
> > So how bad is that hit?  How good are the protection diodes?
> >
> > If the clamp diodes are any good they will reduce the reflection
> > and make things easier back at the transmitter.
> >
> > --
> > The suespammers.org mail server is located in California.  So are all my
> > other mailboxes.  Please do not send unsolicited bulk e-mail or unsolicited
> > commercial e-mail to my suespammers.org address or any of my other addresses.
> > These are my opinions, not necessarily my employer's.  I hate spam.


Article: 60828
Subject: Re: DCM virtex 2 doesn't lose lock
From: Austin Lesea <Austin.Lesea@xilinx.com>
Date: Tue, 23 Sep 2003 08:07:18 -0700
Links: << >>  << T >>  << A >>

Bram,

The DCM is a synchronous state machine, and if the clock is lost, it does not
have the ability to change the LOCKED signal, but the CLKIN_LOST status bit
does go high.

I suggest you use the status bits more fully to determine the true state of the
DCM.

Austin

Bram van de Kerkhof wrote:

> Hi,
>
> I have a design that transmits data trough a cable and sends the clock
> along. At the receiver side
> the clock is going trough a dcm when i disconnect the cable the dcm doesn't
> lose his lock (somtimes it does).
> there is some rubbisch in the hanging cable (status bit is toggling)
>
> what could be the problem. the rubbisch in the cable  is not good enough to
> filter a clock out of it. Even if
> there is no rubbisch the lock doesn't dissapear (have measured it)
>
> Yours Bram
>
> --
> ==================================================
> Bram van de Kerkhof
>
> OCE-Technologies BV
> Building 3N38
>
> St. Urbanusweg 43,
> Venlo, The Netherlands
> P.O. Box 101, 5900 MA Venlo
> ==================================================
> Direct dial : +31-77-359 2148
> Fax           : +31-77-359 5473
> ==================================================
> e-mail       : mailto:bvdk@oce.nl
> ==================================================
> www        : http://www.oce.nl/
> ==================================================



Article: 60829
Subject: Re: FPGA implementation in (V)HDL
From: Brian Drummond <brian@shapes.demon.co.uk>
Date: Tue, 23 Sep 2003 16:19:07 +0100
Links: << >>  << T >>  << A >>
On 22 Sep 2003 12:15:59 -0700, jetmarc@hotmail.com (jetmarc) wrote:

>> a VHDL or Verilog implementation of an FPGA?
>
>I know that somebody started one about 2 years ago, but I can't find
>the bookmark anymore.  The main problem was that the custom FPGA
>needs a custom toolchain, and that makes it a really huge project.
>
>Marc

The logical thing to do would be to combine this with the previous
thread, implement a XC6216 on top of a Virtex-II, use the XC6200 tools
that still exist, and satisfy those folks who can no longer get the
XC6200 for research purposes...


- Brian

Article: 60830
Subject: Re: Regarding XC6216
From: "Steve Casselman" <sc_nospam@vcc.com>
Date: Tue, 23 Sep 2003 15:29:11 GMT
Links: << >>  << T >>  << A >>

> as much as I know XC6216 is the only Xilinx device that has full public
> bitstream documentation (or had at least) also for XC6216 there is
> free JERC6K JBits system inclusive Java sources still downloadable
> from xilinx download site :)
>
> so there are historic and educational reasons to have XC6216, if
> I would have that board would use it for P&R tool testing, as
> bitstream is known and array is relativly simple.
>

I still have a bag of XC6216s. I really wish Xilinx would publish the
bitstream for the  V2Pro. I don't get the logic any more the Pro has DES
encryption so if you want to keep your design secret you can.

Maybe it is time to start an open the bitstream project? Anyone got any good
ideas?

Steve



Article: 60831
Subject: IEEE 1284 Core for Xilinx
From: "James Williams" <james@williams-eng.com>
Date: Tue, 23 Sep 2003 10:52:59 -0500
Links: << >>  << T >>  << A >>
Hello,

Is it possible to get the IEEE 1284 parrallel core for the ISE Webpack?  I
am just a hobbiest and can't afford to pay thousands for the for release of
the ISE.  I just want to be have to use the 1284 parrallel interface on my
device.



Article: 60832
Subject: Re: Regarding XC6216
From: Peter Alfke <peter@xilinx.com>
Date: Tue, 23 Sep 2003 08:53:45 -0700
Links: << >>  << T >>  << A >>
I understand the desire to have XC6216, but the fact is that these parts
are not available. Xilinx, the original manufacturer, does not have a
single part in inventory. (I tried to get one part, and failed!).
So this really is archeology.  Why do you want to spend mental energy on
something you cannot obtain. Why prolong the frustration ?  The part is
dead, because we could not find any volume customers. The baby died for
lack of a loving home outside academia.

If you give me a good reason, I may be able to find a data sheet, but I
will not go on a meaningless wild-goose chase...
Peter Alfke
=======================
Antti Lukats wrote:
> 
> Peter Alfke <peter@xilinx.com> wrote in message news:<3F6F1C81.16801DD9@xilinx.com>...
> > My first answer is: look it up on google. You get 747 hits!
> > Question: Do you need any more?
> > The parts do not exist anymore, so why do you need the data sheet?
> >
> > Peter Alfke, Xilinx
> >
> > "H.Azmi" wrote:
> > >
> > > Hi guyes ,
> > >          Does any body have datasheet for XC6216 ?
> 
> Hi Peter,
> 
> there are people who would like to have XC2616, I actually tried
> to buy XC6216 development board at ebay (Ray Andraka was selling)
> but I was too late :(
> 
> as much as I know XC6216 is the only Xilinx device that has full public
> bitstream documentation (or had at least) also for XC6216 there is
> free JERC6K JBits system inclusive Java sources still downloadable
> from xilinx download site :)
> 
> so there are historic and educational reasons to have XC6216, if
> I would have that board would use it for P&R tool testing, as
> bitstream is known and array is relativly simple.
> 
> antti

Article: 60833
Subject: New to VHDL for Xilinx
From: "James Williams" <james@williams-eng.com>
Date: Tue, 23 Sep 2003 10:57:38 -0500
Links: << >>  << T >>  << A >>
Hello,

I am just learning how to program using VHDL language.  I am trying to
figure out how I can generate a device which detects when two signals change
state at the same time.  Below is a timing diagram.  It must be able to
detect whether both signals changed state in the same time.
    ________
A:                \_____________
                    _____________
B:________/
                  ^--- I need to detect this state change.

What is the best approach for this and how would it look in VHDL?

Thanks,


James



Article: 60834
Subject: Re: Synchronous counter enable pulse length
From: Peter Alfke <peter@xilinx.com>
Date: Tue, 23 Sep 2003 08:58:04 -0700
Links: << >>  << T >>  << A >>


Hal Murray wrote:
> 
> >All smart chip manufacturers try to err on the side of zero or negative
> >hold time, and accept the corresponding larger set-up time.
> 
> Is there anything in the physics that encourages this?
> 
No, it is just so much easier to sell something when you can tell the
potential customer: "Don't worry about hold time, as long as you use a
global clock. Period, no ifs and buts."

Peter Alfke

Article: 60835
Subject: Re: Synchronous counter enable pulse length
From: Peter Alfke <peter@xilinx.com>
Date: Tue, 23 Sep 2003 09:03:47 -0700
Links: << >>  << T >>  << A >>
Starting with the XC3000, 16 years ago, Xilinx has always offered a
delay circuit in the I/O data input, in order to minimize the danger of
a hold-time issue. In XC3000 this delay was permanent, in XC4000 and
later, it was optional.
We knew that we left performance on the table, but we thought (and
think) that satisfied customers are more important than the ultimate
bragging numbers...
Peter Alfke

> I don't know that it was every explained why, but there have been
> descriptions of the Cray-1 that included PC board traces taking extra long
> paths, like zig-zags, to lengthen the propagation time.  It may have been to
> match hold time.
> 
> -- glen

Article: 60836
Subject: Re: Xilinx S3 I/O robustness question
From: rickman <spamgoeshere4@yahoo.com>
Date: Tue, 23 Sep 2003 12:04:02 -0400
Links: << >>  << T >>  << A >>
But if you are simulating to check the possibility of damage, it seems
reasonable to allow for an unconnected trace due to a component being
left off a board intentionally or not or the possiblity of an open trace
on the board.  I don't think many people would expect an open trace to
be the cause of a chip failure in a properly designed board.  If you
don't analyze for this, a chip may have a higher than expected failure
rate due to typical repairable board defects.  


Austin Lesea wrote:
> 
> Hal,
> 
> Simulation includes a receiver at the end of a 2ns line, and you are correct, it
> makes things better.
> 
> Why simulate a driver drving nothing?  Unless of course that is a possibility in
> a system....not a very useful system, though....
> 
> Austin
> 
> Hal Murray wrote:
> 
> > >       The receiver pin is the one that gets the big hit.
> >
> > So how bad is that hit?  How good are the protection diodes?
> >
> > If the clamp diodes are any good they will reduce the reflection
> > and make things easier back at the transmitter.
> >
> > --
> > The suespammers.org mail server is located in California.  So are all my
> > other mailboxes.  Please do not send unsolicited bulk e-mail or unsolicited
> > commercial e-mail to my suespammers.org address or any of my other addresses.
> > These are my opinions, not necessarily my employer's.  I hate spam.

-- 

Rick "rickman" Collins

rick.collins@XYarius.com
Ignore the reply address. To email me use the above address with the XY
removed.

Arius - A Signal Processing Solutions Company
Specializing in DSP and FPGA design      URL http://www.arius.com
4 King Ave                               301-682-7772 Voice
Frederick, MD 21701-3110                 301-682-7666 FAX

Article: 60837
Subject: Re: Xilinx S3 I/O robustness question
From: rickman <spamgoeshere4@yahoo.com>
Date: Tue, 23 Sep 2003 12:10:07 -0400
Links: << >>  << T >>  << A >>
Hal Murray wrote:
> 
> >       The receiver pin is the one that gets the big hit.
> 
> So how bad is that hit?  How good are the protection diodes?
> 
> If the clamp diodes are any good they will reduce the reflection
> and make things easier back at the transmitter.

This is a good question.  So far I have only read people considering the
S3 chip driving.  What about the case where is is on the receiving end
of the signal?  

My designs typically don't consider signal integrity on traces other
than edge sensitive clock lines and chip enables.  For non-edge
sensitive signals, I have always treated it a bit like metastability,
allow some time for the signal to settle out and all will be good by the
time of the clock edge.  But if we have to consider *every* trace on the
board for reflections and overshoot, board design can become a
nightmare!  

-- 

Rick "rickman" Collins

rick.collins@XYarius.com
Ignore the reply address. To email me use the above address with the XY
removed.

Arius - A Signal Processing Solutions Company
Specializing in DSP and FPGA design      URL http://www.arius.com
4 King Ave                               301-682-7772 Voice
Frederick, MD 21701-3110                 301-682-7666 FAX

Article: 60838
Subject: Re: Xilinx S3 I/O robustness question
From: Austin Lesea <Austin.Lesea@xilinx.com>
Date: Tue, 23 Sep 2003 09:18:16 -0700
Links: << >>  << T >>  << A >>
Rick,

Good point, and without the termination (load or receiver) the difference is:

100 mV higher (lower) peak voltage (+/- 237 mV from Vcco and ground).

Still well within the datasheet limits.

Again, simulate what you are doing!

http://support.xilinx.com/xlnx/xweb/xil_tx_display.jsp?BV_SessionID=@@@@2073323889.1064333725@@@@&BV_EngineID=ccceadcjhgejgjicflgcefldfgldgjh.0&sGlobalNavPick=&sSecondaryNavPick=&category=&iLanguageID=1&multPartNum=1&sTechX_ID=al_fathers

Austin

rickman wrote:

> But if you are simulating to check the possibility of damage, it seems
> reasonable to allow for an unconnected trace due to a component being
> left off a board intentionally or not or the possiblity of an open trace
> on the board.  I don't think many people would expect an open trace to
> be the cause of a chip failure in a properly designed board.  If you
> don't analyze for this, a chip may have a higher than expected failure
> rate due to typical repairable board defects.
>
> Austin Lesea wrote:
> >
> > Hal,
> >
> > Simulation includes a receiver at the end of a 2ns line, and you are correct, it
> > makes things better.
> >
> > Why simulate a driver drving nothing?  Unless of course that is a possibility in
> > a system....not a very useful system, though....
> >
> > Austin
> >
> > Hal Murray wrote:
> >
> > > >       The receiver pin is the one that gets the big hit.
> > >
> > > So how bad is that hit?  How good are the protection diodes?
> > >
> > > If the clamp diodes are any good they will reduce the reflection
> > > and make things easier back at the transmitter.
> > >
> > > --
> > > The suespammers.org mail server is located in California.  So are all my
> > > other mailboxes.  Please do not send unsolicited bulk e-mail or unsolicited
> > > commercial e-mail to my suespammers.org address or any of my other addresses.
> > > These are my opinions, not necessarily my employer's.  I hate spam.
>
> --
>
> Rick "rickman" Collins
>
> rick.collins@XYarius.com
> Ignore the reply address. To email me use the above address with the XY
> removed.
>
> Arius - A Signal Processing Solutions Company
> Specializing in DSP and FPGA design      URL http://www.arius.com
> 4 King Ave                               301-682-7772 Voice
> Frederick, MD 21701-3110                 301-682-7666 FAX


Article: 60839
Subject: Re: Regarding XC6216
From: "Tim" <tim@rockylogic.com.nooospam.com>
Date: Tue, 23 Sep 2003 17:22:32 +0100
Links: << >>  << T >>  << A >>
Antti Lukats wrote:
> as much as I know XC6216 is the only Xilinx device that has full
> public
> bitstream documentation (or had at least) also for XC6216 there is
> free JERC6K JBits system inclusive Java sources still downloadable
> from xilinx download site :)
>
> so there are historic and educational reasons to have XC6216, if
> I would have that board would use it for P&R tool testing, as
> bitstream is known and array is relativly simple.

Could you use the Virtual FPGA project on a modern device?



Article: 60840
Subject: Re: New to VHDL for Xilinx
From: Peter Alfke <peter@xilinx.com>
Date: Tue, 23 Sep 2003 09:23:42 -0700
Links: << >>  << T >>  << A >>
James, in the physical world there is no "at the same time".
You have so say " within x picoseconds or nanoseconds or microseconds or milliseconds"
And you should also specify a tolerance on the accuracy of your window...

In a pracical circuit implementation, you could run the B signal through
a chain of cascaded LUTs, each also having its own flip-flop, clocked by A.
After the A transition, you can observe the flip-flops and see whether a
B signal change was travelling through the LUT chain.
If you want finer resolution than about 0.5 ns, you can use the carry
chain and achieve a resolution of 50 picoseconds.
But first you have to figure out the meaning of "simultaneous"!
Peter Alfke, Xilinx Applications
====================================
James Williams wrote:
> 
> Hello,
> 
> I am just learning how to program using VHDL language.  I am trying to
> figure out how I can generate a device which detects when two signals change
> state at the same time.  Below is a timing diagram.  It must be able to
> detect whether both signals changed state in the same time.
>     ________
> A:                \_____________
>                     _____________
> B:________/
>                   ^--- I need to detect this state change.
> 
> What is the best approach for this and how would it look in VHDL?
> 
> Thanks,
> 
> James

Article: 60841
Subject: Re: New to VHDL for Xilinx
From: rickman <spamgoeshere4@yahoo.com>
Date: Tue, 23 Sep 2003 12:34:24 -0400
Links: << >>  << T >>  << A >>
James Williams wrote:
> 
> Hello,
> 
> I am just learning how to program using VHDL language.  I am trying to
> figure out how I can generate a device which detects when two signals change
> state at the same time.  Below is a timing diagram.  It must be able to
> detect whether both signals changed state in the same time.
> 
> A: -------|_____________
> 
> B:________|-------------
>           ^--- I need to detect this state change.
> 
> What is the best approach for this and how would it look in VHDL?

How do you define "at the same time"?  This would imply that there is an
instant in which the transition is made.  In reality the transition
takes an amount of time, during which the voltage that represents the
logic state goes from one valid range, through the invalid range to the
other valid range.  So there is a grey area in both time and voltage
where you don't actually know if the signal is a 1 or a 0.  

If you can work though that issue, the logic required would need a
memory (FF) to know the past state of the signals.  If you see that
either signal has changed state, but the XOR of the two signals has not
changed state, then you know that both inputs have changed state.  

So the next question is, exactly what do you need as an output?  This is
not a typical circuit needed in a typical design.  So exactly how it
will be implemented will depend on just what you are looking for as an
output (how you plan to use it).  

This also sounds like a homework problem.  I expect the assignment is
not to design a circuit since any circuit for this will be full of
hazards.  More likely this is to make you think about the problems in
such a circuit.  

-- 

Rick "rickman" Collins

rick.collins@XYarius.com
Ignore the reply address. To email me use the above address with the XY
removed.

Arius - A Signal Processing Solutions Company
Specializing in DSP and FPGA design      URL http://www.arius.com
4 King Ave                               301-682-7772 Voice
Frederick, MD 21701-3110                 301-682-7666 FAX

Article: 60842
Subject: Re: New to VHDL for Xilinx
From: "James Williams" <james@williams-eng.com>
Date: Tue, 23 Sep 2003 12:11:07 -0500
Links: << >>  << T >>  << A >>
This is to detect the negotiation phase of the IEEE 1284 parrallel port.

I will use the output to disable the current active communications mode, and
begin a negation phase to determine and set a new mode of operation.  I must
detect the changes of both of these signals because they are also used for
compatibility mode and EPP mode tranfer opperations, but they don't
transistion at the same time when in commucations mode.  The transition of
these two signals at near the same time only occurs at the negotiation
phase.

Regards,

James.

"rickman" <spamgoeshere4@yahoo.com> wrote in message
news:3F707610.FD7BBB09@yahoo.com...
> James Williams wrote:
> >
> > Hello,
> >
> > I am just learning how to program using VHDL language.  I am trying to
> > figure out how I can generate a device which detects when two signals
change
> > state at the same time.  Below is a timing diagram.  It must be able to
> > detect whether both signals changed state in the same time.
> >
> > A: -------|_____________
> >
> > B:________|-------------
> >           ^--- I need to detect this state change.
> >
> > What is the best approach for this and how would it look in VHDL?
>
> How do you define "at the same time"?  This would imply that there is an
> instant in which the transition is made.  In reality the transition
> takes an amount of time, during which the voltage that represents the
> logic state goes from one valid range, through the invalid range to the
> other valid range.  So there is a grey area in both time and voltage
> where you don't actually know if the signal is a 1 or a 0.
>
> If you can work though that issue, the logic required would need a
> memory (FF) to know the past state of the signals.  If you see that
> either signal has changed state, but the XOR of the two signals has not
> changed state, then you know that both inputs have changed state.
>
> So the next question is, exactly what do you need as an output?  This is
> not a typical circuit needed in a typical design.  So exactly how it
> will be implemented will depend on just what you are looking for as an
> output (how you plan to use it).
>
> This also sounds like a homework problem.  I expect the assignment is
> not to design a circuit since any circuit for this will be full of
> hazards.  More likely this is to make you think about the problems in
> such a circuit.
>
> -- 
>
> Rick "rickman" Collins
>
> rick.collins@XYarius.com
> Ignore the reply address. To email me use the above address with the XY
> removed.
>
> Arius - A Signal Processing Solutions Company
> Specializing in DSP and FPGA design      URL http://www.arius.com
> 4 King Ave                               301-682-7772 Voice
> Frederick, MD 21701-3110                 301-682-7666 FAX



Article: 60843
Subject: Re: Xilinx Parallel Cable 4 (PC4) and Platform Flash JTAG
From: Chen Wei Tseng <chenwei.tseng@xilinx.com>
Date: Tue, 23 Sep 2003 11:18:19 -0600
Links: << >>  << T >>  << A >>
Antti,

Let me try to summarize the points here.

-Yes, parallel cable IV is only supported by iMPACT to program all 
Xilinx parts. It has bypass function for 3rd party support. It supports 
BSCAN operation for Xilinx parts via iMPACT.
- There are currently no plans to support playing STAPL files in iMPACT
- The Debug Chain GUI functionality was enhanced for 6.1i iMPACT to 
provide TDO capture ability during DR-SCAN and IR-SCAN functions. The 
TAP state machine is also provided in the GUI as a reference.
    The Debug Chain feature was included for simple chain debugging, and 
device debugging using the capture-IR bits read back on TDO.

     Example iMPACT log:
         // *** BATCH CMD : bsdebug -start
         // *** BATCH CMD : bsdebug -tms 1 -tdi 1 -tck 5
         TDO Capture Data: 0
         // *** BATCH CMD : bsdebug -scanir 11111111
         TDO Capture Data: 00000001
         // *** BATCH CMD : bsdebug -scanir 11111110
         TDO Capture Data: 00000001
         // *** BATCH CMD : bsdebug -scandr 11111111111111111111111111111111
         TDO Capture Data: 00000101000000100110000010010011

-Yes, Debug chain function would not be effective to program a part. 
Third Party Boundary Scan Tools, Automatic Test Equipment (ATE) Tools, 
or Embedded Solutions are the alternatives for programming Xilinx 
devices along with third party devices. I'm sure you know a lot more 
about this. 
http://www.support.xilinx.com/xlnx/xil_prodcat_systemsolution.jsp?title=isp_3ptytools_page 
 
http://www.support.xilinx.com/xlnx/xil_prodcat_product.jsp?title=isp_ate_page

- Thanks for your suggestions in this e-mail thread. Please don't 
hesitate to open a case with the Xilinx hotline for other additional 
suggestions that you have for iMPACT to make it a more user-friendly tool.

Regards, Wei
Xilinx Applications

Antti Lukats wrote:
> Chen Wei Tseng <chenwei.tseng@xilinx.com> wrote in message news:<bkn59c$ki52@cliff.xsj.xilinx.com>...
> 
>>Antti,
>>
>>iMPACT does allow user to download, verify, get device ID via JTAG. For 
>>other functions such as EXTEST, INTEST, etc, you can shift in such 
>>instructions with iMPACT's Debug Chain functionality. This feature 
>>allows you to move through the 16 TAP controller states and shift in TDI 
>>data.
>>
>>With 6.1i iMPACT you'll be able to genrate and program the Xilinx part 
>>with SVF (via inbuild XSVF player function).
>>
>>If iMPACT isn't detecting the Parallel Cable for you, please see Xilinx 
>>solution 15742 for debugging tips and contact the Xilinx hotline support 
>>for further issues.
>>
>>Regards, Wei
>>Xilinx Applications
>>
>>Antti Lukats wrote:
> 
> 
> Dear Xilinx Applications!
> 
> thank you for the answer, but it is no anser actually, - see
> using ISE 5.2, if I want to play a STAPL file that programs a 2MB
> Flash connected to a Xilinx FPGA how do I do it with Cable IV?
> Answer is I CAN NOT.
> 
> With Cable III there there are no problems, I just execute the STAPL
> with a STAPL player and its all done.
> 
> Your answer about using 'Debug Chain Functionality' is really really stupid!
> As far as I can see it is only possible todo it in iteractive mode.
> To programa 2MB flash, it takes maybe over 10,000,000,000 transactions
> on JTAG port (depends on chain lenght) if I do it manually by clicking
> on buttons in iMpact - ridiculuous.
> 
> 
> if new iMpact allows SVF playback its a little bit help, but iMpact
> is really really a nighmare (as others on this list have said also)
> 
> thanks for your time (well, you get paid for it)
> 
> antti lukats
> PS my statement stays: Cable IV is not useable for Boundary Scan.
> 
> PPS if you now say I a stupid and should read iMpact manual, then
> FYI I am not and I just did:
> 
> "bsdebug [-start] [-reset] [-stop] [-tms 0|1] [-tdi
> 0|1] [-tck <number>] [-loop <number>] :Executes the
> 
> Boundary-Scan Debug instruction which shifts in the instruction
> and data values specified by -tms and -tdi."
> 
> 
> There is no way to capture TDO !!!!! 
> what means the debug chain batch command can not be used for boundary scan.


Article: 60844
Subject: Re: Xilinx S3 I/O robustness question
From: Austin Lesea <Austin.Lesea@xilinx.com>
Date: Tue, 23 Sep 2003 10:28:47 -0700
Links: << >>  << T >>  << A >>



Rick,

You are going to have to consider the receiving end SI.

In addition to violating the specifications (possible) you can also create
EMI/RFI, and cause substatial substrate and Vcco bounce by slamming the
clamp diodes at the inputs.  The bounce leads to changing the substrate
(ground) and Vcco on die, which causes jitter, and timing failures.  All of
this is trivially prevented by choosing the right series termination at the
driver (or using DCI drivers).

With the Vccint at 1.5V and dropping fast, ground bounce is now becoming
public enemy number 1.

Like I said, you can't get around LA without a car.  Get the simulator.  Use
it.

Austin

rickman wrote:

> Hal Murray wrote:
> >
> > >       The receiver pin is the one that gets the big hit.
> >
> > So how bad is that hit?  How good are the protection diodes?
> >
> > If the clamp diodes are any good they will reduce the reflection
> > and make things easier back at the transmitter.
>
> This is a good question.  So far I have only read people considering the
> S3 chip driving.  What about the case where is is on the receiving end
> of the signal?
>
> My designs typically don't consider signal integrity on traces other
> than edge sensitive clock lines and chip enables.  For non-edge
> sensitive signals, I have always treated it a bit like metastability,
> allow some time for the signal to settle out and all will be good by the
> time of the clock edge.  But if we have to consider *every* trace on the
> board for reflections and overshoot, board design can become a
> nightmare!
>
> --
>
> Rick "rickman" Collins
>
> rick.collins@XYarius.com
> Ignore the reply address. To email me use the above address with the XY
> removed.
>
> Arius - A Signal Processing Solutions Company
> Specializing in DSP and FPGA design      URL http://www.arius.com
> 4 King Ave                               301-682-7772 Voice
> Frederick, MD 21701-3110                 301-682-7666 FAX




Article: 60845
Subject: Re: Added Keyboard controller to C-NIT
From: antti@case2000.com (Antti Lukats)
Date: 23 Sep 2003 10:32:50 -0700
Links: << >>  << T >>  << A >>
antti@case2000.com (Antti Lukats) wrote in message news:<80a3aea5.0309230458.3934bcc3@posting.google.com>...
> do_not_reply_to_this_addr@yahoo.com (Sumit Gupta) wrote in message news:<ae680d56.0309230000.265514b4@posting.google.com>...
> > I have added a keyboard controller to my soc implementation.
> > 
> > http://www.c-nit.net
> 
> download of cpu.v and soc.zip are bad links http: 404 not found
> please fix
> 
> antti
if you copy the url to those files and fix the \ to / manually then
all the files are downloadable

antti

Article: 60846
Subject: Corrupt Xilinx 18vxx poms
From: afocacci@yahoo.com (Virtex_User)
Date: 23 Sep 2003 10:42:29 -0700
Links: << >>  << T >>  << A >>
I'm using a Xilinx 18V04 prom and find that it occasionaly loses it's
program.  I can program the prom without a problem.  I use it for
months, and then one dy when I turn on the board, some of the bits on
the prom are incorrect.  If I reprogram the prom everything works
normally again.  This has happened on several different cards.  Has
anyone else seen this problem.  I searched through the archives on
this newsgroup, and found someone with the exact same problem, but no
solution was offered.  I contacted xilinx, and they have one of the
parts that failed, but claim nothing is wrong with it.  Any
information would be  much appreciated.

Article: 60847
Subject: Re: New to VHDL for Xilinx
From: rickman <spamgoeshere4@yahoo.com>
Date: Tue, 23 Sep 2003 14:37:01 -0400
Links: << >>  << T >>  << A >>
Did my answer help you?  I understand what you are tying to do, but your
description still is not clear enough to tell me exactly what you want
for an output. 

Can you define exactly the state of the two signals at this point?  Will
one always be low going high or will it vary? 


James Williams wrote:
> 
> This is to detect the negotiation phase of the IEEE 1284 parrallel port.
> 
> I will use the output to disable the current active communications mode, and
> begin a negation phase to determine and set a new mode of operation.  I must
> detect the changes of both of these signals because they are also used for
> compatibility mode and EPP mode tranfer opperations, but they don't
> transistion at the same time when in commucations mode.  The transition of
> these two signals at near the same time only occurs at the negotiation
> phase.
> 
> Regards,
> 
> James.
> 
> "rickman" <spamgoeshere4@yahoo.com> wrote in message
> news:3F707610.FD7BBB09@yahoo.com...
> > James Williams wrote:
> > >
> > > Hello,
> > >
> > > I am just learning how to program using VHDL language.  I am trying to
> > > figure out how I can generate a device which detects when two signals
> change
> > > state at the same time.  Below is a timing diagram.  It must be able to
> > > detect whether both signals changed state in the same time.
> > >
> > > A: -------|_____________
> > >
> > > B:________|-------------
> > >           ^--- I need to detect this state change.
> > >
> > > What is the best approach for this and how would it look in VHDL?
> >
> > How do you define "at the same time"?  This would imply that there is an
> > instant in which the transition is made.  In reality the transition
> > takes an amount of time, during which the voltage that represents the
> > logic state goes from one valid range, through the invalid range to the
> > other valid range.  So there is a grey area in both time and voltage
> > where you don't actually know if the signal is a 1 or a 0.
> >
> > If you can work though that issue, the logic required would need a
> > memory (FF) to know the past state of the signals.  If you see that
> > either signal has changed state, but the XOR of the two signals has not
> > changed state, then you know that both inputs have changed state.
> >
> > So the next question is, exactly what do you need as an output?  This is
> > not a typical circuit needed in a typical design.  So exactly how it
> > will be implemented will depend on just what you are looking for as an
> > output (how you plan to use it).
> >
> > This also sounds like a homework problem.  I expect the assignment is
> > not to design a circuit since any circuit for this will be full of
> > hazards.  More likely this is to make you think about the problems in
> > such a circuit.
> >
> > --
> >
> > Rick "rickman" Collins
> >
> > rick.collins@XYarius.com
> > Ignore the reply address. To email me use the above address with the XY
> > removed.
> >
> > Arius - A Signal Processing Solutions Company
> > Specializing in DSP and FPGA design      URL http://www.arius.com
> > 4 King Ave                               301-682-7772 Voice
> > Frederick, MD 21701-3110                 301-682-7666 FAX

-- 

Rick "rickman" Collins

rick.collins@XYarius.com
Ignore the reply address. To email me use the above address with the XY
removed.

Arius - A Signal Processing Solutions Company
Specializing in DSP and FPGA design      URL http://www.arius.com
4 King Ave                               301-682-7772 Voice
Frederick, MD 21701-3110                 301-682-7666 FAX

Article: 60848
Subject: Re: Corrupt Xilinx 18vxx poms
From: Chen Wei Tseng <chenwei.tseng@xilinx.com>
Date: Tue, 23 Sep 2003 12:54:38 -0600
Links: << >>  << T >>  << A >>
Hi,

A couple things to check.

Please ensure you're using 5.2i service pack 3 iMPACT for programming.
After that, can you please perform a verify?

If you've checked this already, can you please open/reopen a case with 
the Xilinx hotline and e-mail me directly with your case number? I'll 
work with you and the hotline regarding this issue.

Regards, Wei
Xilinx Applications

Virtex_User wrote:

> I'm using a Xilinx 18V04 prom and find that it occasionaly loses it's
> program.  I can program the prom without a problem.  I use it for
> months, and then one dy when I turn on the board, some of the bits on
> the prom are incorrect.  If I reprogram the prom everything works
> normally again.  This has happened on several different cards.  Has
> anyone else seen this problem.  I searched through the archives on
> this newsgroup, and found someone with the exact same problem, but no
> solution was offered.  I contacted xilinx, and they have one of the
> parts that failed, but claim nothing is wrong with it.  Any
> information would be  much appreciated.


Article: 60849
Subject: Re: New to VHDL for Xilinx
From: "James Williams" <james@williams-eng.com>
Date: Tue, 23 Sep 2003 14:39:30 -0500
Links: << >>  << T >>  << A >>
A(C3) Is active high, I.E I am interested in the rising edge.
B(C1) Is active low, IE I am interested in the trailing edge (High to low
transition).

Lets make Q1 and Q2 the outputs with one addition output called NEG which is
latched high only when A's rising edge is detected when B's falling edge is
detected.  Something like the following C puersudeo code.

//ON Rising (A) OR trailing (B)
bool APrev,BPrev;
APrev=A;
BPrev=B;
while(1)
{
   if(RisingEdge(A) && A=true&& BPrev !=B)
  {
      NEG=true;

  }
  elseif(TrailingEdge(B) && (A==APrev) && A==true)
 {
     //Nibble read
    ReadNibble();
  }
  elseif(Trailing(B) && A!=true)
  {
     CompatibilityWrite();
  }
  BPrev = B;
  APrev= A;
}

Anyway, something like this.

Regards,

James


"rickman" <spamgoeshere4@yahoo.com> wrote in message
news:3F7092CD.48DC74CF@yahoo.com...
> Did my answer help you?  I understand what you are tying to do, but your
> description still is not clear enough to tell me exactly what you want
> for an output.
>
> Can you define exactly the state of the two signals at this point?  Will
> one always be low going high or will it vary?
>
>
> James Williams wrote:
> >
> > This is to detect the negotiation phase of the IEEE 1284 parrallel port.
> >
> > I will use the output to disable the current active communications mode,
and
> > begin a negation phase to determine and set a new mode of operation.  I
must
> > detect the changes of both of these signals because they are also used
for
> > compatibility mode and EPP mode tranfer opperations, but they don't
> > transistion at the same time when in commucations mode.  The transition
of
> > these two signals at near the same time only occurs at the negotiation
> > phase.
> >
> > Regards,
> >
> > James.
> >
> > "rickman" <spamgoeshere4@yahoo.com> wrote in message
> > news:3F707610.FD7BBB09@yahoo.com...
> > > James Williams wrote:
> > > >
> > > > Hello,
> > > >
> > > > I am just learning how to program using VHDL language.  I am trying
to
> > > > figure out how I can generate a device which detects when two
signals
> > change
> > > > state at the same time.  Below is a timing diagram.  It must be able
to
> > > > detect whether both signals changed state in the same time.
> > > >
> > > > A: -------|_____________
> > > >
> > > > B:________|-------------
> > > >           ^--- I need to detect this state change.
> > > >
> > > > What is the best approach for this and how would it look in VHDL?
> > >
> > > How do you define "at the same time"?  This would imply that there is
an
> > > instant in which the transition is made.  In reality the transition
> > > takes an amount of time, during which the voltage that represents the
> > > logic state goes from one valid range, through the invalid range to
the
> > > other valid range.  So there is a grey area in both time and voltage
> > > where you don't actually know if the signal is a 1 or a 0.
> > >
> > > If you can work though that issue, the logic required would need a
> > > memory (FF) to know the past state of the signals.  If you see that
> > > either signal has changed state, but the XOR of the two signals has
not
> > > changed state, then you know that both inputs have changed state.
> > >
> > > So the next question is, exactly what do you need as an output?  This
is
> > > not a typical circuit needed in a typical design.  So exactly how it
> > > will be implemented will depend on just what you are looking for as an
> > > output (how you plan to use it).
> > >
> > > This also sounds like a homework problem.  I expect the assignment is
> > > not to design a circuit since any circuit for this will be full of
> > > hazards.  More likely this is to make you think about the problems in
> > > such a circuit.
> > >
> > > --
> > >
> > > Rick "rickman" Collins
> > >
> > > rick.collins@XYarius.com
> > > Ignore the reply address. To email me use the above address with the
XY
> > > removed.
> > >
> > > Arius - A Signal Processing Solutions Company
> > > Specializing in DSP and FPGA design      URL http://www.arius.com
> > > 4 King Ave                               301-682-7772 Voice
> > > Frederick, MD 21701-3110                 301-682-7666 FAX
>
> -- 
>
> Rick "rickman" Collins
>
> rick.collins@XYarius.com
> Ignore the reply address. To email me use the above address with the XY
> removed.
>
> Arius - A Signal Processing Solutions Company
> Specializing in DSP and FPGA design      URL http://www.arius.com
> 4 King Ave                               301-682-7772 Voice
> Frederick, MD 21701-3110                 301-682-7666 FAX





Site Home   Archive Home   FAQ Home   How to search the Archive   How to Navigate the Archive   
Compare FPGA features and resources   

Threads starting:
1994JulAugSepOctNovDec1994
1995JanFebMarAprMayJunJulAugSepOctNovDec1995
1996JanFebMarAprMayJunJulAugSepOctNovDec1996
1997JanFebMarAprMayJunJulAugSepOctNovDec1997
1998JanFebMarAprMayJunJulAugSepOctNovDec1998
1999JanFebMarAprMayJunJulAugSepOctNovDec1999
2000JanFebMarAprMayJunJulAugSepOctNovDec2000
2001JanFebMarAprMayJunJulAugSepOctNovDec2001
2002JanFebMarAprMayJunJulAugSepOctNovDec2002
2003JanFebMarAprMayJunJulAugSepOctNovDec2003
2004JanFebMarAprMayJunJulAugSepOctNovDec2004
2005JanFebMarAprMayJunJulAugSepOctNovDec2005
2006JanFebMarAprMayJunJulAugSepOctNovDec2006
2007JanFebMarAprMayJunJulAugSepOctNovDec2007
2008JanFebMarAprMayJunJulAugSepOctNovDec2008
2009JanFebMarAprMayJunJulAugSepOctNovDec2009
2010JanFebMarAprMayJunJulAugSepOctNovDec2010
2011JanFebMarAprMayJunJulAugSepOctNovDec2011
2012JanFebMarAprMayJunJulAugSepOctNovDec2012
2013JanFebMarAprMayJunJulAugSepOctNovDec2013
2014JanFebMarAprMayJunJulAugSepOctNovDec2014
2015JanFebMarAprMayJunJulAugSepOctNovDec2015
2016JanFebMarAprMayJunJulAugSepOctNovDec2016
2017JanFebMarAprMayJunJulAugSepOctNovDec2017
2018JanFebMarAprMayJunJulAugSepOctNovDec2018
2019JanFebMarAprMayJunJulAugSepOctNovDec2019
2020JanFebMarAprMay2020

Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z

Custom Search