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Messages from 60425

Article: 60425
Subject: Re: Error when downloading with EDK
From: Aurelian Lazarut <aurash@xilinx.com>
Date: Fri, 12 Sep 2003 16:06:34 +0100
Links: << >>  << T >>  << A >>
Antti,

XPS is using Impact (in batch mode) but if you are having trouble with XPS let me
know so I can help you
Cheers,
Aurash

Antti Lukats wrote:

> dont try to download with XPS (waste of time)
> download with impact manually, or if that doesnt work
> use Chipscope for downloading - for some of the boards
> we have Chipscope is only thing that works, dont understand
> why xilinx cant make their download software to work.
>
> antti
>
> > When I try to download it, gives the error below, what is wrong??? I am
> > unsign the Insight/Memec V2MB1000 Virtex2 evaluation board, if it is
> >
> > INFO:iMPACT:1366 -
> >    Reading etc\xcr3064xl_vq44.bsd...
> > // *** BATCH CMD : program -p 2
> > Validating chain...
> > INFO:iMPACT:1209 - Testing for '0' at position 12.The Instruction capture of
> > the
> >    device 2 does not match expected capture.
> > INFO:iMPACT:1206 - Instruction Capture = '1111100000001110101'
> > INFO:iMPACT:1207 - Expected    Capture = '000XXX01XXXX0100001'

--
 __
/ /\/\ Aurelian Lazarut
\ \  / System Verification Engineer
/ /  \ Xilinx Ireland
\_\/\/

phone: 353 01 4032639
fax: 353 01 4640324



Article: 60426
Subject: Re: Metatstable Modeling
From: "John_H" <johnhandwork@mail.com>
Date: Fri, 12 Sep 2003 15:12:41 GMT
Links: << >>  << T >>  << A >>

"Jim Granville" <jim.granville@designtools.co.nz> wrote in message
news:3F60E3A8.116A@designtools.co.nz...
> Peter Alfke wrote:
  <snip>
> > Measurements on Virtex-IIPro flip-flops showed that the metastable
> > window is:
> >
> > . 0.07 femtoseconds for a delay of 1.5 ns.
> > . The window gets a million times smaller for every additional 0.5 ns of
delay.
> >
> > Every CMOS flip-flop will behave similarily. The manufacturer just has
> > to give you the two parameters ( x femtoseconds at a specified delay,
> > and y times smaller per ns of additional delay)
  <snip>
>  That's a "specific systems-oriented statistical calculation".
> Please demonstrate how to apply the above x & y, to give me
> all the information I seek.
>
> -jg

The asynchronous system produces even distribution across the sampling clock
cycle.
The synchronous system with arbitrary phase gives you a lumped distribution
at the phase offset.
The critical point to realize that you won't get a system to be consistently
going metastable is that there is *significant* jitter in the sampling and
data clocks relative to the metastability window.

Determine the distribution of the data relative to the sample point.  The
peak of this (gaussian?) distribution will be the worst-case error point.
What percentage of that statistical distribution is within the 0.07
femtosecond window?  This provides for the "worst case" for management or
for engineers.

It may not have been as easy when the metastability window was much larger
than the system jitter.



Article: 60427
Subject: Downloading into XCV600 FPGA using PCI
From: fpga_uk@yahoo.co.uk (Isaac)
Date: 12 Sep 2003 08:45:54 -0700
Links: << >>  << T >>  << A >>
Hi Guys, 

I have written program in a way that I have logic which is being
already download in to FPGA( PCI ). In my C code I am using API
function to write to FPGA and then on the same bus but using different
Address I am reading the values out of FPGA. What I have in my C code
that I have used Sleep()command make pause then to execite the next
statement which is read fucntion.  But If I change time in sleep
command than I am getting different values.
It means that inside the FPGA in evertying clock cycle the value the
signal which I am reading is changing all the time. Also in my VHDL
code I haven't got anything which makes the values to change as time
passes. And also according to the simulation I have a stable output as
well.
Could any body tell me how to do this properly to get stable output or
if some one has done this before then please give me some hint to sort
out this prob.

Cheers 


Isaac

Article: 60428
Subject: Re: FPGA Reconfiguration Question
From: vkode78@yahoo.com (xfpgas)
Date: 12 Sep 2003 10:09:18 -0700
Links: << >>  << T >>  << A >>
I wanted to give you more information..

I have an application that I can implement on a Virtex device by
Partial Run Time Reconfiguration (RTR). This is part of my work for my
thesis in graduate school.

I have a fixed  logic Block. And one reconfigurable Logic Block.
Fixed Logic Block is a processing engine (PE). The data for that will
be available in the Reconfigurable Logic (RL).  I can either use the
LUTs as distributed RAM or just use BlockRAM to store my data in the
RL Block. My PE will work on the data and when it is finished I will
read the output from the PE. And then, I will load the Reconfigurable
block with the new data to be worked on by the PE. So all I have to do
is change the contents of the LUT/BlockRAM using JBITS and partially
reconfigure the Device for the new data to be worked on by the PE. And
this is all the device does -- load the Data into the Reconfigurable
Logic Block and let the PE(Fixed Logic Block) do the math on it, and
this goes on. I am okay with the reconfiguration delay. Having said
that, I believe the Performance/cost (Savings in terms of Area) would
be improved this way rather than implementing everything in parallel
(if this requires lets say a million PEs to be implemented) across an
array of FPGAs. This ofcourse is not true if all I need is a few PEs.

My goal is to eventually make this a scalable appication with a Big
Virtex Device with multiple PEs all working on the Data which will be
reconfigured using RTR. And finally, develop a platform to have this
done over a huge array of FPGAs

Does anyone know of any work done on this? I would appreciate your
comments and suggestions.

1) Can a Virtex device handle this sort of Partial RTR ? Is there a
thumb rule regarding how often partial RTR can be done and if this can
be done for the life of the device? ( I apologize if this sounds
ignorant, I just want to make sure before I spend more time and
resources )

Thanks,
Kode

Article: 60429
Subject: Re: What clock domain is a Xilinx DCM LOCK signal in?
From: "Steven K. Knapp" <steve.knappNO#SPAM@xilinx.com>
Date: Fri, 12 Sep 2003 10:15:50 -0700
Links: << >>  << T >>  << A >>
Everything, except the RESET input, is controlled by the rising edge of
CLKIN.
---------------------------------
Steven K. Knapp
Applications Manager, Xilinx Inc.
Spartan-3/II/IIE FPGAs
http://www.xilinx.com/spartan3
---------------------------------
Spartan-3:  Make it Your ASIC

"John Providenza" <johnp3+nospam@probo.com> wrote in message
news:349ef8f4.0309111534.36aadea9@posting.google.com...
> I understand about the phase align capabilities provided by the DCM,
> but what clock domain are the LOCKED and STATUS bits created in?
>
> I want to feed LOCKED into a state machine, but I don't see in the
> Xilinx docs anyplace which clock produces it.
>
> John Providenza
>
>
> "Steven K. Knapp" <steve.knappNO#SPAM@xilinx.com> wrote in message
news:<bjobmb$oab1@cliff.xsj.xilinx.com>...
> > You can phase align feedback using either the CLK0 or CLK2X DCM outputs.
> >
> > There is a relatively new application note on DCMs in Spartan-3 that may
be
> > useful to your question.
> >
> > XAPP462:  Using Digital Clock Managers (DCMs) in Spartan-3 FPGAs
> > http://www.xilinx.com/bvdocs/appnotes/xapp462.pdf
> >
> > Phase alignment is optional for the Digital Frequency Synthesizer
function
> > in a DCM.
> > ---------------------------------
> > Steven K. Knapp
> > Applications Manager, Xilinx Inc.
> > Spartan-3/II/IIE FPGAs
> > http://www.xilinx.com/spartan3
> > ---------------------------------
> > Spartan-3:  Make it Your ASIC
> >
> >
> > "John Providenza" <johnp3+nospam@probo.com> wrote in message
> > news:349ef8f4.0309101349.2cbe675a@posting.google.com...
> > > I don't see in the Xilinx documentation in what clock domain
> > > the LOCK signal coming from a DCM is produced.  Do I need to
> > > synchronize it into the CLK0 domain to avoid metastability?
> > >
> > > Thanks!
> > >
> > >
> > > John Providenza



Article: 60430
Subject: Re: FPGA Reconfiguration Question
From: "Steven K. Knapp" <steve.knappNO#SPAM@xilinx.com>
Date: Fri, 12 Sep 2003 10:22:05 -0700
Links: << >>  << T >>  << A >>

"> Lets say I have an application that needs the following:
>
> Do a partial RTR ( Run Time Reconfiguration) of a Virtex Device
> continuosly through out its life time  at very frequent intervals. And
> I can live with the Reconfiguratin delay
>
> Can this be done? Do you see any issues with this?

This can and has been done.  Xilinx FPGAs use fully reprogrammable SRAM
configuration cells with no wear-out mechanism.

Partial reconfiguration is a bit trickier but not rocket science either.
Here are a few links that might prove useful.

Partial Reconfigurability Frequently Asked Questions
http://www.xilinx.com/ise/advanced/partial_reconf_faq.htm

Virtex Series Configuration Architecture User Guide
http://support.xilinx.com/xapp/xapp151.pdf

Two Flows for Partial Reconfiguration: Module Based or Small Bit
Manipulations
http://www.xilinx.com/xapp/xapp290.pdf

---------------------------------
Steven K. Knapp
Applications Manager, Xilinx Inc.
Spartan-3/II/IIE FPGAs
http://www.xilinx.com/spartan3
---------------------------------
Spartan-3:  Make it Your ASIC



Article: 60431
Subject: Re: FPGA Reconfiguration Question
From: "Steve Casselman" <sc_nospam@vcc.com>
Date: Fri, 12 Sep 2003 17:35:27 GMT
Links: << >>  << T >>  << A >>
> 1) Can a Virtex device handle this sort of Partial RTR ? Is there a
> thumb rule regarding how often partial RTR can be done and if this can
> be done for the life of the device? ( I apologize if this sounds
> ignorant, I just want to make sure before I spend more time and
> resources )
>
> Thanks,
> Kode

If you generate the ll file  you can see the bit locations of the rams and
lookup tables that you use. You can do Partial configurations all you want.
The FPGA will last as long as a RAM.

Steve



Article: 60432
Subject: Re: Crystal Input to FPGA
From: Brian Drummond <brian@shapes.demon.co.uk>
Date: Fri, 12 Sep 2003 19:17:23 +0100
Links: << >>  << T >>  << A >>
On Wed, 10 Sep 2003 22:06:21 -0400, rickman <spamgoeshere4@yahoo.com>
wrote:

>Glen Herrmannsfeldt wrote:

>> The oscillator that I used to know used three CMOS inverting gates in series
>> with the crystal wrapped around them.  Possibly some resistors, too.
>> Usually one more gate to buffer and shape the result.
>
>But what is the advantage over an oscillator unless you are trying to
>squeze every penny out of the design?  The difference between an
>oscillator and a crystal is less than $.50.  

Off the shelf oscillators for standard frequencies are one thing. 

But when I was looking for custom frequencies I found manufacturers were
happy to make small batch or even one-off crystals at a very respectable
price; at the time, they didn't seem to be tooled up to make one-off
oscillator modules - or at least they wanted much more money for the
job.

Maybe this has changed in the last few years.

- Brian


Article: 60433
Subject: Re: Time Killing Post P&R Simulation
From: Brian Drummond <brian@shapes.demon.co.uk>
Date: Fri, 12 Sep 2003 19:17:25 +0100
Links: << >>  << T >>  << A >>
On Thu, 11 Sep 2003 10:07:27 -0700, Mike Treseler
<mike.treseler@flukenetworks.com> wrote:

>Bob Perlman wrote:
>
>> I've been doing FPGA design for years, and can count the number of
>> times I've done post-route simulation on the fingers of one hand.
>
>I agree. If an FPGA design is 100% synchronous,
>sims functionally, and passes post-route static timing,
>post-synth/route simulation is rarely indicated.

I find it a useful crutch when you don't understand the way the timing
constraints work ... and the details of their syntax is not always
clear! but that need is reduced with more experience.

OTOH ... when the design is not 100% synchronous ... I have found errors
(** mostly mine! :-) crossing clock domains when I synchronised
handshake signals incorrectly. It's a useful tool in the armoury, to
pull out when things go wrong, but I agree it shouldn't be in the normal
development loop.

Related question: if you have one or two FF's in the entire design
dedicated to resolving metastability, you want to turn off their Tsu/Th
checks, since their whole point is to encounter setup/hold violations!

How do you do that for these individual FF's while leaving all the other
checks in place? (to catch any uncovered domain-crossing signal paths)
I resorted to inserting To_01() in the relevant signals in the
gate-level netlist by hand, which was untidy, but tolerable for the
(mercifully few) passes I needed, but there HAS to be a better way...


** but the FIFO solution from Xilinx app note ???(I forget which) also
"failed" post-route sim, coming out of reset. It only brings one reset
line out, which is used for both clock domains internally. I modified it
to bring out a reset in each clock domain, since I ran the incoming
reset through a synchroniser for the rest of my logic anyway.

Call me paranoid? In real life I doubt it matters, but in sim, once
"reset" put the counters into an indeterminate state, it never
recovered.

- Brian

Article: 60434
Subject: Re: Altera's Quartus II "smart compilation" feature killed my design?
From: Mike Treseler <mike.treseler@flukenetworks.com>
Date: Fri, 12 Sep 2003 11:42:37 -0700
Links: << >>  << T >>  << A >>
enq_semi wrote:

> So, let me redefine my questions:
> 1. Why with "smart compilation" turned on it still recompiles
> everything?

"Smart Compilation" just means save the cache files
in case they can be reused. It doesn't make the cache
any more likely to be reusable. That is a function
of device utilization, routing strategy and the
impact of the design change.

> 2. Why the compilation didn't work after I moved 8 wires?

-- Maybe "didn't work" means
"routed successfully, but did not function correctly"

When you gamble by making design changes on the back end,
sometimes you lose. Consider making all design changes
at the front end and rerunning your functional sim
and synthesis before place+route.

-- Maybe "didn't work" means "did not route successfully"

When device utilization is high, changing even one
pin can lose you the route.


     -- Mike Treseler


Article: 60435
Subject: Re: Time Killing Post P&R Simulation
From: Mike Treseler <mike.treseler@flukenetworks.com>
Date: Fri, 12 Sep 2003 12:12:05 -0700
Links: << >>  << T >>  << A >>


Brian Drummond wrote:

> Related question: if you have one or two FF's in the entire design
> dedicated to resolving metastability, you want to turn off their Tsu/Th
> checks, since their whole point is to encounter setup/hold violations!

related thread:

http://groups.google.com/groups?q=synchronizer+sim+ack+blind


> ** but the FIFO solution from Xilinx app note ???(I forget which) also
> "failed" post-route sim, coming out of reset. It only brings one reset
> line out, which is used for both clock domains internally. I modified it
> to bring out a reset in each clock domain, since I ran the incoming
> reset through a synchroniser for the rest of my logic anyway.
> Call me paranoid? In real life I doubt it matters, but in sim, once
> "reset" put the counters into an indeterminate state, it never
> recovered.

Reliability comes from getting the details right.
Writing your own code is one way to do it.

    -- Mike Treseler


Article: 60436
Subject: Re: Xilinx S3 I/O robustness question
From: Peter Alfke <peter@xilinx.com>
Date: Fri, 12 Sep 2003 12:12:59 -0700
Links: << >>  << T >>  << A >>
This is a long and complex e-mail. 
Let me just correct one fundamental popular misconception below:

lecroy wrote:
> 
> Austin,
> I do not agree with your statement &#8220;&#8230;, as the nmos is ON,
> or the pmos is ON, effectively clamping the IOB pin to either gnd or
> Vcco.&#8221; .   If we look at an example of an I/O pin (so not a
> dedicated output), when we transition from a low to high state on the
> output, the high side driver is sourcing current to the load.  As the
> signal propagates down our transmission line and reaches the end, some
> energy will reflect back.  Let&#8217;s use a very high impedance for
> our termination, so the reflected signal is in phase with the
> incident.  As the reflected signal reaches the output pin it will
> raise the voltage.  Because the driver is sourcing, it has no way to
> clamp this transient.  So, the catch diodes would clamp the reflected
> signal to a level just over the supply voltage.

This is a fairly common misconception.
A p-channel output transistor, when active, has a certain impedance, say
10 Ohm. It sources and also sinks current with that impedance . All MOS
transistors behave like resistors (at least over a certain voltage
range). They conduct current in BOTH directions. Therefore, the active
p-channel output transistor will snub the incoming reflection.
If you don't believe it, just try it out. It's a simple enough experiment.

Peter Alfke, Xilinx Applications

Article: 60437
Subject: Re: Xilinx S3 I/O robustness question
From: lecroy7200@chek.com (lecroy)
Date: 12 Sep 2003 14:20:57 -0700
Links: << >>  << T >>  << A >>
I just got the following e-mail.....  It has some data, but a better
article may have been:

http://support.xilinx.co.jp/xapp/xapp329.pdf

I am still looking for an answer to my question.





This is a long and complex e-mail. 
Let me just correct one fundamental popular misconception below:

lecroy wrote:
> 
> Austin,
> I do not agree with your statement &#8220;&#8230;, as the nmos is ON,
> or the pmos is ON, effectively clamping the IOB pin to either gnd or
> Vcco.&#8221; .   If we look at an example of an I/O pin (so not a
> dedicated output), when we transition from a low to high state on the
> output, the high side driver is sourcing current to the load.  As the
> signal propagates down our transmission line and reaches the end, some
> energy will reflect back.  Let&#8217;s use a very high impedance for
> our termination, so the reflected signal is in phase with the
> incident.  As the reflected signal reaches the output pin it will
> raise the voltage.  Because the driver is sourcing, it has no way to
> clamp this transient.  So, the catch diodes would clamp the reflected
> signal to a level just over the supply voltage.

This is a fairly common misconception.
A p-channel output transistor, when active, has a certain impedance,
say
10 Ohm. It sources and also sinks current with that impedance . All
MOS
transistors behave like resistors (at least over a certain voltage
range). They conduct current in BOTH directions. Therefore, the active
p-channel output transistor will snub the incoming reflection.
If you don't believe it, just try it out. It's a simple enough
experiment.

Peter Alfke, Xilinx Applications

Article: 60438
Subject: Re: frequency constraint changes routability
From: Andrew Paule <lsboogy@qwest.net>
Date: Fri, 12 Sep 2003 17:04:18 -0500
Links: << >>  << T >>  << A >>
sounds like new chip type is in order.

John McMiller wrote:

>Hi.
>I have a xc2v8000 design (70% utilization).
>
>With the same EDIF netlist the Xilinx routability changes dramatically
>with frequency:
>
>Clock constraint:  25 MHz -> routed design
>Clock constraint:  50 MHz -> 1200 un-routed wires 
>Clock constraint: 100 MHz -> 60000 un-routed wires
>
>Unfortunately 100 MHz is my target frequency...
>
>Is there a flag that tells the Xilinx P&R to prefer routing over
>timing at the first phase, and do speed optimization only afterwards?
>
>ThankX,
>John
>  
>


Article: 60439
Subject: Re: Altera's Quartus II "smart compilation" feature killed my design?
From: Ben Twijnstra <btwijnstra@SPAM.ME.NOT.chello.nl>
Date: Fri, 12 Sep 2003 23:22:33 GMT
Links: << >>  << T >>  << A >>
Hi Yi,

> 
> When I say "does NOT work at all", it means not only I cannot get
> anything from the DAC0 pins, but also I cannot bootload the FPGA (I
> have bootloader in the design) after I download the new design.
> 
> Somehow during the re-compilation, the bootloader (8051 processor,
> intruction ROM and RAM) are affected, which should have nothing to do
> with the 8 wires I changed at the top level.
> 
> Any help/suggestions are greatly appreciated.
> 
> Yi Zhang
> ENQ Semi.

Doesn't look good. What version of Quartus are you running? 2.2 or 3.0? Did
you later retry using a normal compile, and did that work?


Best regards,



Ben

Article: 60440
Subject: Re: Xilinx S3 I/O robustness question
From: Peter Alfke <peter@xilinx.com>
Date: Fri, 12 Sep 2003 16:28:26 -0700
Links: << >>  << T >>  << A >>
Let me help you, and rephrase your original question:
If a 3.3 V output on Spartan3, going active Low to active High, drives a
transmission line of arbitrary length that is open ended at the far end,
there will be a return signal that wants to pull the 3S pin higher than
Vcco = 3.3 V.
Can this cause do damage to the Spartan3 pin?

My answer would be: NO.
The returning 3.3V wave wants to pull the pin to 6.6 V, but the
transmission line impedanec is roughly 50 Ohm, and the chip pull-up
impedance is roughly 10 Ohm, so you have a voltage divider that raises
the output pin voltage by only 1/6 of the 3.3 V swing = 550 mV. The
resulting theoretical 3.85 voltage is really a bit lower since the
reflection is not perfect, and there are losses on the line.
Also, this spike will only last a few nanoseconds.
I would say that this poses no problem. But I have copied Steve Knapp,
who handles Spartan applications. He may add his opinion to this.

Peter Alfke, Xilinx
=============================
lecroy wrote:
> I am still looking for an answer to my question.
> 
> 

Article: 60441
Subject: Re: Crystal Input to FPGA
From: hmurray@suespammers.org (Hal Murray)
Date: Sat, 13 Sep 2003 00:36:21 -0000
Links: << >>  << T >>  << A >>
>But when I was looking for custom frequencies I found manufacturers were
>happy to make small batch or even one-off crystals at a very respectable
>price; at the time, they didn't seem to be tooled up to make one-off
>oscillator modules - or at least they wanted much more money for the
>job.

Fox has custom frequency oscillators availably at reasonably cost and
reasonably quickly.
  http://www.foxonline.com/jitomain.htm

I expect there are others.

-- 
The suespammers.org mail server is located in California.  So are all my
other mailboxes.  Please do not send unsolicited bulk e-mail or unsolicited
commercial e-mail to my suespammers.org address or any of my other addresses.
These are my opinions, not necessarily my employer's.  I hate spam.


Article: 60442
Subject: Z-busses and synthesis
From: H. Peter Anvin <hpa@zytor.com>
Date: 12 Sep 2003 17:39:08 -0700
Links: << >>  << T >>  << A >>
Hello all,

I'm curious if anyone happens to know how the Xilinx and Altera tools,
in particular, handle Z-values for internal signals.  If one has a
collection of modules which use bidirectional tristate busses, can one
combine them in the obvious way and have the synthesis program create
whatever logic is needed to simulate the wired-MUXness of the tristate
bus, or do one have to explicitly recode everything to use gates or
muxes?

Thanks,

	-hpa
-- 
<hpa@transmeta.com> at work, <hpa@zytor.com> in private!
If you send me mail in HTML format I will assume it's spam.
"Unix gives you enough rope to shoot yourself in the foot."
Architectures needed: ia64 m68k mips64 ppc ppc64 s390 s390x sh v850 x86-64

Article: 60443
Subject: Re: Crystal Input to FPGA
From: "Daniel Lang" <dblx@xtyrvos.caltech.edu>
Date: Fri, 12 Sep 2003 17:43:42 -0700
Links: << >>  << T >>  << A >>
"Brian Drummond" <brian@shapes.demon.co.uk> wrote in message > Off the shelf
oscillators for standard frequencies are one thing.
>
> But when I was looking for custom frequencies I found manufacturers were
> happy to make small batch or even one-off crystals at a very respectable
> price; at the time, they didn't seem to be tooled up to make one-off
> oscillator modules - or at least they wanted much more money for the
> job.
>
> Maybe this has changed in the last few years

Digi-Key carries several brands of off the shelf oscillators that they
can program to your custom frequencies (qty = 1).

Daniel Lang




Article: 60444
Subject: Re: Webpack Vs. ISE
From: Marc Guardiani <marc@guardiani.com>
Date: Sat, 13 Sep 2003 02:08:49 GMT
Links: << >>  << T >>  << A >>
Are you going to be using ISE or Foundation? They are two completely 
different software packages. ISE is very similar to the Webpack (another 
reply you received describes the differences). Foundation is no longer 
supported by Xilinx and is based on third party software. Also 
Foundation will not do the newer FPGAs and ISE will not do the older FPGAs.

Dave wrote:
> I am just about to go through a 115 page introduction tutorial on the XCESS
> website for using the Xilinx Webpack 4.x edition. However I will be using
> the ISE Foundation 4.x edition and want to know if I am wasting my time
> reading the entire Webpack tutorial to learn how to use the ISE Foundation
> edition. I am assuming its all the same, with Webpack just having less
> features. Anyone who is familiar with both editions that can let me know to
> go ahead with this or STOP - and find a tutorial at Xilinx instead (I need
> to install the software for their tutes I think) would be much appreciated.
> Initial stages will be purely schematic entry. VHDL will come later.
> 
> Regards
> Dave
> 
> 


Article: 60445
Subject: Re: What are Pull ups?
From: Marc Guardiani <marc@guardiani.com>
Date: Sat, 13 Sep 2003 02:22:36 GMT
Links: << >>  << T >>  << A >>


rider wrote:

> Hi!
> 
> I am using SPARTAN 2 XC2S150 for my design. I have a question
> regarding pull up resistors. I am using ISE5.1.
> 
> 1)What is meant by optional pull ups? There are options in the
> Constraints Editor to insert pull ups at the I/Os. Are these PERMANENT
> pull ups or just during configuration? If I select these pull ups,
> then i also need to set M2M1M0=100 ?

Well, they're only permanent from the standpoint that they are there 
after the device is configured.

You do not need M[2..0] set to 100 to get these pullups. They are in the 
device configuration. If you set M[2..0] to be 100 you will also get 
these pullups at power up and during configuration. If you set M[2..0] 
to 000, then the pins will be three-state (hi-z) at power up and during 
configuration.

> 
> 2)Alternatively if i DO NOT select those pull ups in the Constraints
> editor, but i still set M2M1M0=100 then what will happen? Pull ups
> will be used for configuration only?

See previous answer.

> 
> 3) Do i need to connect all my VCCO pins  to 3.3V and VCCINT to 2.5V?
> All GND pins on the pacakge be grounded?

Yes, yes, and yes.

> 
> 4)If I use one clock signal in my design, then it can be input on only
> one IGCKO(input global clock buffer) or i need to connect all IGCK's
> to this clk signal?

You should input this on a single global clock. If you input this on 
multiple clocks, even if you use a DLL, you may introduce additional 
skew between the clocks.

> 
> Regards
> Rider


Article: 60446
Subject: Re: Webpack Vs. ISE
From: "Matt" <bielstein2002@comcast.net>
Date: Sat, 13 Sep 2003 04:48:54 GMT
Links: << >>  << T >>  << A >>
Marc,

Xilinx has four versions of their ISE software. They are:

1) Webpack
2) BaseX
3) Foundation
4) Alliance

1 and 2 are subsets of Foundation which has the XST synthesis tool. The
differentiator is that #3 has the full toolset with support for all Xilinx
devices. Numbers 1 and 2 have XST but only support the low to mid range
devices. Alliance is the third party flow which does not include XST.
It should be noted that XST does not support devices based on the 4000
architecture. i.e. 4000 family, Spartan/Spartan XL. All other families are
supported. If you need support for the 4000 stuff you need to go third
party.

Hope this helps...


Matt

"Marc Guardiani" <marc@guardiani.com> wrote in message
news:R_u8b.758$U41.369@nwrdny01.gnilink.net...
> Are you going to be using ISE or Foundation? They are two completely
> different software packages. ISE is very similar to the Webpack (another
> reply you received describes the differences). Foundation is no longer
> supported by Xilinx and is based on third party software. Also
> Foundation will not do the newer FPGAs and ISE will not do the older
FPGAs.
>
> Dave wrote:
> > I am just about to go through a 115 page introduction tutorial on the
XCESS
> > website for using the Xilinx Webpack 4.x edition. However I will be
using
> > the ISE Foundation 4.x edition and want to know if I am wasting my time
> > reading the entire Webpack tutorial to learn how to use the ISE
Foundation
> > edition. I am assuming its all the same, with Webpack just having less
> > features. Anyone who is familiar with both editions that can let me know
to
> > go ahead with this or STOP - and find a tutorial at Xilinx instead (I
need
> > to install the software for their tutes I think) would be much
appreciated.
> > Initial stages will be purely schematic entry. VHDL will come later.
> >
> > Regards
> > Dave
> >
> >
>



Article: 60447
Subject: need help with Xilinx ISE 4.2i software
From: Jon Elson <elson@pico-systems.com>
Date: Sat, 13 Sep 2003 01:30:21 -0500
Links: << >>  << T >>  << A >>
Hello, all, I hope someone can help,

I used to have my Xilinx Foundation/ISE up to date, but
I let the support lapse, as all the new work seemed to be aimed at
devices I was not going to use in the forseeable future.

I had Foundation running on an older Win 95 system, and
just stored the upgrade boxes.  I got A win 2000 system set up,
installed ISE 4.2i, got my licenses for ISE and Foundation from
Xilinx, and everything seemed to be working.  Now, I'm trying
to seriously learn VHDL, and so I need to get FPGA Express
working.  This used a different license scheme, as it was licensed
from Synopsys.  I can't figure out how to get a license file from
Xilinx, or convert my old license, or whatever it takes.  I have
an old license from the Win 95 Foundation, but of course the
disk serial numbers are different.

Does anyone have any suggestions on how to make this work?
I really can't expect Xilinx to help, as I dropped my support
contract.

Thanks very much in advance,

Jon


Article: 60448
Subject: Re: Z-busses and synthesis
From: Jon Elson <elson@pico-systems.com>
Date: Sat, 13 Sep 2003 01:34:17 -0500
Links: << >>  << T >>  << A >>


H. Peter Anvin wrote:

>Hello all,
>
>I'm curious if anyone happens to know how the Xilinx and Altera tools,
>in particular, handle Z-values for internal signals.  If one has a
>collection of modules which use bidirectional tristate busses, can one
>combine them in the obvious way and have the synthesis program create
>whatever logic is needed to simulate the wired-MUXness of the tristate
>bus, or do one have to explicitly recode everything to use gates or
>muxes?
>  
>
Using schematic entry to Xilinx Foundation and ISE, I have done this
both in CPLDs (XC9500 series) and in Spartan FPGAs.  The FPGAs can
do it directly in hardware, I think the CPLDs simulate the logic function
with gates that assume a logic 1 on the bus if no BUFT is driving it.
That's not a condition you'd really want to allow, anyway, for some poor
soul reading the docs later.

Jon


Article: 60449
Subject: Re: Altera's Quartus II "smart compilation" feature killed my design?
From: H. Peter Anvin <hpa@zytor.com>
Date: 13 Sep 2003 00:22:17 -0700
Links: << >>  << T >>  << A >>
Followup to:  <cd4a30b8.0309120454.734ddc0a@posting.google.com>
By author:    enq_semi@yahoo.com (enq_semi)
In newsgroup: comp.arch.fpga
>
> > 
> > Try removing the db directory and recompiling.
> > 
> > 	-hpa
> 
> I think the title I used was not accurate: it should be "smart
> compilation did not SAVE my design".
> 
> The fact it runs for more than one hour can only mean that Quartus did
> recompile everything (even the design has no change except 8 wires and
> I didn't remove the db directory).
> 
> So, let me redefine my questions:
> 1. Why with "smart compilation" turned on it still recompiles
> everything?
> 2. Why the compilation didn't work after I moved 8 wires?
> 

I have found that changing a file while a compile is in progress (at
least across a network; haven't tried it on the same machine) messes
up the dependency generation in smart compile.

The other thing is that if *any* logic changes it has to re-run the
fitter, which at least for my designs is 60% of the compile time.

However, if the only thing that has changed is .mif files, smart
compile can take the time down from 15 minutes to 15 seconds and
such, since all it needs to re-run is the assembler.

	-hpa
-- 
<hpa@transmeta.com> at work, <hpa@zytor.com> in private!
If you send me mail in HTML format I will assume it's spam.
"Unix gives you enough rope to shoot yourself in the foot."
Architectures needed: ia64 m68k mips64 ppc ppc64 s390 s390x sh v850 x86-64



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