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Hi Marc, Xilinx do welcome user inputs on improving the tools. You're more than welcomed to let me know or open hotline cases for change requests on Xilinx software tools. We all benefits from specific constructive suggestions! Best Regards, Wei Xilinx Applications Marc Randolph wrote: > Peter Alfke <peter@xilinx.com> wrote in message news:<3F6F1A16.EC328D4F@xilinx.com>... > >>Lorenzo Lutti wrote: >> >>> >>>Yes! But be afraid of iMPACT user interface, which is the worst >>>nightmare ever invented. I've lost more than ten minutes to understand >>>how to use a PROM with iMPACT... >> >>Lorenzo, you must be pretty smart if you can solve the "worst nightmare >>ever invented" in a mere ten minutes... :-) >>Peter Alfke > > > Howdy Peter, > > I interpreted his comment to mean that he wasted ten minutes on > just one aspect of the many that form the nightmare that is iMPACT. > And I have to agree with him. The tool sure works like it was > designed by someone that doesn't actually have to use it more than > once or twice. The rest of the Project Navigator (at least on 5.x), > while noticably better than iMPACT, is also very disappointing coming > from a company that produces such high caliber hardware. > > Have fun, > > MarcArticle: 60901
Perhaps I just missed what I am looking for, but I cannot seem to find any indication of the speed of most elements withing the Spartan3. For example, what is the time response of an adder, What is the time response of a multiplier? (I did get that earlier thanks to Steve Knapp.) I know that these are highly dependent on loading, etc. but can't Xilinx at least give me an approximate answer. For example, why waste my time further if the response with a minimum load is already slower than I can tolerate. On the other hand, why waste time in checking these designs to the nth degree if the response speed is twice as fast as I need. Thanks, Theron HicksArticle: 60902
> Still, many ideas from that time are still in use today. That is true. And sometimes people discover new uses for old techniques. It never hurts to learn them, because they can give you ideas on how to solve your current problems. Thanks for the information Glen. I found a lot of links to Earle Latches but no diagrams. I guess the design is too old for the internet. --vArticle: 60903
Just FYI, the free WebPack 6.1i is now available and supports the Spartan-3 XC3S50, XC3S200, and the XC3S400. Also, the XC3S50 supported in WebPack 6.1i has four 18K block RAMs, four 18x18=36 hardware multipliers, and two Digital Clock Managers (DCMs) Xilinx WebPack 6.1i http://www.xilinx.com/xlnx/xil_prodcat_landingpage.jsp?title=ISE+WebPack Devices Supported in WebPack 6.1i http://www.xilinx.com/ise/products/webpack_config.htm --------------------------------- Steven K. Knapp Applications Manager, Xilinx Inc. General Products Division Spartan-3/II/IIE FPGAs http://www.xilinx.com/spartan3 --------------------------------- Spartan-3: Make it Your ASICArticle: 60904
Petter Gustad wrote: >Steve Lass <lass@xilinx.com> writes: > > > >>Linux also uses less memory. The average is about 6% less and a few >>really big designs that run out of memory on Windows XP run fine >>under Linux. >> >> > >Hopefully there will be a 64-bit Opteron version... > Yes, that's the plan. Of course running on a 64 bit operating system takes about 1.5X more memory. Steve > >Petter > >Article: 60905
Peter Alfke wrote: >rider wrote: > > > >>2)I have a 20MHz clock in my design that is used in some flip flops in >>the design. Most of the circuit is combinational and with about 18 >>combinational clocks. >> >> >That is a scary statement. >Are you really using 18 clocks driven by combinatorial logic? >You must be either very inexperienced, very brave, or very smart. Or >perhaps all three. >Normal humans stay away from such design methodologies, and use >synchronous logic with a minimum of global clocks (preferrably only one). >That's better for your health, your sleep, and your sanity... >Peter Alfke > > Well, he's certainly using the right (read ONLY) architecture that will do it. I got started with Xilinx on a project where I needed 72 flip-flops on a board, all essentially asynchronous from any other. (This was a timing and logic controller for nuclear detector applications). Xilinx was the ONLY architecture that could handle lots of acynchronous clocks at the time. It may still be. There certainly can be complications with things like this. We needed to have totally asynchronous timing, with resolution below 1 nS, so no global clock could do it. We used the AD9201 timing chip to handle the time delays, but that chip lacks a FF to make it into a one-shot function, which was what we needed. JonArticle: 60906
James Williams wrote: >Is there one with the IEEE 1284 Core VHDL that is in english? > > I poked around a while and found the VHD file, which seems readable. I haven't tried to UNDERSTAND it yet, however - that is different. http://www.nahitech.com/nahitafu/fpgavhdl/ieee1284_2/ieee1284main-ver01.vhd <http://www.nahitech.com/nahitafu/fpgavhdl/ieee1284_2/ieee1284main-ver01.vhd%27> JonArticle: 60907
Hi Antti
Thanks for the response.
haha. I don't expect anyone to do work for me, othwersie I won't learn
anything, but I wouldn't mind some guidance along the way from you guys..
Anyway I need to ask 2 questions regarding your reply.
1. When you say USB11T11A, do you mean the Philips tranceiver PDIUSBP11A? If
no then I'm sorry but i'm not able to find anything on USB11T11A. Have I
gone blind?
2. Regarding the usb (japanese design), I have ended up towards a brick
wall. What I mean to say is, I have been looking at the design for couple of
hours and there are 4 components that I'm not sure what they do. The main
problem is that the code was written for a Xilinx component and because I'm
using Altera component, I'm do not have the librabires that these component
are using.
Firstly the library defined is (which is for Xilinx only (pls correct me if
i'm wrong))
library unisim;
use unisim.vcomponents.all;
and the 4 components that are using this library are
u_DLL : CLKDLL
port map ( CLKIN => CLKINM,
CLKFB => GCLK,
RST => RST,
CLK0 => GCLKM,
CLK2X => CLKM,
LOCKED => LOCK
);
u_GCLK : BUFG
port map ( I => GCLKM,
O => GCLK
);
u_CLK : BUFG
port map ( I => CLKM,
O => CLK
);
u_CLKIN : IBUFG
port map ( I => CLKIN,
O => CLKINM
);
If you can explain me how I can replace these components for Altera design,
I will have a step to progress. If I can get past this point, then I have
something to try on the chip and play around. My problem is that right now I
can't go past compiling as Quartus doesn't recognize these components (or
the library). Pls Advice
Thanks again
Regards
"Antti Lukats" <antti@case2000.com> wrote in message
news:80a3aea5.0309240119.7925b682@posting.google.com...
> "SneakerNet" <nospam@nospam.org> wrote in message news:<p43cb.157047
> > Has anyone successfully implemented USB 2.0 or USB 1.1 protocol in
> [deleted]
>
> USB11T11A FS/LS USB tranceiver
>
> usb_phy (opencores) UTMI interface that connects to USB11T11A
>
> usb1.1 (opencores) connects to usb_phy (opencores) connects to
> USB11T1A it is not HID but it will enumerate in hardware iw the USB
> host will 'see' it, but ther is no host software provide
>
> usb (japanase desing) full HID USB core includes USB11T1A model) can
> directly be connected to usb D+ D- pins! (no tranceiver chip), there
> is some VB test program to talk to the core (as it is HID peripheral)
>
> antti
> PS I am afraid you have todo some homework :) cant do it for you
Article: 60908
Hi Neil,
Congratulations on the funniest post I've seen on CAF for ages!!
Your parody of the precious "Hacker, Unix Guru" getting upset because
someone dared offer advice on how to google was priceless! Thanks for
brightening my day, and keep up the good work!
Meant in good humour, Syms.
Article: 60909antti@case2000.com (Antti Lukats) writes: > FYI > > MPGA Meta Gate array > > pure Xilinx SRL16 oriented design, > > 1 MPGA cell = 1 Virtex slice Web page of openchip.org is still empty, so I can only speculate what you are doing. Hmm, only 2 LUTs per cell can only be roughly such an design: N-E-W-S inputs (no far ones) into one 4LUT, function there, out direct and out via FF both to an 2nd 4LUT (what with its other 2 inputs?) and output of that identical in all 4 directions (no space for Nout Eout Sout Wout muxes, hmm, how do signals cross each other?). That would be an minimal SoG-FPGA in LUT+PIP FPGA implementation. SoG = Sea of Gates, FPGA with no specific LUT logic vs PIP routing split, like Algotronix CAL1024 or Xilinx XC6200 or Atmel AT6000. LUT+PIP = the oposite, few luts (10% of chip) and 90% PIP based routing in between, like XC2000, XC3000, XC3100, XV4000, XC5200, Virtex, ... > bitstream is prepared as ASCII chart that can be directly downloaded! > yes you have ASCII chart you edit it and download to FPGA Split up into the LUTs, with all the rest of the host-FPGA unchanged? > KRPAN (OC embedded FPGA) > > this is very similar to Algotronix CAL1024 with little bit enhanced > 1 KRPAN cell is approx 26 Virtex slices That is what most FPGA-in-FPGA designs seem to be like. Emulate CAL1024 or Cal2/XC6200 style designs. In particular an XC6200 bit compatible design will waste a lot of space (them 3 8-Muxes (each 4 LUTs, 2 F5, 1 F6) per cell are expensive, add then 4 4-Muxes for output (each 2 LUTs with F5), add then a few LUTs for the function unit, and then somehow enough FFs for them 24 config bits per cell). So 26 slices is large but believeable. An XC6200 feature-alike (translate XC6200 bitstream to lut values and write them per SLR16) would be smaller (only 2 LUTs per 8-Mux, as selection bits come from the LUTs content) and allow additional features (8-Mux -> 2 LUTs and F5-OR, so offer 16+16 functions instead of just 8 Mux states). Making an optimize for implement-in-Virtex SoG would be massively more space saving, but not compatible (or even translatable) with the XC6200 toolschains. But one can make ones own tools, possibly derived from the many outside-Xilinx ones that are available from universities. Problem is that I dislike SoG style FPGAs. Their "no routing" architecture, which is sold as advantage by the proponents (it is more "elegant", because less details), ends up in real designs being "emulate routing using logic or out muxes", which uses more chip space (wasted cells just for routing) and is slower (even in full-custom chips it is 1 NAND-NAND Mux per cell, instead of one PIP transistors gate per CLB. And the 24bit/cell of an XC6200 compared with the 864bit/CLB of Virtex gives us 36cells at cost of one CLB (assuming SRAM costs dominate). So 9cells at cost of LUT. But an 6x6 grid of cells gives max 6 lines of data traversing it and costs 6 NAND-NAND hops, and so is way inferior to an CLB with 24 lines traversing it and one single PIP stage of delay. Also SoG loses the "1 bit per LUT row" data path design, making hardwired efficient carry chains impossible. So the result is massively slower arithmetic (3 Muxes for bit generating cell (each NAND-NAND) + 2 transfer Muxes per bit, as opposed to the 1 NAND-NAND 2bit lookahead per 2bits, if I reconstruct the Virtex chips layout properly). So that is (3+2*1)*2=10 vs (1/2)*2=1 in propagation delay. > I wonder if your comment is still no comment? > guess it is. > me smiling here :) Perhaps he knows that SoG has no future. XC6200 did not die because someone at Xilinx disliked its name. It was an commercial faillure. IMHO because it is/was an SoG. An design which ist technologically inferior. And can not be made better. Only academia liked it, because its one advantage (bitstream documented), inherited from CAL1032, outweighted performance for their types of jobs (research and test students). But anyone who wants performance, needs an LUT+PIP design, with its space/speed optimal routing by PIPs and 1-LUT-per-bit data paths with fast dedicated carry. At least DSP and soft-CPU people need this, badly. That is IMHO why all the large vendors (X, A, Lucent/Lattice) are all LUT+PIP based. And that is why people like me and Casselmann keep on hammering on Xilinx to open up Virtex or V2 documentation. Only alternative is to either reverse engineer Xilinx, make own FPGAs with documanted bitstream, at least on base of an ASIC to get speed (no FPGA-in-FPGA double speed/density loss). Both cost a lot of time. Of course any successfull OpenFPGA (outside of academia) is therefore going to also have an LUT+PIP structure. All projects I have seen so far do not have it, because they are SoG. -- Neil Franklin, neil@franklin.ch.remove http://neil.franklin.ch/ Hacker, Unix Guru, El Eng HTL/BSc, Programmer, Archer, Blacksmith - hardware runs the world, software controls the hardware code generates the software, have you coded today?Article: 60910
Petter Gustad wrote: > Hopefully there will be a 64-bit Opteron version... Steve Lass <lass@xilinx.com> writes: > Yes, that's the plan. That's great to hear! > Of course running on a 64 bit operating system > takes about 1.5X more memory. Sure! But it can take advantage of a lot more memory too. Memory is inexpensive, so if configuring a machine with 8G or 16G of RAM speeds things up or succeeds in PAR for large designs that fail on 32 bit systems, that's a small price to pay.Article: 60911
"Vinh Pham" <a@a.a> wrote in message
news:r7ncb.1311$5z.1162@twister.socal.rr.com...
> > Still, many ideas from that time are still in use today.
>
> That is true. And sometimes people discover new uses for old techniques.
> It never hurts to learn them, because they can give you ideas on how to
> solve your current problems. Thanks for the information Glen. I found a
> lot of links to Earle Latches but no diagrams. I guess the design is too
> old for the internet.
I wonder if I can get this to work:
Fixed width font required:
clock -------
| nand )------------\
data -------- \
| \
|----
| nand )---------------| nand ) -------------- out
out ----
| /
---- /
| nand )------------/
clockbar ----
Clock and its inverse, clockbar, apparently don't have so strict timing
requirements as one might guess.
To implement AND/OR logic, the number of inputs on the final nand can
be increased, and additional copies of the left middle nand can be
added, also with more inputs.
-- glen
Article: 60912Peter Alfke <peter@xilinx.com> wrote in message news:<3F6F9240.E1B74AB5@xilinx.com>... > Here are some practical points. > For all but the most extremely fast applications ( say up to 200 MHz), > synchronous counters are built using a global clock, and the bult-in > free ripple carry structure, which of course determines a max frequency > (where the ripple carry can still meet the set-up time requirements of > the MSB.) Decoding TC can be quite tricky, that's why I suggested the > digital differentiator which actually detects TC+1. It is interesting to see this discussion come up, I had never thought about doing a cout/TC (delayed) in this way! To implement the "digital differentiator", the best I could come up with was a falling edge detector on MSB using an AND gate, an inverter and a flip-flop. D gets the MSB and Q is ANDed with NOT(MSB). Depending on use, I guess the AND output could be synchronized (delay of 2 clocks then) if needed. Keeping this clever TC method in mind, I'm trying to build a programmable frequency divider which uses a 20-bit loadable synchronous counter. The divisor is held in a register and is arbitrary, so no clever apriori optimizations. Currently I'm targetting a Flex6K but I'm also eyeing a Xilinx Spartan XL part. I found if I have a counter setup to count down and decode on count == 1 which drives a DFF and is used to SLOAD the counter, I need a large number of LUTs to implement the decode/compare logic(not surprising). To use the TC method above(counting-up), I need to load my counter with the 1's complement of my divisor. Is the only alternative to count-down (and lots of LUTs) or count-up/TC (1's comp. of divisor) for my frequency generator to use a phase accumulator arrangement? Did I miss any other clever tricks? Thanks in advance. -- JayArticle: 60913
Jon, I was making a general statement in favor of synchronous design. Smart people using smart hardware can violate all these "rules"... I am glad Xilinx ( the ONLY one) worked out for you. :-) Peter Alfke ============================= Jon Elson wrote: > > P > > > > > Well, he's certainly using the right (read ONLY) architecture that will > do it. > I got started with Xilinx on a project where I needed 72 flip-flops on a > board, all essentially asynchronous from any other. (This was a timing and > logic controller for nuclear detector applications). Xilinx was the ONLY > architecture that could handle lots of acynchronous clocks at the time. It > may still be. There certainly can be complications with things like this. > > We needed to have totally asynchronous timing, with resolution below 1 > nS, so no global clock could do it. We used the AD9201 timing chip to > handle > the time delays, but that chip lacks a FF to make it into a one-shot > function, > which was what we needed. > > JonArticle: 60914
On Wed, 24 Sep 2003 14:05:29 -0600, Chen Wei Tseng <chenwei.tseng@xilinx.com> wrote: >Hi Marc, > >Xilinx do welcome user inputs on improving the tools. You're more than >welcomed to let me know or open hotline cases for change requests on >Xilinx software tools. We all benefits from specific constructive >suggestions! > >Best Regards, Wei >Xilinx Applications Ok, here are my suggestions for today. 1. Allow multiple installations of (different versions of) Xilinx software on the same machine. Drop the use of the XILINX environment variable - it's a PITA. 2. Add a "save project as script" command to the project manager. This allows a user to use the GUI to set up their project options, then save a shell script or batch file and then never use the GUI again. Regards, AllanArticle: 60915
Allan Herriman <allan.herriman.hates.spam@ctam.com.au.invalid> writes: > 1. Allow multiple installations of (different versions of) Xilinx > software on the same machine. Drop the use of the XILINX environment > variable - it's a PITA. Conflicting requirements. The XILINX environment variable is what ALLOWS multiple installations. That's how the pieces of an installation find the other related pieces, rather than some other version.Article: 60916
SneakerNet wrote: > > Hi Antti > Thanks for the response. > haha. I don't expect anyone to do work for me, othwersie I won't learn > anything, but I wouldn't mind some guidance along the way from you guys.. > Anyway I need to ask 2 questions regarding your reply. > 1. When you say USB11T11A, do you mean the Philips tranceiver PDIUSBP11A? If > no then I'm sorry but i'm not able to find anything on USB11T11A. Have I > gone blind? > 2. Regarding the usb (japanese design), I have ended up towards a brick > wall. What I mean to say is, I have been looking at the design for couple of > hours and there are 4 components that I'm not sure what they do. The main > problem is that the code was written for a Xilinx component and because I'm > using Altera component, I'm do not have the librabires that these component > are using. > Firstly the library defined is (which is for Xilinx only (pls correct me if > i'm wrong)) > library unisim; > use unisim.vcomponents.all; > > and the 4 components that are using this library are > u_DLL : CLKDLL > port map ( CLKIN => CLKINM, > CLKFB => GCLK, > RST => RST, > CLK0 => GCLKM, > CLK2X => CLKM, > LOCKED => LOCK > ); > > u_GCLK : BUFG > port map ( I => GCLKM, > O => GCLK > ); > > u_CLK : BUFG > port map ( I => CLKM, > O => CLK > ); > > u_CLKIN : IBUFG > port map ( I => CLKIN, > O => CLKINM > ); > > If you can explain me how I can replace these components for Altera design, > I will have a step to progress. If I can get past this point, then I have > something to try on the chip and play around. My problem is that right now I > can't go past compiling as Quartus doesn't recognize these components (or > the library). Pls Advice This is something I know a bit more about. These are all clock components. CLKDLL is a DLL (Delay Locked Loop) like a PLL only more Xilinx like ;) The Altera parts have PLLs depending on the part. I don't know if this is required or just used to allow different external and internal clock rates. The BUFG and IBUFG are just clock buffers. They are used to drive the internal clock distribution networks. Altera should have equivalent components or you may not need to instantiate them since they are typically locked to a given pin and should be inferred by most tools. Read up a bit on the Xilinx and Altera chips and this will all be very clear. -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAXArticle: 60917
Hi: I can download my design with parallel port in my notebook. But I still can't download in the desktop hosts. At first, I thought it might be my desktop computer's problem. But when I move to another desktop one, this still occurs. Still don't know why. Anyway, thanks Christopher Saunter's timely help. Best RegardsArticle: 60918
On Thu, 25 Sep 2003 10:35:48 +1000, Allan Herriman <allan.herriman.hates.spam@ctam.com.au.invalid> wrote: >On Wed, 24 Sep 2003 14:05:29 -0600, Chen Wei Tseng ><chenwei.tseng@xilinx.com> wrote: > >>Hi Marc, >> >>Xilinx do welcome user inputs on improving the tools. You're more than >>welcomed to let me know or open hotline cases for change requests on >>Xilinx software tools. We all benefits from specific constructive >>suggestions! >> >>Best Regards, Wei >>Xilinx Applications > >Ok, here are my suggestions for today. > >1. Allow multiple installations of (different versions of) Xilinx >software on the same machine. Drop the use of the XILINX environment >variable - it's a PITA. > >2. Add a "save project as script" command to the project manager. >This allows a user to use the GUI to set up their project options, >then save a shell script or batch file and then never use the GUI >again. 3. Add options to XST to allow defines, parameters and generics to be set from the command line as well as from a project file. Regards, Allan.Article: 60919
Symon wrote: > > Hi Rick, > OK, I suppose 'MUST' isn't strictly accurate, you might not care > whether the design works or not! How about 'SHOULD' instead? ;-) Those > signals bouncing back and forth may not affect the circuits functional > operation, but what are you gonna do when it happens on a 5 inch, 32 > bit data bus and you can't pass the CE/FCC mark tests? Sell it in > Elbonia, I guess! Is there a good market there? If a 5 inch 32 bit data bus without termination precludes passing CE/FCC RFI tests, then no PC would ever be sold. Few RFI issues are solved purely at the PC board level. In US commercial markets, the requirements are very different than consumer markets as well. > As for ground bounce, if those diodes are dumping energy, be sure > you've decoupled the Rx IC as well as the Tx one! Generally, it's > better not to have to rely on the diodes, don't you think? You end up > trading decoupling capacitors for termination resistors. That is assuming that the diodes would be triggered. I seem to recall that the basic analysis done here showed that this was unlikely. > I'm not saying simulate every trace. Simulate one, and layout the > rest accordingly, as I think Austin says in a parallel post. Check the > PCB layout very carefully, watching out for traces that don't comply > with your SI design. I like Austin's idea of adopting a standard > (HSTL, SSTL, PCI), makes it easy. That is the part I am not clear about. These traces are all individual circuits. If you have the luxury of a lot of open board space to route straight lines here and there, then sure, you can make each one very similar. On a small, tight board it will be very difficult to make them that similar. If the signal is critical enough to require a simulation, then I expect I would need to simulate each of them. I am surprized that the Spartan 3 chips are so sensitive to over and undershoot that this has become a major issue. I have seen lots of high speed boards and none had FPGAs or any other chips that needed this degree of analysis to prevent damage. -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAXArticle: 60920
Austin Lesea wrote: > > Rick, > > Fight it as long as you can, but everyone else is using the more advanced > tools, and simulating everything (at the companies where they want to be > successful on the first pcb turn -- as for the others, I don't hear from > them often anymore....). Funny. But I doubt it is very accurate. I have worked at some of the larger companies making telecom test equipment and I have yet to meet a board designer who simulates all of the traces. The ones I spoke with only simulate the clock lines or other signal lines when the timing is tight with no time for settling. Like I said, this is the first time I have heard a chip maker claim that typical ringing and undershoot can cause chip damage. Of course an absurdly designed trace and create excessive swings. But the typical amount of ringing is normally listed in data sheets as being within spec for chips. > And yes, if you do not pay attention now, you will cause ground bounce (50 - > 60 mA of reflection current per IO is possible), Under what conditions is this "possible"? I would expect this to be an extreme case. The analyis listed here indicated much lower currents (~35 mA) and only for the brief time (< 1 ns) of the overshoot. If the device can't handle these low currents without ground bounce, how can it possibly provide the much larger currents (> 55 mA) for the initial level change without ground bounce? > and with the Virtex II Pro, > and Spartan 3 if the IOs are operated at 3.3V, you may exceed the Abs Max > data sheet limits if you do not pay attention to what you are doing. And > that will cause a reduction in the 20 year projected lifetime. Below 3.0V, > there are no reliability issues to consider, as the clamp diodes are > sufficient to protect the IOs. Smaller, faster, less expensive technology > from the foundries has some drawbacks: leakage current, and IO robustness > at voltages greater than 3.75 volts being two of them. > > The new tools allow for extraction of all pcb parameters, and easy > simulation of all tracks/traces. You can also create a design that is > correct by construction: use DCI or series or parallel termination, and > make 50 ohm (or whatever) traces. Then you do not have to simulate > everything. So the DCI in the S3 chips will allow matching of the chip IO impedance to the trace, right? > Or use a standard: HSTL, SSTL, PCI. Then you also don't have to think. > But I also simulate to make sure I haven't missed anything. I only wish standards really did preclude the "thinking". I have worked with RS-232 and many others too long to beleive that. -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAXArticle: 60921
Sam Kaan wrote: > > banktrade2002@yahoo.com (Emile) wrote in message news:<952209fb.0309220456.7aae7278@posting.google.com>... > > rickman <spamgoeshere4@yahoo.com> wrote in message news:<3F6E9D92.98206CA3@yahoo.com>... > > > If you are really interested, I have the old ORCA software for schematic > > > entry using Workview (included). It may use a hardware key, I don't > > > remember. I must have one around, but it may take a bit to find it. > > > The software however, I have handy if you are interested. > > > > > > But my advice is to toss the board and deny ever having found it. :) > > > > Just a note to say we have 500 Lucent ORCA FPGAs on consignment sale, > > 250 each of the OR2T15 and OR2T40. Any reasonable offer is welcome. > > > > -Emile > > Are the OR2T15 and OR2T40 fairly new chips or the obsoleted ones? I > guess I don't really care as long as the tools that are available can > still program them. If I train yourself with it, that's what really > matters for me anyway. Both of these chips were on our board designed in 1999 and they were not new chips then. But I don't know that they are obsoleted. As to tools, you will need to check with Lattice. Lucent did not provide current tools for these parts. Lattice may cover them under their newer toolset, or may not... -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAXArticle: 60922
Thanks Steve. I appreciate the feedback. "Steve Lass" <lass@xilinx.com> wrote in message news:3F71C406.3050105@xilinx.com... > Our limited testing has show Linux to be about 10% faster than Windows > running PAR. Linux > also uses less memory. The average is about 6% less and a few really > big designs that run out > of memory on Windows XP run fine under Linux. > > Steve > > Matt wrote: > > >Hehe... okay, let me rephrase. Have you noted any performance differences > >relative to your Windows experiences? Good and bad. I promise not to call it > >a benchmark! ;-) > > > >I haven't had the opportunity to try the Linux version yet. --Matt > > > > > > > >"Hans" <hansydelm@no-spam-ntlworld.com> wrote in message > >news:CIWab.308$Ne.985132@newsfep2-win.server.ntli.net... > > > > > >>Hi Matt, > >> > >>No I haven't (too busy). Also you know what they say about benchmarks > >> > >> > >"Lies, > > > > > >>Damn Lies and Benchmarks :-) > >> > >>Hans. > >> > >>"Matt" <bielstein2002@comcast.net> wrote in message > >>news:SMPab.521826$YN5.347243@sccrnsc01... > >> > >> > >>>Question... have you done any benchmarks for performance relative to > >>>Windows? (Synthesis/Translate/Map/PAR) Same or similar hardware would be > >>>best. > >>> > >>>Thanks in advance! > >>> > >>>"Hans" <hansydelm@no-spam-ntlworld.com> wrote in message > >>>news:1nzab.364$4G3.59567@newsfep2-gui.server.ntli.net... > >>> > >>> > >>>>Try (bash), > >>>> > >>>>export LD_ASSUME_KERNEL=2.4.1 > >>>> > >>>>It runs fine on my RH9, > >>>>Hans. > >>>>www.ht-lab.com > >>>> > >>>>"Garry Allen" <garrya@ihug.com.au> wrote in message > >>>>news:3abc4240.0309181808.3e1b9cbc@posting.google.com... > >>>> > >>>> > >>>>>I am very thankful that Xilinx is now supporting Linux directly in > >>>>>ISE6.1. However, out of the box it only directly supports Redhat 7.3 > >>>>>and Redhat 8. Has anyone managed to install it under Redhat 9 and > >>>>> > >>>>> > >what > > > > > >>>>>if anything did you need to do to get it to call the glibc libraries > >>>>>successfully? > >>>>> > >>>>>At the moment when I run ./setup, it fails with an error msssage > >>>>>stating that it cannot find the glibc libraries. I am unsure if I > >>>>> > >>>>> > >can > > > > > >>>>>run multiple versions of the gcc compiler > >>>>>Comments > >>>>>Thanks > >>>>>Garry Allen > >>>>> > >>>>> > >>>> > >>>> > >>> > >>> > >> > >> > > > > > > > > >Article: 60923
I am trying to use the embedded ppc in Xilinx Virtex 2 pro FPGA to reconfigure the same. I have gone thro the embedded design applications , xapp 058, xapp503. As I see, those applications had external processors, but what i am trying to achieve is store bit files in PROM , boot with a file , later, access the other file from PROM and reconfigure the entire device. It seems, System ACE Cf is a promising solution to this. But I need help on how to interface PROM with PPC To put it precisely, I am trying to load bit streams on the fly by configuring PPC I would appreciate any advice and help Early thanks for the time spend to reply. Thank you Regards Ramnathan >Article: 60924
Steve Lass wrote: > > Our limited testing has show Linux to be about 10% faster than Windows > running PAR. Linux > also uses less memory. The average is about 6% less and a few really > big designs that run out > of memory on Windows XP run fine under Linux. > > Steve Do they have the same ceiling ? ISTR comments on (some versions?) of windows only being able to access 2GB RAM, because MS decided the other 2GB was for them, not for you. ( and who would want > 2GB anyway.... :) Any tests of Linux/AMD 64 bit CPUs P&R ? -jg
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