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On Wed, 30 Jul 2003 19:45:56 -0600, Thad Smith <ThadSmith@acm.org> wrote: >Thad Smith wrote: > >I'm following up my own post for a correction. > >> Assuming that the DAC is updated once each cycle of the output >> frequency, you want your frequency to be within f (1 +- 1/3600), which >> would generate the maximum phase error, assuming that the phase was >> exactly matched at the beginning. That suggests that you want at least >> a 12-bit converter. > >12 bits should be sufficient for the full scale frequency. Since the OP said he needed to >track 1 to 50 Hz with 0.1 degree max phase error, he will need an additional 6 bits to get >the required resolution at the low end (1 Hz). Not true. The OP quoted the phase error spec in terms of degrees, not microseconds. .1 deg is 1 out of 3600 at any frequency. So 12 bits (which gives 1 out of 4096) is good enough at any frequency. -Robert Scott Ypsilanti, Michigan (Reply through newsgroups, not by direct e-mail, as automatic reply address is fake.)Article: 58701
Hi Fellows, I have main architecture consists of different components. All these components are defined in different *.vhd files and I am combining all these VHDL files in one *.vhd file and downloading into the CHIP and it's working fine according to logic. Lets call this main BLOCK as BLOCK1. Now,I need 6 of these blocks on the same chip (I am using XCV600 device). And I need to interconnect different signals defined in the BLOCK. say for example I need to loop all of them together. How could I accomplish this task. I want only one *.vhd file so that it would be easy to download one *.rbt file into the chip at one time. 1. Do I have to define different input / output signal so that every BLOCK has different signal names from each other and than use port map and component decelartion in top *.vhd file to accopmlish the task. Thats how all these *.vhd files would be in one *.vhd file. For example in one BLOCK I have 4 entity/arch for 4 components and 1 main entity/arch where port mapping and component decleration is defines , so I have 5 entity / arch in one BLOCK and it's in one *.vhd file. Thats how for 6 of these BLOCK I would have 30 entity/arch + 1 main entity/arch in which all of these components (which I think 6 one of each BLOCK)will be defined along with port mapping. So in all 31 entity/arch pair would be in one *.vhd file. Do you think is this correct. Or is there is any other better way to do this. 2. How can I use make file option to compile 6 different *.vhd files (one of each block )and 1 main *.vhd file (for component decleration and port mapping) to generate one *.rbt file. I am worried because I have to use 12 BLOCKS of different logic design having 12 entity/arch pair block (in all 145 Entity/arch pairs )and interconnect all these 12 block with 6 above mentinoed BLOCKS. Cheer Guru's Any help would be appreciated. IsaacArticle: 58702
"Subroto Datta" <sdatta@altera.com> wrote in message news:<cH0Wa.44$n54.3@newssvr16.news.prodigy.com>... > Jean-Luc, > > To simulate, either do a functional sim prior to synthesis or do a > timing simulation using the VHDL/Verilog netlist generated after place and > route.A step by step description can be found in: > http://www.altera.com/support/software/nativelink/simulation/modelsim/eda_vi > ew_using_msim.html > > - Subroto Datta > Altera Corp. > Thank you. I did a functional simulation but I have timing problems with embedded ram cells that are not detected by static analysis (either dc or quartus). I tried a timing simulation after place and route as indicated by the link you give (and it worked quite fine indeed !) but wanted to simulate the design before the replace_fpga command hoping to keep meaningful names in the design. Actually is there a way to match signals in the output vho file produced by quartus against 'original' signals without headaches ? ThanksArticle: 58703
"Paul Leventis" <paul.leventis@utoronto.ca> wrote in message news:<4VYVa.24466$hOa.9030@news02.bloor.is.net.cable.rogers.com>... > > One additional source of info would be to get the fab costs for the > > 8"/12" wafers from say TSMC or UMC and try to figure the production > > costs of your FPGA and possibly your own design committed to an ASIC > > directly for comparison. > > > > I am not saying this is easy... > > You can say that again -- I don't think it's possible for anyone outside the > operations/product engineering groups of an FPGA company to compute the cost > of FPGA fabrication. You need to know (a) wafer prices (b) mask costs > (ammortized over # of chips produced) (c) defect density vs. demand over > product lifetime (d) die sizes (e) suceptability to defects (f) repair rates > (for Altera parts w/redundancy) (e) development/support/software costs > (ammortized over products sold) etc. And because big FPGA manufacturers are > some of the largest fab customers/partners, I'd guess they don't pay list > price... > > Regards, > > - Paul Leventis > Altera Corp. As Rajeev so accurately stated in an earlier post, "...multiple pricing plans are offered, and vendors make it difficult to find out the best available price ...". As liquidators of networking companies worldwide, we see incredible pricing disparities all the time, from x to 5x. Something else that everyone should well be aware of is this: contract manufacturers buy these high-end devices in the open market every day via their "preferred, non-franchise, suppliers". Why would Celestica buy an XCV2000E-6FG680C at ₤800 when they can buy it at ₤350, "under the radar" of franchise, and invoice the customer at ₤800, the contract price? If the parts are new, factory sealed, guaranteed as fit, form, and function, and being sold on Net 60 terms, it seems to make sense. At the very least, they "blend" the purchases. My self serving shpeal: If you use Xilinx, Altera, PMC-Sierra, Broadcom, or other high-end devices common in the Next Generation space, such as lasers, and just want to know what the "grey market" price is for a particular device, just ask. We'll be happy to send a quote, a digital photograph, and total availability. Regards, EPArticle: 58704
jaxlau@yahoo.com (Jacques athow) wrote in message news:<acc717b2.0307302009.3a3150ba@posting.google.com>...
> I have a project that needs a 21.48MHZ clock input. But the problem is
> that I dont have that type of oscillator. As the project is going to
> be in an large FPGA , is it possible to generate using coregen and a
> 40MHZ square source(the FPGA clock), a dds with adequate resolution
> and that at a certain phase increment, would in turn generate the
> 21.48MHZ needed but as a sinusoid.
>
Sorry, but your All-Digital DDS idea sounds really stupid.
If you want to go DDS, you should output the sin wave to the proper
DAC, filter out the alias at Fs-Fout with analog filter and convert to
the square wave with good precise comparator.
Plus, Fs=40MHz is not enough, you need at least 70-100MHz.
Plus, if the phase noise of the Fout is important you will need very
clean board layout - any GND noise on the analog part is directly
translated into phase noise. Etc...
Can you afford a jitter of order of 5ns ? Then, it would be really
simple: multiply 40MHz signal up to 200MHz with DLL and build your
21.48MHZ Fout from the accumulator, running at 200MHz:
acc(31..0) = acc(31..0) + INCR;
Fout = acc(31);
where
INCR = round((21.48 * 2^32)/200) = 461279488;
Article: 58705Robert - a 12 bit converter is not capable of 12 bits - ever. Even for perfect power and perfect VCO and perfect loop filter, the design is going to require a 14 bit converter. The other things that are not mentioned in here are: 1) the loop filter - you are going to need close to 80dB - ouch, can you say guard band and really good board design 2) a "perfect" VCO. I've built a fair number of pll's for accurate clocks - used to work on clock jitter for a living. This design is going to take a good analog engineer, and a good simulation package and good models to get it to work to spec. Andrew Robert Scott wrote: >On Wed, 30 Jul 2003 19:45:56 -0600, Thad Smith <ThadSmith@acm.org> >wrote: > > > >>Thad Smith wrote: >> >>I'm following up my own post for a correction. >> >> >> >>>Assuming that the DAC is updated once each cycle of the output >>>frequency, you want your frequency to be within f (1 +- 1/3600), which >>>would generate the maximum phase error, assuming that the phase was >>>exactly matched at the beginning. That suggests that you want at least >>>a 12-bit converter. >>> >>> >>12 bits should be sufficient for the full scale frequency. Since the OP said he needed to >>track 1 to 50 Hz with 0.1 degree max phase error, he will need an additional 6 bits to get >>the required resolution at the low end (1 Hz). >> >> > >Not true. The OP quoted the phase error spec in terms of degrees, not >microseconds. .1 deg is 1 out of 3600 at any frequency. So 12 bits >(which gives 1 out of 4096) is good enough at any frequency. > > >-Robert Scott > Ypsilanti, Michigan >(Reply through newsgroups, not by direct e-mail, as automatic reply address is fake.) > > >Article: 58706
> Subject: RAM reset question - Xilinx Virtex > From: "Jamie Sanderson" <jamie@nortelnetworks.com> > Date: Fri, 26 Jan 2001 11:39:30 -0500 >Since Virtex came out, Xilinx has been recommending against use of the >global reset logic. I'm wondering now if that doesn't affect initialisation >of memory components. If I do require my memories to be re-initialised, >could I simply hook up my reset line to a manually instantiated startup >block, without changing any of my other logic? Or is it an all or nothing >decision? > >Your input is appreciated! > I read the above article in archive of this NG. I think the "global reset logic" meaned GSR. But I didn't find any offcial document about the GSR usage from Xilinx. "rickman" <spamgoeshere4@yahoo.com> news:3F27FFBD.12C17DA0@yahoo.com... : louis lin wrote: : > : > In the archive of this NG, some article said Xilinx has been recommending : > against use of the global reset logic. But I never found any application note : > of Xilinx about this issue. : > Could you please tell me where is the related statement or document? : > : : I don't think anyone has said that the global reset should not be used. : I belive the issue is that because of its slow propagation delay, it can : not guarantee a clean exit from reset. That is, it can't guarantee a : clean exit unless you do some thinking about your design. : : For example, if you use FSMs, the initial transition should depend on an : external signal or some other delayed reset. That way you can be sure : that the reset has been removed from all FFs in the FSM and they will : not startup out of sync. : : In essence, any part of your design that can get out of kilter if the : reset ends on different clock cycles should be synchronized using some : other signal. You can think of this as a post-reset enable signal. : : -- : : Rick "rickman" Collins : : rick.collins@XYarius.com : Ignore the reply address. To email me use the above address with the XY : removed. : : Arius - A Signal Processing Solutions Company : Specializing in DSP and FPGA design URL http://www.arius.com : 4 King Ave 301-682-7772 Voice : Frederick, MD 21701-3110 301-682-7666 FAXArticle: 58707
Prasanna wrote: > > Here are some examples I can think of. > > Lets say you have a mode bit that you use in your logic and you know > some paths specifically do not exist when the core is not in that > mode, that becomes a false path. > > Lets say, you do a complex logic such as a CRC and find that your > final CRC evaluation takes more than one clock cycle (based on byte > enables) and cannot meet the speed requirements. You can pipeline the > data and calculate final CRC in multiple clock cycles. This is exactly what multicycle is not. If you allowed the CRC calculation to have two or three clock cycles for the logic delays to settle out and used an enable on the register at the end, that would be a multicycle path. This requires a separate multicycle timing spec since otherwise the tool will try to optimize this to get it to run in one clock cycle. If you add pipeline registers, then each stage will need to be done in a single clock cycle and will definitely *not* be multicycle. -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAXArticle: 58708
Hi All, I have some questions regarding my frequency counter design which is using xc4085xl-09-bg560. I am using Xilinx Foundation series 2.1i. This Frequency Counter is to measure frequency from QCM (Quartz Crystal Microbalance sensor) which operate at 10MHz. There will be 8 QCM input hence i am using 8 clock input. Since it required me to use dedicated clock buffer, i am using BUFG for all the clock input of this QCM. Should i use difference clock buffer for each clock input ? Which buffer should i use for each clock input? Below are the Warnings After Implementation: For number 2 & 3 , i dont understand this Warning and how to handle this warning. 1.WARNING:NgdHelpers:359 - The input pad net "CLK" driving one or more clock loads should only use a dedicated clock buffer (e.g., BUFG, BUFGP, BUFGS). This could result in large clock skews on this net. 1a. WARNING:Timing - Clock nets using non-dedicated resources were found in this design. Clock skew on these resources will not be automatically addressed during path analysis. To create a timing report that analyzes clock skew for these paths, run trce with the '-skew' option. 2. WARNING:OldMap:78 - All of the external outputs in this design are using slew-rate-limited output drivers. The delay on speed critical outputs can be dramatically reduced by designating them as fast outputs in the original design. Please see your vendor interface documentation for specific information on how to do this within your design-entry tool. Note: You should be careful not to designate too many outputs which switch together as fast, because this can cause excessive ground bounce.For more information on this subject, please refer to the IOB switching characteristic guidelines for the device you are using in the Programmable Logic Data Book. 3.WARNING:OldMap:548 - All the logic for "HMAP symbol "U5/U9/HMAP_60" (output signal=Q_OUT<8>)" has been removed! This may be caused by key logic being trimmed. Please consult the Removed Logic section of this report to see if this is the case. YOur comments is much appreciated. Very many Thanks, EmiliaArticle: 58709
John Williams <jwilliams@itee.uq.edu.au> wrote in message news:bg6ve1$jqh$1@bunyip.cc.uq.edu.au... > Hi Jon, > Last I looked, Handel-C permits pointer variables, and pointer > dereferencing. Say you declare an array of some 10 elements of a > datatype (let's say bytes for convenience). > > byte myarray[10]; > byte *ptr = myarray; > > AFAIK this is all legal and synthesisable Handel-C syntax. > > Now, you can dereference ptr, and you can also increment it. > > So far I'm happy, the synthesis tools can just implement the array as an > addressable register or something like that. > > However, what happens when you increment "ptr" past the last element in > the array, and then dereference it? Then you face the fact that it's > not *really* a pointer, it's just a syntactic construct that *looks* > like a pointer, and in limited set of circumstances will *act* like a > pointer. Right about now my brain caves in thinking about what it would > really mean to have a pointer in an FPGA... Surely the difference here is that in software a pointer will take a structure that will allow it to point to some point in memory. You can increment this past the last element in an array, but you'll be able to decrement it back to a valid position. If you increment past the last element and de-reference it you'll get the contents of the memory at that location, but this isn't a valid result. In hardware the synthesis tool could implement an array of registers with a mux and de-mux to select the relevant location. It could also use a RAM. What happens when the pointer is incremented past the last element depends purely on the actual structure used to implement the pointer for that size of array/RAM, but once again you don't get a valid result. Nial. ------------------------------------------------ Nial Stewart Developments Ltd FPGA and High Speed Digital Design www.nialstewartdevelopments.co.ukArticle: 58710
Jonathan Bromley wrote: > Find yourself a civilised editor with a block/column select and > fill facility. On Windoze we generally use TextPad, which is > pretty goodand can be had in a free eval version if you don't > mind the nag screens: > www.textpad.com > > Or NEdit on Unix/Linux. I admit to being an emacs user here. :-). http://geekshirts.sourceforge.net/gallery.php3?thumbs=true&name=policeII Jon.Article: 58711
The idea here would be to make an all digital high frequency generator, which would stay inside of the FPGA. Usually, a DDS generates sine values from a look up table located inside some block memory. I've understood the idea with an outside DAC and an inverter bias to make it work as a high gain amplifier so that the sinusoidal no longer appears as a sine but a squarewave. The delay of the gate would indeed put the main constrain on the maximum frequency of operation. Now the thing that I wanted to know is could we just use the values inside of the FPGA and just by having a digital comparator that outputs a logic high when the sine values exceed a limit and then otherwise, remains to zero. From my point of view, this will create the clipping effect. I dont know if it is correct thought to think of it like that. The values at the output of any DDS are the sinusoidal coefficients that when placed on a DAC, will results in some voltage/current weight of the sine to be created. I think it should work anyway. hmurray@suespammers.org (Hal Murray) wrote in message news:<vihl2m7a4kc4fd@corp.supernews.com>... > >output of this block, we would theoretically have a square wave. The > >only inconvenience is that the generated square wave would be one that > >doesn't possess a 50% duty cycle. > > Why wouldn't it be (close to) 50% duty cycle? How close do you > need? > > If you do the clipping with an inverter and AC couple the sine > wave to the input and bias the input with a big resistor feeding > back from the output, there is feedback on the bias that wil > set the clipping level to make a 50% duty cycle output. > > I'm not sure how well that works at high speeds. It works fine > at anything that isn't pushing the inverter very hard.Article: 58712
Hi, As a study for a project I need to investigate the possibility of implementing a tiny TCP/IP stack and tiny MAC controller on FPGA. This stack is capable to transfer some data packets directly into S(D)RAM without help of the microcontroller. Thus a simple communication via Ethernet from the desktop PC is required for download/upload to/from the memory. The FPGA board is attached to an Ethernet PHY device such as DP83847A. In this case a MAC controller was implemented in FPGA but the FPGA utilitization is too high. There is less room available for other blocks. My intention is to build a small TCP/IP stack and MAC blocks in the FPGA and the transaction between FPGA/Ethernet PHY and the desktop PC has to kept as simple as possible. Thus no heavy/extensive protocol is needed. The questions raised are: 1. What is the minimum TCP/IP function set required to do simple file transfer and etc.? 2. Is it possible to perform all tasks only in FPGA without help of the microprocessor? 3. Are there any resources (VHDL code and C program on PC) available on this topic? I will welcome all comments and suggestions. please feel free to write us at erik.coenders@philips.com Thank you all.Article: 58713
Hi all.
I am trying to learn VHDL on my own using textbooks and the Altera
MaxPlusII Baseline simulator.
I am trying to implement a rather trivial digital ciruit using
structural modeling (i.e. components and configurations). Below I am
showing my VHDL code as Part A and Part B. Part A contains the main
part of the code and Part B contains the entities (and their
architectures) of the components used in part A. Here are they:
Part A:
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
ENTITY example1 IS
PORT(
IN1, IN2: IN STD_LOGIC;
OUT1 : OUT STD_LOGIC);
END example1;
ARCHITECTURE ex1_str OF example1 IS
COMPONENT AND2
PORT (A,B: IN STD_LOGIC;
C: OUT STD_LOGIC);
END COMPONENT AND2;
COMPONENT NAND2
PORT (A,B: IN STD_LOGIC;
C: OUT STD_LOGIC);
END COMPONENT NAND2;
COMPONENT OR2
PORT (A,B: IN STD_LOGIC;
C: OUT STD_LOGIC);
END COMPONENT OR2;
-- Configuration specification
FOR A1: AND2 USE ENTITY WORK.AND2(AND2_ARCH);
FOR N1: NAND2 USE ENTITY WORK.NAND2(NAND2_ARCH);
FOR O1: OR2 USE ENTITY WORK.OR2(OR2_ARCH);
SIGNAL Z1, Z2 : STD_LOGIC;
BEGIN
-- Component Instantiation Statement
A1: AND2
PORT MAP ( A => IN1, B => IN2, C => Z1);
N1: NAND2
PORT MAP ( A => IN1, B => IN2, C => Z2);
O1: OR2
PORT MAP ( A => Z1, B => Z2, C => OUT1);
END ex1_str;
Part B:
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
ENTITY AND2 IS
PORT(
A,B: IN STD_LOGIC;
C: OUT STD_LOGIC);
END AND2;
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
ENTITY NAND2 IS
PORT(
A,B: IN STD_LOGIC;
C: OUT STD_LOGIC);
END NAND2;
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
ENTITY OR2 IS
PORT(
A,B: IN STD_LOGIC;
C: OUT STD_LOGIC);
END OR2;
ARCHITECTURE AND2_ARCH OF AND2 IS
BEGIN
C <= A AND B;
END AND2_ARCH;
ARCHITECTURE NAND2_ARCH OF NAND2 IS
BEGIN
C <= A NAND B;
END NAND2_ARCH;
ARCHITECTURE OR2_ARCH OF OR2 IS
BEGIN
C <= A OR B;
END OR2_ARCH;
Here are some of my attempts:
1.
I put part A and part B in the same file and tried to compile, but the
attempt failed. Should part B reside in a different file and be
compiled as a library?
2.
The Altera Help files are very vague on how to compile a library. If I
put part B in a separate VHDL file, how can I compile that file and
make it part of the WORK library? Or more general, how can I make that
file part of a library other than WORK?
Thank you in advance,
Nikos Annitsakis
Article: 58714All, The Fclock of a DDFS has to be at least 2X the Fout (just to work). Using the sine lookup table, and the DAC will improve the performance, especially if you filter the output of the DAC will a narrow BPF or a clean up PLL (will reduce jitter a lot). My suggestion? Double the clock in to 80 MHz, run the DDFS, do a sine lookup, go to a 10 bit DAC, use a PLL or BPF, and then feed the result back into an HSTL or SSTL input comparator (with Vref = Vcco/2). Make sure you have sufficient resolution (ie bits) in the DDFS to get within your frequency accuracy requirement of the 21.84 MHz. It may be that you will never be "exactly" 21.84 MHz with a 80 MHz input clock....(always off by ~ Fclock * 1/2^N where N is the number of bits in the DDFS). Austin Michael S wrote: > jaxlau@yahoo.com (Jacques athow) wrote in message news:<acc717b2.0307302009.3a3150ba@posting.google.com>... > > I have a project that needs a 21.48MHZ clock input. But the problem is > > that I dont have that type of oscillator. As the project is going to > > be in an large FPGA , is it possible to generate using coregen and a > > 40MHZ square source(the FPGA clock), a dds with adequate resolution > > and that at a certain phase increment, would in turn generate the > > 21.48MHZ needed but as a sinusoid. > > > > Sorry, but your All-Digital DDS idea sounds really stupid. > If you want to go DDS, you should output the sin wave to the proper > DAC, filter out the alias at Fs-Fout with analog filter and convert to > the square wave with good precise comparator. > Plus, Fs=40MHz is not enough, you need at least 70-100MHz. > Plus, if the phase noise of the Fout is important you will need very > clean board layout - any GND noise on the analog part is directly > translated into phase noise. Etc... > > Can you afford a jitter of order of 5ns ? Then, it would be really > simple: multiply 40MHz signal up to 200MHz with DLL and build your > 21.48MHZ Fout from the accumulator, running at 200MHz: > acc(31..0) = acc(31..0) + INCR; > Fout = acc(31); > where > INCR = round((21.48 * 2^32)/200) = 461279488;Article: 58715
Jaques, It is called using the MSB directly. You do not get any reduction in jitter (ie jitter is one clock period peak to peak). Do it all the time. Austin Jacques athow wrote: > The idea here would be to make an all digital high frequency > generator, which would stay inside of the FPGA. Usually, a DDS > generates sine values from a look up table located inside some block > memory. I've understood the idea with an outside DAC and an inverter > bias to make it work as a high gain amplifier so that the sinusoidal > no longer appears as a sine but a squarewave. The delay of the gate > would indeed put the main constrain on the maximum frequency of > operation. Now the thing that I wanted to know is could we just use > the values inside of the FPGA and just by having a digital comparator > that outputs a logic high when the sine values exceed a limit and then > otherwise, remains to zero. From my point of view, this will create > the clipping effect. I dont know if it is correct thought to think of > it like that. The values at the output of any DDS are the sinusoidal > coefficients that when placed on a DAC, will results in some > voltage/current weight of the sine to be created. I think it should > work anyway. > > hmurray@suespammers.org (Hal Murray) wrote in message news:<vihl2m7a4kc4fd@corp.supernews.com>... > > >output of this block, we would theoretically have a square wave. The > > >only inconvenience is that the generated square wave would be one that > > >doesn't possess a 50% duty cycle. > > > > Why wouldn't it be (close to) 50% duty cycle? How close do you > > need? > > > > If you do the clipping with an inverter and AC couple the sine > > wave to the input and bias the input with a big resistor feeding > > back from the output, there is feedback on the bias that wil > > set the clipping level to make a 50% duty cycle output. > > > > I'm not sure how well that works at high speeds. It works fine > > at anything that isn't pushing the inverter very hard.Article: 58716
Thanks for the responses everyone. I'm still a little puzzled, but it's gone from dark to murky =). news:<3f28efba.636665@news.wwnet.net>... > On Wed, 30 Jul 2003 19:45:56 -0600, Thad Smith <ThadSmith@> > wrote: > > >Thad Smith wrote: > > > >I'm following up my own post for a correction. > > > >> Assuming that the DAC is updated once each cycle of the output > >> frequency, you want your frequency to be within f (1 +- 1/3600), which > >> would generate the maximum phase error, assuming that the phase was > >> exactly matched at the beginning. That suggests that you want at least > >> a 12-bit converter. > > > >12 bits should be sufficient for the full scale frequency. Since the OP said he needed to > >track 1 to 50 Hz with 0.1 degree max phase error, he will need an additional 6 bits to get > >the required resolution at the low end (1 Hz). no-one@nowhere.com (Robert Scott) wrote in message > Not true. The OP quoted the phase error spec in terms of degrees, not > microseconds. .1 deg is 1 out of 3600 at any frequency. So 12 bits > (which gives 1 out of 4096) is good enough at any frequency. I'm on the same page with regard to the 1/3600 part at a frequency. I think what Thad is saying is that I need 12-bits at a given frequency, but to get to a given frequency I need more bits. If my range is 1-50Hz just to get to a frequency in that range (if I could do it in integer multiples of Hz) I'd need 6-bits assuming a 1:1 correlation between a bit and output Hz. Then I would need an additional 12-bits to do sub-frequency control to meet my phase requirement. Also,I think that the VCO's gain factor comes into play and will affect the number of bits, given I don't have a 1:1 correlation between a bit and a Hz. Thanks again for the responses... -- Jay.Article: 58717
"Austin Lesea" <Austin.Lesea@xilinx.com> wrote in message news:3F284FDE.71CE8DCF@xilinx.com... > Pete, > > We win some, we lose some. You never know what "feature" (or latent bug) will > be the deciding factor. > > But thanks for the feedback. I was well aware of the issue and the tradeoffs. > If folks want that 5V input tolerance without limiting resistors, they can > still buy Xilinx and use Spartan II, or Virtex. > Yes. Our problem was 3.3V (and sometimes even 2.5V) tolerance. Unfortunately, we needed the speed/capacity of either a VIIPro or a Str*t*x, so Spartan II/Virtex was not a possibility. PeteArticle: 58718
Glen Herrmannsfeldt wrote:
> Does the following generate a gated clock?
>> if shift_en_s = '1' then
Not if it follows the line
elsif rising_edge(clk) then
in a synchronous process.
It's the process template that
gives you a synchronous clock, not
any single sequential statement.
> The following statement must be done before the rest. While simulators may
> execute them in order, synthesized logic tends to execute them all at the
> same time.
>
>
>> bcd_value := bcd_value(22 downto 0) & ser_out_s;
>> bcd_out_s <= bcd_value;
Actually, the synth will give you a netlist that simulates
the same as that code, executed in order.
Sequential statements execute in zero sim time.
The only delay is for rising_edge(clk).
Your code is a hardware specification that can only
be completely understood in the context of simulation. There is
usually no one-to-one correspondence between code statements
and the synthesis netlist components.
> Does this generate a gated clock? Can you do it in traditional synchronous
> logic form, where either the previous contents, or the contents with "0011"
> added are loaded back in? (Also with the shift_en_s enable.)
>
>
>> if bcd_value(3 downto 0) >= "0101" then
>> bcd_value(3 downto 0) := bcd_value(3 downto 0) + "0011";
>> end if;
This synthesizes nothing unless bcd_value is assigned
directly or indirectly to an entity port.
If this assignment occurs within a synchronous process,
the output will be registered by clk.
> Gated clocks are especially hard in FPGA's.
If you stick to the synchronous process template, you
will never have one to worry about.
-- Mike Treseler
Article: 58719jaxlau@yahoo.com (Jacques athow) wrote: >Now the thing that I wanted to know is could we just use >the values inside of the FPGA and just by having a digital comparator >that outputs a logic high when the sine values exceed a limit and then >otherwise, remains to zero. So you take the output of the phase accumulator and feed that to a sinewave lookup table, then compare the output of the lookup table with a fixed value (which will have to be zero if you are trying to generate a squarewave from a sinewave) and use the output of the comparator as a clock. A very complicated way of recreating the phase accumulator MSB - maybe the synthesis tool will optimize away your whole idea. The MSB of the phase accumulator *is* your squarewave clock. The only problem is its edges jitters by as much as the phase accumulator clock period, in your case 25ns which is a bit embarrassing as the edges of the clock you are trying to generate are only 23ns apart. You only on chip solution is to use a faster phase accumulator clock to reduce the output jitter to an acceptable level.Article: 58720
Your first question should be the allowable peak-to-peak jitter of the 21.48 MHz output. Using a 40 MHz-clocked DDS would give you max +/-12 ns jitter in a purely digital design, no sinuoids at all. You can do much better by increasing the clock rate (use the DCM for that) to 200 MHz, resulting in a max jitter of 2.5 ns, and you can do better yet by using multiple accumulators to get the jitter down to 300 ps (that's what I am doing in a design I am working on right now). I do not see the need for any sinewaves... Peter Alfke, Xilinx Applications ================ Jacques athow wrote: > > I have a project that needs a 21.48MHZ clock input. But the problem is > that I dont have that type of oscillator. As the project is going to > be in an large FPGA , is it possible to generate using coregen and a > 40MHZ square source(the FPGA clock), a dds with adequate resolution > and that at a certain phase increment, would in turn generate the > 21.48MHZ needed but as a sinusoid. > > Now, in order to complete the design, the signal would remain in the > digital domain and pass through some clipping logic, which would give > a '1' when the sine value is greater than an arbritrary index. At the > output of this block, we would theoretically have a square wave. The > only inconvenience is that the generated square wave would be one that > doesn't possess a 50% duty cycle. > > Could we use the available DLL to reconstruct the clock, based from > the just created pseudo clock from the DDS? > > The tool used is coregen and we have a virtex 2 platform. > I would really appreciate some clues about this idea. > > Thanks. > JacArticle: 58721
Peter Alfke <peter@xilinx.com> wrote in message news:<3F1F1F1A.C5C50F9E@xilinx.com>... > Your question can best be answered by a Xilinx salesperson, or most > likely a Sales Representative. If they cannot get you the answer > dirctly, they contact the factory. > They will love to talk to you and give you a quote with "budgetary > figures". They really are your friend, because they have a vested > interest to make you succeed. That is the only way they will get paid. Peter, unfortunately this is not entirely correct. You are right if you talk about small companies talking to small distributors or large companies talking to large distributors. But if you are a small company talking to a large distributor - and xilinx uses only the largest distributors - than the distributor is your enemy. At least I had the feeling during my last couple of calls to distributors. A few weeks ago I send out a request for quotes for 100 pieves XC2S200 to all european xilinx distributors and got a single response! When XC2S was really new I asked Xilinx UK for samples. They did a search in some stock database an pointed me to Insight Munich who had a few parts in stock. But Insight simply denied that. "No Stock" was their answer. After calling three people at Xilinx in three countries and calling insight again and again finally sample stock magically apeared in munich exactly in the quantity that Xilinx hat told me. Please Xilinx: Hire some small, independant distributor in europe that is willing to talk to people who place orders that are worth just a few thousand dollars. To answer the original question: For quantities below 100 the prices never dropped in the past by more than a few percent. But there appeared new parts that are cheaper. Kolja SulimmaArticle: 58722
Austin, Thank you very much for the explanation. I wanted to be sure that I understood the problem well. It would have been nice if xilinx had that feature. I also did find out that Apex20KE would not support 1.8V input or output signals unless the Vccio was at 1.8V. So my assumption in my earlier email was wrong. Although, at Vccio = 3.3V, the inputs are 2.5 and 3.3V tolerant. Regards, Prashant Austin Lesea <Austin.Lesea@xilinx.com> wrote in message news:<3F284FDE.71CE8DCF@xilinx.com>... > Pete, > > We win some, we lose some. You never know what "feature" (or latent bug) will > be the deciding factor. > > But thanks for the feedback. I was well aware of the issue and the tradeoffs. > If folks want that 5V input tolerance without limiting resistors, they can > still buy Xilinx and use Spartan II, or Virtex. > > Austin > > Pete Fraser wrote: > > > "Austin Lesea" <Austin.Lesea@xilinx.com> wrote in message > > news:3F282CEE.521DD3E1@xilinx.com... > > > > > The reason why we "do not have this feature" is that the IO ESD cell > > > required for that feature is a non standard cell design (ie not a foundry > > > supported standard ESD IO cell). > > > > Thanks for the explanation. It's the first time I've > > heard it in adequate detail. > > > > However, you should know that it has cost you > > at least two designs that I know of.Article: 58723
Pete, Ah well. As I said. There is also the possibility of using a TI or QuickSwitch NMOS pass gate device to limit the high levels without affecting the speed. Austin Pete Fraser wrote: > "Austin Lesea" <Austin.Lesea@xilinx.com> wrote in message > news:3F284FDE.71CE8DCF@xilinx.com... > > Pete, > > > > We win some, we lose some. You never know what "feature" (or latent bug) > will > > be the deciding factor. > > > > But thanks for the feedback. I was well aware of the issue and the > tradeoffs. > > If folks want that 5V input tolerance without limiting resistors, they can > > still buy Xilinx and use Spartan II, or Virtex. > > > > Yes. Our problem was 3.3V (and sometimes even 2.5V) tolerance. > Unfortunately, we needed the speed/capacity of either a VIIPro > or a Str*t*x, so Spartan II/Virtex was not a possibility. > > PeteArticle: 58724
Paul Leventis wrote: > Hi Jason, > > First off, that's a pretty cool little algorithm... had to prove to myself > that it worked. ... > > I'm not sure that I've found the problem with your code, ... The best and quickest way to do both is to write a testbench an run a sim. This quickly resolves all questions about how the langage works and how the logic functions. > (0) I think the first problem is a lack of comments... uncommented code is > always wrong :-) My favorite comments are a plain text description at the top of each process about function and handshake protocols. These can be collected at the top of the architecture after the sim is working. Detail comments at the end of line, can often be replaced by by well-named statement labels, constants and variables. > (1) Process #3. I hate variables. Especially variables mixed with > signals... Signals are the only way in and out of a process. > you must be very disciplined when using variables (I only use > them in for loops...). So I honestly don't know what the code will > translate into, as you are assigning a value to variable, then assigning to > the variable to a signal, then changing the value of the variable. In the case referenced, the first value is exported to the signal at the next clk and the second value is held by the variable until the next clk, if it is needed. This is not as complex as you think. Variables are stuck inside the process. They only reach the entity ports if you make a signal assignment inside the process. Synthesis will use a register to save the variable's *final* value. only if this value is needed at the next clk. Run a sim sometime, and watch the variables as you trace code. -- Mike Treseler
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