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The Cyclone start with a 100 pin TQFT. Martin > Hi, > > My application requires a lot of core but few physical i/o lines. Can > anyone suggest a modern fpga that is delivered in a 68-pin plcc and/or > 80-pin pqfp package? > > Thanks, > > RobArticle: 58776
rickman <spamgoeshere4@yahoo.com> wrote in message news:<3F29C212.EC74896B@yahoo.com>...
> I could have emailed this directly to Peter, but I thought it might be
> useful to others. I have a socket on my board which requires 5 volt
> tolerance on a number of pins. It also has to be reasonably low power
> meaning I can't power a high current surge on power up. The part I
> currently have selected is the Altera EP1K30 which seems to do
> everything I need and should live with my 200 mA power on surge
> limitation. But all the other parts on the board can be Xilinx. So I
> would like to find a Xilinx alternative for this socket.
>
> In the Xilinx camp I have considered a couple of devices which are 5
> volt tolerant.
>
> Coolrunner - XCR3512XL - 3.3 volt, very low power, no RAM, current part.
> SpartanXL - 3.3 volt, low power, distributed RAM only, old tools only.
> Spartan2 - 2.5 volt, very high power, block RAM, current part.
>
> Is this a correct summary? Are there any parts that I have not listed
> that I should consider?
>
> I have been given a very good price on the Coolrunner XCR3512XL, but
> even with 512 macrocells, including small FIFOs (8 bits x 16 words, two
> FIFOs) uses up half the chip.
^^^^^^^^^^^^^
Unless the design is complete and you can verify that it fits AND you
have a pinout, this would scare the hell out of me. I have to admit
not having used the Coolrunnner, but over the past six years, we have
had an absolutely horrible time making very minor changes to
moderately full 95xxx series Xilinx CPLD's. Again, this may not apply
as much to the Coolrunner, since it is a completely different family -
but I'd still verify it first.
I agree with the other poster - what about the Cypress or Lattice
devices? I realize that gets you away from your "all Xilinx" board,
but is there really a good reason for desiring that (except maybe you
can get all parts from one distributor)?
Marc
Article: 58777I am very much aware of the Lattice parts. I had an LC5512MB slated for the socket. But when I found in the electrical spec notes that it is only 5 volt tolerant on 64 pins max, (and couldn't get any more detail from support) I decided to find another alternative. I am happy with the Altera part, the EP1K30. But I am just trying to eliminate any other contenders that I might be able to get cheaper. It would also be useful to get all the PLDs on this board from one vendor, even if I can't use the same software for each. Paul Sereno wrote: > > Rick, > I do not know if are aware about the new Lattice devices. In what > is called ispXP technology Lattice offers a CPLD architecture with the > option of using some of the Multi Function Blocks as Memory (FIFO, > Dual Port RAM, Pseudo Dual Port RAM). > The software is free from the Lattice website > (www.latticesemi.com) that comes with Synlify and Leonardo Spectrum as > synthesis tool. > This device is 5V tolerant and there is no "power surge" > problems. > > Regards, > > Paul, > > rickman <spamgoeshere4@yahoo.com> wrote in message news:<3F29C212.EC74896B@yahoo.com>... > > I could have emailed this directly to Peter, but I thought it might be > > useful to others. I have a socket on my board which requires 5 volt > > tolerance on a number of pins. It also has to be reasonably low power > > meaning I can't power a high current surge on power up. The part I > > currently have selected is the Altera EP1K30 which seems to do > > everything I need and should live with my 200 mA power on surge > > limitation. But all the other parts on the board can be Xilinx. So I > > would like to find a Xilinx alternative for this socket. > > > > In the Xilinx camp I have considered a couple of devices which are 5 > > volt tolerant. > > > > Coolrunner - XCR3512XL - 3.3 volt, very low power, no RAM, current part. > > SpartanXL - 3.3 volt, low power, distributed RAM only, old tools only. > > Spartan2 - 2.5 volt, very high power, block RAM, current part. > > > > Is this a correct summary? Are there any parts that I have not listed > > that I should consider? > > > > I have been given a very good price on the Coolrunner XCR3512XL, but > > even with 512 macrocells, including small FIFOs (8 bits x 16 words, two > > FIFOs) uses up half the chip. > > > > The Spartan 2 is not an option due to the startup power. > > > > If I am willing to work with the SpartanXL and I can get a good price on > > it, I could put that on the board. I am not crazy about having to use > > older, not so well supported tools. Having to use a different tool is > > the only real reason to not use the Altera part. What tools are > > available exactly? If I don't buy a third party VHDL synthesis tool, is > > there something equivalent to XST in the older "Classic" tools? Are the > > "Classic" tools "paid for" only? > > > > Any other chip family alternatives? > > > > -- > > > > Rick "rickman" Collins > > > > rick.collins@XYarius.com > > Ignore the reply address. To email me use the above address with the XY > > removed. > > > > Arius - A Signal Processing Solutions Company > > Specializing in DSP and FPGA design URL http://www.arius.com > > 4 King Ave 301-682-7772 Voice > > Frederick, MD 21701-3110 301-682-7666 FAX -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAXArticle: 58778
Rick, Any reason why you can not use the added series 100 ohm resistor method? If you select the drive levels/standards of the other devices, you may not even need resistors at all. In fact if they are 5V TTL drivers, then they will not be able to souce current all the way to 5V, and no resistors are required. That way you could also use Virtex II, or Spartan 3. By the way, there is no max Icc standby in the ep1k30 data sheet.....just typical. Power on surge is not specified at all. At least if we need a bit of current on startup, we always specify it. Austin rickman wrote: > I could have emailed this directly to Peter, but I thought it might be > useful to others. I have a socket on my board which requires 5 volt > tolerance on a number of pins. It also has to be reasonably low power > meaning I can't power a high current surge on power up. The part I > currently have selected is the Altera EP1K30 which seems to do > everything I need and should live with my 200 mA power on surge > limitation. But all the other parts on the board can be Xilinx. So I > would like to find a Xilinx alternative for this socket. > > In the Xilinx camp I have considered a couple of devices which are 5 > volt tolerant. > > Coolrunner - XCR3512XL - 3.3 volt, very low power, no RAM, current part. > SpartanXL - 3.3 volt, low power, distributed RAM only, old tools only. > Spartan2 - 2.5 volt, very high power, block RAM, current part. > > Is this a correct summary? Are there any parts that I have not listed > that I should consider? > > I have been given a very good price on the Coolrunner XCR3512XL, but > even with 512 macrocells, including small FIFOs (8 bits x 16 words, two > FIFOs) uses up half the chip. > > The Spartan 2 is not an option due to the startup power. > > If I am willing to work with the SpartanXL and I can get a good price on > it, I could put that on the board. I am not crazy about having to use > older, not so well supported tools. Having to use a different tool is > the only real reason to not use the Altera part. What tools are > available exactly? If I don't buy a third party VHDL synthesis tool, is > there something equivalent to XST in the older "Classic" tools? Are the > "Classic" tools "paid for" only? > > Any other chip family alternatives? > > -- > > Rick "rickman" Collins > > rick.collins@XYarius.com > Ignore the reply address. To email me use the above address with the XY > removed. > > Arius - A Signal Processing Solutions Company > Specializing in DSP and FPGA design URL http://www.arius.com > 4 King Ave 301-682-7772 Voice > Frederick, MD 21701-3110 301-682-7666 FAXArticle: 58779
Martin, If it had about half the pins and 10x the LE I'd be interested. Rob Martin Schoeberl wrote: > > The Cyclone start with a 100 pin TQFT. > > Martin > > > Hi, > > > > My application requires a lot of core but few physical i/o lines. Can > > anyone suggest a modern fpga that is delivered in a 68-pin plcc and/or > > 80-pin pqfp package? > > > > Thanks, > > > > RobArticle: 58780
Hi NG. What does the speed grade of a FPGA mean? What does it mean that a FPGA has a speed grade of -3 ??? Best Regards TerryArticle: 58781
Marc Randolph wrote: > > rickman <spamgoeshere4@yahoo.com> wrote in message news:<3F29C212.EC74896B@yahoo.com>... > > I have been given a very good price on the Coolrunner XCR3512XL, but > > even with 512 macrocells, including small FIFOs (8 bits x 16 words, two > > FIFOs) uses up half the chip. > ^^^^^^^^^^^^^ > Unless the design is complete and you can verify that it fits AND you > have a pinout, this would scare the hell out of me. I have to admit > not having used the Coolrunnner, but over the past six years, we have > had an absolutely horrible time making very minor changes to > moderately full 95xxx series Xilinx CPLD's. Again, this may not apply > as much to the Coolrunner, since it is a completely different family - > but I'd still verify it first. > > I agree with the other poster - what about the Cypress or Lattice > devices? I realize that gets you away from your "all Xilinx" board, > but is there really a good reason for desiring that (except maybe you > can get all parts from one distributor)? No, sticking with Xilinx is not a strong desire since the software is not common anyway. But Lattice has nothing that will fit this socket and I have not been able to get a decent price on a Cypress part. I guess that is also part of my goal to use Xilinx. I have gotten some really great pricing on the parts I have discussed with them. They are working with me, so it makes me want to work with them. But I agree that using the XCR3512XL is scaring me as well. That is why I am asking about other Xilinx alternatives. I am sure I looked at the Cypress parts. I need about 170+ IOs in a 256 FBGA. The insides are not real important since that many IOs almost always means a larger part than what I need, say 20,000 gates or 1000 LUT/FF. The memory is optional since with that many FFs I can make my own FIFOs easily. Any idea of what a real price in a Cypress part would run? I don't really see much that will fit the socket unless I am missing something. -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAXArticle: 58782
Glen Herrmannsfeldt wrote: > > "rickman" <spamgoeshere4@yahoo.com> wrote in message > news:3F2923F5.32975097@yahoo.com... > > Prasanna wrote: > > (snip) > > > > Lets say, you do a complex logic such as a CRC and find that your > > > final CRC evaluation takes more than one clock cycle (based on byte > > > enables) and cannot meet the speed requirements. You can pipeline the > > > data and calculate final CRC in multiple clock cycles. > > > > This is exactly what multicycle is not. If you allowed the CRC > > calculation to have two or three clock cycles for the logic delays to > > settle out and used an enable on the register at the end, that would be > > a multicycle path. This requires a separate multicycle timing spec > > since otherwise the tool will try to optimize this to get it to run in > > one clock cycle. If you add pipeline registers, then each stage will > > need to be done in a single clock cycle and will definitely *not* be > > multicycle. > > In an FPGA the register is pretty much free (in most architectures, anyway) > so you probably should pipeline it. Not always true. Anytime you add a register, you have to add setup time and output delay to your path. Plus your path must be broken arbitrarily and it is not simple to pick the optimal points. By not adding registers and using an enable on the one register, you allow the full N clock cycles for the logic to settle. This was exactly how we designed an ATM chip. Once the cell had been received we had three clocks to analyze it and decide what to do with it. Turns out we needed all three as a multicycle. If we had pipelined it we would not have met the timing budget. -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAXArticle: 58783
emilia wrote: > > > > > "There is probably no reason to use global buffers for any of the QCM inputs. > > If you are just measuring their frequencies, each QCM input is probably only > > driving a single counter, which is then sampled into the system clock > > domain. Since each QCM load is small, you don't need a global buffer. You > > just need one for the system clock." > > -Kevin > > Hi Kevin, > > Thanks for the response. Actually i have another clock input which > operate at 1KHz, this clock will to to counter which will then produce > pulse every 1s. This pulse will to each of the QCM counter. Once the > QCM counter detected this pulse it will latch the measured frequency > of the QCM. So do i need to put Global buffers for this 1KHz clock > input and just use normal buffer for 8 of the QCM clock input ? I replied to your email about this. I recommend that you not use a clock buffer for the 1 kHz reference. Instead treat it like a signal and reclock it into each of the 8 QCM clock domains. There you can detect the rising edge and use that to enable a 1 second counter (0 to 999). Of course this will use more logic than a single time base counter, but you will not need a ninth global clock route. Since your chip does not have a ninth clock input, your only other alternative is to control the skew on the clock net and to manually verify the skew on every P&R. I don't think the tools will automatically control this for you. -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAXArticle: 58784
Kolja Sulimma wrote: > > Another anekdote: > Insight forced me to buy two complete lots of 24 -I needed 30 - > because breaking up a lot alledgedly was to much hassle and than > delivered three lots of 15, 10 and 23. I feel your pain. I once tried to order some parts from a vendor who had a partial pack in stock. I was told I had to buy a full pack irregardless because they "don't break packs". So they wanted to ship me the partial now and back order the rest... No, I am pretty sure it was not me who was missing something! -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAXArticle: 58785
Rob Judd wrote: > > Hi, > > My application requires a lot of core but few physical i/o lines. Can > anyone suggest a modern fpga that is delivered in a 68-pin plcc and/or > 80-pin pqfp package? > > Thanks, > > Rob No, the best you will do is a VQFP100 or you will have to use a CPLD. The CPLDs come in some pretty small packages, but not a lot of density in them. -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAXArticle: 58786
Austin Lesea wrote: > > Rick, > > Any reason why you can not use the added series 100 ohm resistor method? If > you select the drive levels/standards of the other devices, you may not even > need resistors at all. In fact if they are 5V TTL drivers, then they will > not be able to souce current all the way to 5V, and no resistors are > required. > > That way you could also use Virtex II, or Spartan 3. This is for an PC/104 bus interface. Some of the signals are bidir and even the rest have to be both directions since this board will support both master and slave operation. Some signals are pullup up to 5 volts with 330 ohm resistors. Will Virtex II drive that? I am not willing to risk anything on the Spartan 3 working with a 5 volt bus. They are currently not even 3.3 volt tolerant. > By the way, there is no max Icc standby in the ep1k30 data sheet.....just > typical. Power on surge is not specified at all. At least if we need a bit > of current on startup, we always specify it. If you call, Altera will give you power numbers. Well, when I called they gave *me* numbers :) -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAXArticle: 58787
Thank you, Jesse, for your responce. kempaj@yahoo.com (Jesse Kempa) wrote in message news:<95776079.0307250822.47aa38d1@posting.google.com>... > > The simplest solution to your current implementation attempt is to use > a signal that Nios (and all avalon masters) must respond to: the > waitrequest signal. Waitrequest is just that. When a master attempts a > bus transfer with a slave, it is locked waiting until the slave > negates waitrequest. I would caution you to ensure that your logic > negates waitrequest, as a logical error that would leave it asserted > would hang the CPU (or any other master) attempting access. > I tried it - it worked exactly as you told. Thanks !!! But not everything worked: I did managed to write to SDRAM, and to read the written value from there directly (by accessing certain address), when I used on-chip memory both for data memory and for program memory. It also worked when I used SDRAM (more specifically - interface to user logic) as a data memory, and on-chip memory as a program memory. But when I used SDRAM as program memory, it didn't work. I use Germs (the Germs itself if sitting on-chip) to upload the program, and the upload looked fine - it also looked fine in the logic analyzer, though I can't really check that the whole program was uploaded - I just saw that 'something' was uploaded. Anyway, the program just didn't work. Do you by any chance know what seems to be the problem here? > > > > Or maybe there is a way to configure NIOSes SDRAM controller to support > > two NIOS CPUs instead of using that external arbiter? > > > > The second thing I can suggest, and would recommend, is to make use of > our own bus arbitration logic. You can in fact connect two (or more) > masters (two Nios', DMA, your own custom master, another > microprocessor) to any avalon slave, including the SDRAM controller. > I believe that in the end I will use this controller, but for now I just have to use the "external" arbiter, because this controller/arbiter allows me to access the SDRAM directly through the PCI (the development board is a PCI card) Well anyway, Thanks. I hope that you or anyone else would be able to help me with this problem (the program memory problem) YevgenyArticle: 58788
se10110@yahoo.com wrote: > I think what Thad is saying is that I need 12-bits at a given > frequency, but to get to a given frequency I need more bits. I discussed this a little more in another post. The reason you need more bits is that at the low end of your range, you don't have as much relative precision. If, instead on 1 Hz minimum, you had a 10 Hz minimum, you would need only 3 additional bits to maintain adequate relative precision. Andrew Paule talks about some of the practical analog considerations and I defer to his expertise and experience in that area. > Also,I think that the VCO's gain factor comes into play and will > affect the number of bits, given I don't have a 1:1 correlation > between a bit and a Hz. Yes, it matters. You had stated earlier a gain factor that mapped 0 - 5 V to approximately 0 - 59 Hz, allowing you to use almost the full range of the converter. There is no need for a particular bit to represent a one Hz difference. ThadArticle: 58789
In article <3F2A868E.85807215@yahoo.com>, rickman <spamgoeshere4@yahoo.com> wrote: >Not always true. Anytime you add a register, you have to add setup time >and output delay to your path. Plus your path must be broken >arbitrarily and it is not simple to pick the optimal points. By not >adding registers and using an enable on the one register, you allow the >full N clock cycles for the logic to settle. This was exactly how we >designed an ATM chip. Once the cell had been received we had three >clocks to analyze it and decide what to do with it. Turns out we needed >all three as a multicycle. If we had pipelined it we would not have met >the timing budget. Of course, two observations: 1) Flip-flop setup and clk->Q combined are pretty low compared to interconnect costs. EG, from the Spartan II datasheet, the additional time if the flip-flop is the LUT output is ~2 ns. So even if your design is running at 100 MHz in one of these parts, only 20% of your time is going to the flops. In the Virtex II its in the <1 ns range on the slowest speedgrade. 2) Retiming can place those registers in the right place. You can either do the transformation by hand or use a tool, but I'm not sure how well Synplify will handle retiming through preplaced blocks, and the attempt to maintain initial conditions really hurts the power of this transformation. Nonetheless, it is possible, and NOT hard (given a timing model), to move all the registers manually into the right place, given the algorithm to solve the problem. If a block is feed forward, and you just want to repipeline the block, the task is easier. -- Nicholas C. Weaver nweaver@cs.berkeley.eduArticle: 58790
In article <3F2A4153.66C411AD@ob-wan.com>, Rob Judd <judd@ob-wan.com> wrote: >Hi, > >My application requires a lot of core but few physical i/o lines. Can >anyone suggest a modern fpga that is delivered in a 68-pin plcc and/or >80-pin pqfp package? Is your concern board area? Hand soldering? Cost? A small BGA package might be appropriate, as a .5mm spacing BGA for a small pincount is really tiny, if the concerns are board area and cost. -- Nicholas C. Weaver nweaver@cs.berkeley.eduArticle: 58791
> Unless the design is complete and you can verify that it fits AND you > have a pinout, this would scare the hell out of me. I have to admit > not having used the Coolrunnner, but over the past six years, we have > had an absolutely horrible time making very minor changes to > moderately full 95xxx series Xilinx CPLD's. Again, this may not apply > as much to the Coolrunner, since it is a completely different family - > but I'd still verify it first. > speaking of xilinx cpld's... You must design your logic towards the cpld's architecture. The 95xxx series are great, but they have problems when using more than 5 product terms (pt) per macrocell (mc). Also the 36 array inputs (for an 18mc array) can be too little. Some tricks like using a GTS or GTS net for an output bus can reduce the amount of product terms significantly. The fitter report gives some hidden hints for altering the partitioning of your logic to fit into the device. The 95xxxXL devices have 54 array inputs which is mostly more than you ever need. I've done lots of 95144xl designs with 144 mc usage and still alter the designs due to updated functional needs. The coolrunner XPLA3 devices have also 36 array inputs (for an 16mc array) but only 3 pt's per mc. The product terms can be assigned more flexible due to the pla, but for lots of applications that's no feature. A loadable 16bit up/down counter can not be done in one array since it needs 4 pt's per mc. So the XPLA3 device XCR3032 has less resources than an imaginary XC9532XL (The 9536xl has 4 more mc's !) but consumes less power. Of course there are also designs which benefits from the pla architecture. Both 95xxxXL and XPLA3 are 5 V tolerant. The coolrunner2 devices consumes one third of the power of the XPLA3 devices and have lots of additional features. They have 40 array inputs (for an 16mc array) and 3.5 pt's per mc. The core needs a 1.8 V supply, the inputs are not 5V tolerant, but can use schmitt triggers. FF's can toggle at both clock edges. The 128mc and > devices have built in clock dividers up to /16, and some additional io standards. The coolrunner2 devices are really cool, but the 95xxxXL devices have more logic resources. MIKEArticle: 58792
Hello, In article <3F2A9077.12B7170F@xilinx>, peter@xilinx says... > I have been watching this thread for a while... > Why would anybody do this design in analog, when it is so easy to get > close to perfection doing the whole thing digitally ? For the price of > one DAC you can get thousands of flip-flops. Use a 50 or 100 MHz clock > and achieve any accuracy you want. Use multi-phaese 200 MHz clocks if > you need better than one nanosecond precision... > Am I missing something ? Well, I cheated just a bit, I don't have a VCO, I have a motor control unit. I'm varying the voltage to the motor control unit to get a "frequency" out of it. My VCO "gain" is really the motor gain (RPM/Volt translated to Hz / volt). I didn't want to complicate the situation by bringing that in (being a motor and not a VCO doesn't alter the number of bits question) Using PWM would work for my application upto 11-12 bits(given a 40-60MHz input clock), but beyond that my PWM output frequency drops too low. I haven't solved this problem yet...dithering may work here. I also considered using a real DAC, buffering the output and driving an SMPS in voltage-control mode (to drive the motor) but as others have pointed out, the DAC noise problems will probably kill me. My newserver has been acting funny(read not letting me post), otherwise I would have tried to clairify a bit earlier. But I'm curious Peter, assuming I used a 50 to 100MHz clock, the only way to get the delays would be to make a (big) shift-register and delay my signal by clock cycles, right? Wouldn't that mean a huge multiplexor on the output to select which tap I use? How exactly would multi-phase 200MHz clocks work out here? Generate a 0deg and a 90deg signal using the DCM on a Xilinx part or something? Thanks again for all the helful responses everyone. -- Jay.Article: 58793
I have been watching this thread for a while... Why would anybody do this design in analog, when it is so easy to get close to perfection doing the whole thing digitally ? For the price of one DAC you can get thousands of flip-flops. Use a 50 or 100 MHz clock and achieve any accuracy you want. Use multi-phaese 200 MHz clocks if you need better than one nanosecond precision... Am I missing something ? Peter Alfke ================== Thad Smith wrote: > > Robert Scott wrote: > > On Wed, 30 Jul 2003 19:45:56 -0600, Thad Smith <ThadSmith@acm.org> > > wrote: > > >>I'm following up my own post for a correction. > >> > >> > >>>Assuming that the DAC is updated once each cycle of the output > >>>frequency, you want your frequency to be within f (1 +- 1/3600), which > >>>would generate the maximum phase error, assuming that the phase was > >>>exactly matched at the beginning. That suggests that you want at least > >>>a 12-bit converter. > >> > >>12 bits should be sufficient for the full scale frequency. Since the OP said he needed to > >>track 1 to 50 Hz with 0.1 degree max phase error, he will need an additional 6 bits to get > >>the required resolution at the low end (1 Hz). > > > > > > Not true. The OP quoted the phase error spec in terms of degrees, not > > microseconds. .1 deg is 1 out of 3600 at any frequency. So 12 bits > > (which gives 1 out of 4096) is good enough at any frequency. > > Yes, one part in 4096 gives sufficient resolution, but assuming that he > uses 12 bits to achieve the span 0 to 50 Hz, at the minimum frequency of > 1 Hz, his relative resolution is 1/50 of what is available at 50 Hz. > Hence he needs more bits for the same relative resolution at the low > end. There are other ways of handling it, such as a non-linear > transformation. > > ThadArticle: 58794
Nicholas, No, manufacturability is the main concern. I don't have easy access to high volume production machinery, which is almost guaranteed to be necessary for most of the newer packages. If I can plug it in, great. If not, I need to be able to hand-solder it with a standard Weller iron. Rob Nicholas C. Weaver wrote: > > In article <3F2A4153.66C411AD@ob-wan.com>, Rob Judd <judd@ob-wan.com> wrote: > >Hi, > > > >My application requires a lot of core but few physical i/o lines. Can > >anyone suggest a modern fpga that is delivered in a 68-pin plcc and/or > >80-pin pqfp package? > > Is your concern board area? Hand soldering? Cost? > > A small BGA package might be appropriate, as a .5mm spacing BGA for a > small pincount is really tiny, if the concerns are board area and > cost. > -- > Nicholas C. Weaver nweaver@cs.berkeley.eduArticle: 58795
It's just a number that differentiates it from a slower and a faster otherwise identical part. Ten years ago, these numbers had some meaning (frequency or prop delay) but we all gave up on that. In most cases, a larger number means faster, but I would check that in the data sheet. Peter Alfke, Xilinx ==================== Terry Andersen wrote: > > Hi NG. > What does the speed grade of a FPGA mean? What does it mean that a FPGA has > a speed grade of -3 ??? > > Best Regards > TerryArticle: 58796
In article news:p682ivc926o9murvj8er0u330bvphmf2jg@4ax.com Allan Herriman wrote: "On Thu, 24 Jul 2003 18:43:58 -0400, rickman <spamgoeshere4@yahoo.com> wrote: >In C programming the compiliers define constants for the date and time >and a lot of other things that are useful information to a program. Do >VHDL synthesis packages do the same thing? No. I did suggest this to the committee a few years ago, but it never got off the ground (probably on the grounds that it would have made VHDL easier to use). >I am looking for an >indication of what tool is being used or what chip is being targeted so >that instantiated components can be tailored for the brand and family of >chip. I am sure I am not the first person to think of this. We do a similar thing here, for similar reasons. [..]" So did Jiri Gaisler for the ERC32. See the LEON source code at HTTP://WWW.Gaisler.com/download.htmlArticle: 58797
> in C > count_val++ > > in VHDL > count_val <= count_val + 1; > You conveniently leave out all of the necessary supporting code required to actually implement your counter. Now let's take a little more complex example (with ALL of required code): int 13 array3d [5][6][3]; // 13 bit wide array of 5*6*3 = 90 integers int 4 i,j,k; // valid 4-bit array indices i = 1; j = 2; k = 3; array3d[i][j][k]++; i++; j--; array3d[i][j][k]--; > It would be interesting to see a comparison of the devices needed to > implement a fairly complex function (SDH/Sonet TU11 -> STM1 device) > when designed in HandelC and an HDL, and the corresponding development > times. Celoxica does have some case studies on their web site: http://www.celoxica.com/technical_library/case_studies/default.asp TomArticle: 58798
The XC3S400 will be in the 6.1i version of Webpack which is scheduled for the end of September. rickman wrote: >I thought this was discussed in a thread here, but I can't find it even >with Google Groups. Anyone have the skinny on what version will support >the XC3S400 and when that is likely to be out? > >Hmmm... maybe I should search my email instead of here. > > >Article: 58799
In 6.1i (coming in September), there are two values that can be set; PACK=CLOSED and PLACE=CLOSED. The PLACE=CLOSED implies PACK=CLOSED to map so the packer also closes the Area Group to all comps not in the same Area Group during packing. For 5.1i, the packer used "CLOSED=PACK" but there was not equivalent placer control. This keeps logic that is not contained in the group from being included in the slice. Steve Aman Gayasen wrote: >Hi, > I am trying to map some modules in my design into different regions >on an >FPGA (XC2V250). I also wish that the AREA_GROUP that is designated for >a particular instance does NOT contain any other logic. > Is there a way to do this? > > I have tried using the AREA_GROUP constraint, but it does not prevent >ungrouped logic from being mapped into the region assigned to an >area-group. > I looked through the Constraints guide that Xilinx provides. It says >that such a behavior can be obtained for modular design flow. Does >that mean I will need to unnecessarily use a modular design flow >(although I have all the module descriptions ready with me, and my >design is not really very big). > > Please tell me if there is a simpler way. > >regards, >Aman > >
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