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Brian Drummond wrote: > > On Tue, 05 Aug 2003 12:18:31 -0400, rickman <spamgoeshere4@yahoo.com> > wrote: > > >Alan Fitch wrote: > >> > >> "rickman" <spamgoeshere4@yahoo.com> wrote in message > > >> > This is the line of code producing the error... > >> > > >> > WaitTime := (ARM_command.RelTime - (now - CurrentTime)); > >> > > > >> It sounds like Modelsim is confused. Is it actually an error, or just > >> a warning? Having a signal read that is not in the sensitivity list > >> is not an error. Can you disable Modelsim's synthesis checks? > > >I am getting the same error from a different assignment now. The common > >point is that a signal is on the right hand side of the assignment and a > >variable is on the left. I am using the variable assignment operator, > >":=". This is reported as an error, not a warning. > > > > Last_Bus_Action := Bus_Command.Bus_Action; > > If that's the case, then assigning the record field to an intermediate > signal would probably "fix" it. Not nice, but as an expedient to (a) > keep moving and (b) home in on the real problem, maybe worth trying. > > -- parallel signal assignment > tempAction <= Bus_Command.Bus_Action; > > -- within process or whatever > Last_Bus_Action := tempAction; > > Assuming it works, then a support call to ModelSim, asking why one > works, but not the other, would be very worthwhile. > > - Brian I already have a work around and have sent the problem to Xilinx (Mentor does not support the Starter Edition). But thanks. -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAXArticle: 59026
Prasanna wrote: > > rickman <spamgoeshere4@yahoo.com> wrote in message news:<3F3079B9.9E9AD29C@yahoo.com>... > > John wrote: > > > > > > Hi all: > > > I have the following verilog codes which shift the serial data to parallel > > > data.But it cost > > > too much LEs in Altera FPGA.Then I want to make it wokes in EAB.I do not > > > what to do.Anybody would help me? > > > > > > reg[31:0] reg_in[7:0],reg_out[7:0]; > > > > > > always @(posedge clk) > > > begin > > > if(reset) > > > cnt8<=0; > > > else > > > if(cnt8==7) > > > begin > > > cnt8<=0; > > > reg_out[0]<=reg_in[0]; > > > reg_out[1]<=reg_in[1]; > > > reg_out[2]<=reg_in[2]; > > > reg_out[3]<=reg_in[3]; > > > reg_out[4]<=reg_in[4]; > > > reg_out[5]<=reg_in[5]; > > > reg_out[6]<=reg_in[6]; > > > reg_out[7]<=reg_in[7]; > > > end > > > else > > > begin > > > cnt8<=cnt8+1; > > > reg_in[0]<=reg_in[1]; > > > reg_in[1]<=reg_in[2]; > > > reg_in[2]<=reg_in[3]; > > > reg_in[3]<=reg_in[4]; > > > reg_in[4]<=reg_in[5]; > > > reg_in[5]<=reg_in[6]; > > > reg_in[6]<=reg_in[7]; > > > reg_in[7]<=data_receive; > > > > > > end > > > end > > > > I don't think an EAB will help you much. This code will use one LAB (8 > > LEs) for the shift register and 3 or 4 more LEs for the counter. The > > shift register can fit in an EAB (but not with the counter), so you will > > save only one LAB for using an EAB. Why do you think this uses too many > > LEs? > > Question... > > Wont you receive valid serial data when cnt8 = 8 ? Your code does not > seem to sample serial data when cnt8 = 8 and just seems to output > parallel data. > > - Prasanna cnt8 will never reaches 8. It counts 0 to 7. But I think you are right in that reg_in will not shift serial data in on cnt8 = 7. It stops shifting and so only 7 serial in samples are ever loaded into reg_in before 8 bits are parallel loaded to reg_out. So reg_out will get 7 new bits and one old bit. This can be changed so that reg_in gets shifted outside of the if statement. Then every clock will shift in and reg_out will get 8 new bits each time. -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAXArticle: 59027
> Corret me if I am wrong, the code is actually converting an 8 bit wide data > input to a 256 wide data output, so it requires much more than 8 LEs. Oops, it should be a 32-bit -> 256 bit conversion. Sorry. Jim Wu jimwu88NOOOOSPAM@yahoo.comArticle: 59028
Jim Wu wrote: > > rickman <spamgoeshere4@yahoo.com> wrote in message > news:3F3079B9.9E9AD29C@yahoo.com... > > > > I don't think an EAB will help you much. This code will use one LAB (8 > > LEs) for the shift register and 3 or 4 more LEs for the counter. The > > shift register can fit in an EAB (but not with the counter), so you will > > save only one LAB for using an EAB. Why do you think this uses too many > > LEs? > > > > -- > > I guess you overlooked the register definition: > > reg[31:0] reg_in[7:0],reg_out[7:0]; > > Corret me if I am wrong, the code is actually converting an 8 bit wide data > input to a 256 wide data output, so it requires much more than 8 LEs. > > Take a look at the link below to see if it helps: > http://www.altera.com/support/software/eda_maxplus2/synplty/intro/logicop.ht > ml I am a bit rusty at VHDL and even rustier at Verilog. Am I correct in saying that this defines 32 - 8 bit shift registers? Regardless, each shift register takes 1 EAB and you still need 8 LEs for each of 32 output registers. Unless you had a lot of EABs or you just did not have the room for the LEs, this is not very practical. It might be possible to use one EAB as all of the shift registers if the sample rate is slow enough that you can time multiplex the RAM between 32 channels. Even if you can't do 32 in one EAB, you can find a multiple rate that the system clock can run compared to the data input rate and use multiple EABs to share the load. Even if you can only run at 4x the data rate, this will bring the EAB count down to 8. I guess this is what the OP may have been thinking about. -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAXArticle: 59029
news@rtrussell.co.uk wrote: > > Jim Granville <jim.granville@designtools.co.nz> wrote: > > : If the fitter has not at this stage reported the Prod terms, you > : could re-target a 9572XL,(just for the purposes of getting > : a complete fitter report!), and then compare with the one below. > > Good idea. However what I tried instead was disabling my > constraints file (which simply determines the pinout). It still > fails to fit, but this time it does report the counts: > > Macrocells used: 36/36 (100%) > Product terms used: 180/180 (100%) > Registers used: 36/36 (100%) > Pins used: 34/34 (100%) > Function block inputs used: 73/108 (67%) > > It then reports "Cannot place signal P<4>". > > This compares with the successful XC9536 report: > > Macrocells used: 36/36 (100%) > Product terms used: 146/180 (81%) > Registers used: 36/36 (100%) > Pins used: 34/34 (100%) > Function block inputs used: 56/72 (77%) > > So the number of product terms has gone from 146 on the XC9536 > to 180 on the XC9536XL and the number of function block inputs > has gone from 56 to 73. > > Does this shed any light ? Is it likely it will ever fit in an > XC9536XL ? A problem here, is it did not fit, and so you do not know if 180 is product terms WANTED, or just the ceiling it bumped into. I can give you the observation 'It's not looking good' :) -jgArticle: 59030
Is there any benefit in terms of power consumption or performance in doing something like the following ? if (a && b) a <= 0; It seems to me it could be re-written as if (b) a <= 0; to save some logic. I think the difference is the 'a' reg would be clocked more often using the second line of code, but does it make a difference if the same (pre-existing) value is written to the register ? Thanks, RobArticle: 59031
A clarification. The Ethernet SGDMA does not work because the driver support in Linux is missing and is currently being added. EMAC SGDMA hardware is available and can be included in designs. - Peter Peter Ryser wrote: > > It sure is! I'm bringing across the PPC kernel drivers into uClinux at > > the moment, and there's some funny stuff going on in there! Some wierd > > hard-coded assumptions about the names given to OPB peripherals, and > > some other crazy things - but the workaround was quite simple. > > I'd be interested to hear what the workaround is. > > > The reason I ask is that if I spend the time to integrate an ethernet > > MAC into the microblaze-uclinux hardware target and get the driver in, > > can I be reasonably confident that the driver itself works properly, and > > that any errors are therefore mine?! :) > > The Ethernet works fine in interrupt driven mode. It doesn't work for SGDMA. > > - PeterArticle: 59032
I am currently using Xilinx Webpack 4.1 on a WinNT (SP6) machine and thinking to upgrade to version 5.2. The web site does not say v5.2 supports WinNT. I was wondering if anyone has tried the latest webpack on WinNT. Thanks JimArticle: 59033
If you write down the truth table, you will see the two equations are not equivalent. Jim Wu jimwu88NOOOOSPAM@yahoo.com Robert Finch <robfinch@sympatico.ca> wrote in message news:mCdYa.3083$_a4.616963@news20.bellglobal.com... > Is there any benefit in terms of power consumption or performance in doing > something like the following ? > > if (a && b) a <= 0; > > It seems to me it could be re-written as > > if (b) a <= 0; > > to save some logic. > > I think the difference is the 'a' reg would be clocked more often using the > second line of code, but does it make a difference if the same > (pre-existing) value is written to the register ? > > Thanks, > Rob > > > >Article: 59034
Hello, In view of the fact that most field programmable gate arrays are designed to accomodate two-level AND-OR expressions how can an FPGA synthesizer benefit from computing both a minimal AND-OR expression and a minimal OR-AND expression and then choosing the one of lower cost? Thanks, NeilArticle: 59035
The classical, so-called SRAM-based FPGAs implement logic in 4-input Look-Up Tables, each with one output, implementing any function of those four inputs. AND and OR are just more primitive ways of expressing logic functionality. That's also why Karnaugh maps have become meaningless. If you can express it as a function of four variables, there is nothing more to do or to be optimized: It fits in one LUT. Peter Alfke ========== Neil Zanella wrote: > > Hello, > > In view of the fact that most field programmable gate arrays are designed to > accomodate two-level AND-OR expressions how can an FPGA synthesizer benefit > from computing both a minimal AND-OR expression and a minimal OR-AND > expression and then choosing the one of lower cost? > > Thanks, > > NeilArticle: 59036
No surprise to me. Some guy out of MIT got a patent for the mechanics of the human arm (actually, any articulation-muscle mechanism on any animal on earth for the last several billion years). Face it, patents are business tools. They have nothing to do with invention any more. Very few things any more are inventions, most are implementations. Most are things that good engineers should be able to produce given a problem and related constraints. Oh well. -- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ Martin Euredjian To send private email: 0_0_0_0_@pacbell.net where "0_0_0_0_" = "martineu" "Jonathan Bromley" <jonathan@doulos.com> wrote in message news:bgoku4$sm6$1$8302bc10@news.demon.co.uk... > "y_p_w" <y_p_w@hotmail.com> wrote in message > news:591da479.0308041524.4ac35381@posting.google.com... > > The URL would be too long. It's patent 6,601,126, and > > is available at <http://patft.uspto.gov/netahtml/srchnum.htm> > > > > This sounds fishy to me > [...] > > > > Here are some of the "claims" of the patent: > [...] > > Sounds an awful lot like the ARM-originated AMBA interconnect > spec, which has been in the public domain for years. > > Nice reinforcement of my prejudices about patent examiners. > -- > Jonathan Bromley, Consultant > > DOULOS - Developing Design Know-how > VHDL * Verilog * SystemC * Perl * Tcl/Tk * Verification * Project Services > > Doulos Ltd. Church Hatch, 22 Market Place, Ringwood, Hampshire, BH24 1AW, UK > Tel: +44 (0)1425 471223 mail: jonathan.bromley@doulos.com > Fax: +44 (0)1425 471573 Web: http://www.doulos.com > > The contents of this message may contain personal views which > are not the views of Doulos Ltd., unless specifically stated. > > >Article: 59037
> If you write down the truth table, you will see the two equations are not
> equivalent.
Ok,
line a b new a
-----------
1 0 0 a (old a)
2 0 1 a (old a)
3 1 0 a (old a)
4 1 1 0 (new value for a=0)
the only time 'a' changes is if both a and b are 1
however, looking at line 2, it is safe to convert the table to the
following:
a b new a
-----------
1 0 0 a (old a)
2 0 1 0 (new value for a=0) - no problem because old value already be zero
3 1 0 a (old a)
4 1 1 0 (new value for a=0)
So regardless of whether or not 'a' is a 1 or a 0, the value of 'a' can be
set to the new value(0) whenever 'b' is 1.
>
> Jim Wu
> jimwu88NOOOOSPAM@yahoo.com
>
> Robert Finch <robfinch@sympatico.ca> wrote in message
> news:mCdYa.3083$_a4.616963@news20.bellglobal.com...
> > Is there any benefit in terms of power consumption or performance in
doing
> > something like the following ?
> >
> > if (a && b) a <= 0;
> >
> > It seems to me it could be re-written as
> >
> > if (b) a <= 0;
> >
> > to save some logic.
> >
> > I think the difference is the 'a' reg would be clocked more often using
> the
> > second line of code, but does it make a difference if the same
> > (pre-existing) value is written to the register ?
> >
> > Thanks,
> > Rob
> >
> >
> >
> >
>
>
Article: 59038Sorry to act as a shill, but I believe the Xilinx Spartan-3 family provides the largest amount of logic with the fewest number of I/O pins. http://www.xilinx.com/spartan3 The smallest package option would be the 100-pin VQFP package. In that package, you get an XC3S200 with up to 3,840 LUT/Flip-Flop pairs plus 216Kbits of block RAM and up to 63 user I/O pins. If you need even more density, the next step up is the 144-pin TQFP package. This time, you get an XC3S400 with up to 7,168 LUT/Flip-Flop pairs plus 288Kbits of black RAM and up to 97 user I/O pins. You can keep moving up to something with up to 66K LUT/Flip-Flop pairs, depending on how big a package that you can tolerate. The next version of WebPack, due out in September provides free support for the XC3S50, the XC3S200, and the XC3S400. The current version only includes the XC3S50. http://www.xilinx.com/xlnx/xil_prodcat_landingpage.jsp?title=ISE+WebPack I couldn't tell exactly, but it looks like you might be interested in an embedded processor as well. Here is a link to embedded processing solutions for Spartan-3 FPGAs, which includes the powerful 32-bit RISC MicroBlaze core or the low-cost, efficient 8-bit PicoBlaze controller core. http://www.xilinx.com/xapp/xapp477.pdf --------------------------------- Steven K. Knapp Applications Manager, Xilinx Inc. Spartan-3/II/IIE FPGAs http://www.xilinx.com/spartan3 --------------------------------- Spartan-3: Make it Your ASIC "Rob Judd" <judd@ob-wan.com> wrote in message news:3F2A4153.66C411AD@ob-wan.com... > Hi, > > My application requires a lot of core but few physical i/o lines. Can > anyone suggest a modern fpga that is delivered in a 68-pin plcc and/or > 80-pin pqfp package? > > Thanks, > > RobArticle: 59039
WebPack 6.1i, due out at the end of September, supports the Spartan-3 XC3S50, XC3S200, and XC3S400. The present version supports just the XC3S50. http://www.xilinx.com/xlnx/xil_prodcat_landingpage.jsp?title=ISE+WebPack --------------------------------- Steven K. Knapp Xilinx Spartan-3/II/IIE FPGAs http://www.xilinx.com/spartan3 --------------------------------- Spartan-3: Make it Your ASIC "rickman" <spamgoeshere4@yahoo.com> wrote in message news:3F29C811.5B21458E@yahoo.com... > I thought this was discussed in a thread here, but I can't find it even > with Google Groups. Anyone have the skinny on what version will support > the XC3S400 and when that is likely to be out? > > Hmmm... maybe I should search my email instead of here. > > -- > > Rick "rickman" Collins > > rick.collins@XYarius.com > Ignore the reply address. To email me use the above address with the XY > removed. > > Arius - A Signal Processing Solutions Company > Specializing in DSP and FPGA design URL http://www.arius.com > 4 King Ave 301-682-7772 Voice > Frederick, MD 21701-3110 301-682-7666 FAXArticle: 59040
WinNT is not supported. Only XP or Win2K. We've tried it on NT, but it does not work. "Jim Wu" <jimwu88NOOOOSPAM@yahoo.com> wrote in message news:QSdYa.15959$mZ6.13063@nwrdny02.gnilink.net... > I am currently using Xilinx Webpack 4.1 on a WinNT (SP6) machine and > thinking to upgrade to version 5.2. The web site does not say v5.2 supports > WinNT. I was wondering if anyone has tried the latest webpack on WinNT. > > Thanks > Jim > >Article: 59041
There isn't much FPGA related in here any more... I'm not sure where this sort of thing gets discussed. I expect the low end micro hackers are good at it. >What do you mean about "Be sure to fixup the broadcast case"? see below >1. Is only the UDP protocol sufficient to be implemented in FPGA for >simple data transfers to the target (FPGA) from the PC? Do I need also >the ARP or other protocols? Yes, you need to answer ARP requests. You can generally fake that when getting started if you hard wire it into the ARP table on the machine you are testing from. You also need DHCP if you don't want to put your IP address into a config file someplace. >2. Which protocols can I miss when the PC knows the 32-bit IP number >of the target? Is a 48-bit ethernet address required? The hardware works on the 48 bit host ID. You could hack around that if you have control of the other end too, but that is abusing Ethernet rather than using it. (Which might be OK if you just need to do a one off hack and don't want to talk to several machines.) >3. Suppose that all UDP packets will also be forwarded through the >router(s) to the target. Does it needs a special attention when only >the UDP is implemented? Will the routers change the IP header (and UDP >header) of the UDP packets before they are arrived at target? The routers will update the hop count. Mostly, they won't touch anything else. (except to fixup the checksum) The trick with simple implementations for UDP over Ethernet is that you don't have to know about routers. When you get a packet, you send the answer back to where you got it. That happens at both the Ethernet layer and at the IP layer. All the info you need is in the headers. >4. Is the connection negotiation required between the PC and the >target? Do you think that the PC will always transfer some UDP packets >without restrictions? The server side of simple UPD protocols doesn't need to save any info. It gets a request packet, looks at a few command bytes (you have to invent this layer of protocol), does what it says (say reads the temperature and puts in into the packet) then fixes up the packet (say changes the packet type from query to response) and sends it back. The send-it-back part involves copying the source field from the packet into the destination. That happens twice - Ethernet/48 bit layer and also at the IP/32 bit layer. Then you put your info into the source fields, fixup a few more header bytes, compute the IP checksum, and send it off. Note that this doesn't know if it's sending back directly or through a router. Except for the broadcast, you could just swap the source/destination fields. The simple/stateless server moves all work of retransmissions and timers back to the other end. If you want to do something a bit more complicated, the next step is probably TFTP/BOOTP. It's often used to fetch boot files over the network. (for example, because you don't have a disk, or you are installing new software) -- The suespammers.org mail server is located in California. So are all my other mailboxes. Please do not send unsolicited bulk e-mail or unsolicited commercial e-mail to my suespammers.org address or any of my other addresses. These are my opinions, not necessarily my employer's. I hate spam.Article: 59042
Take a look at Core Foundry. They specialize in making FPGAs a less expensive solution compared to an ASIC or ASSP. That includes the licensing and small quantities. For example, they can stuff two independent OC48 performance monitors, and do concatenated payload extraction, in the slowest speed grade 1C3 Cyclone part. Qty = 1, that part costs about $17. A single channel ASSP might run you $150 or more, times 2. Plus you use less board space and power. I've talked to them about licensing and they can work in a variety of ways. One of interest was spreading the license "fee" out over some quantity of parts. This gets applied when parts are purchased, so there isn't any up-front fee to burden an engineering budget. It gets tacked onto the BOM like any other component on the board. The fee is qty dependent like any other part, and expires after a predetermined total amount is paid. You can even buy out the license with a lump sum if desired. There seem to be as many ways to license IP as their are vendors. Good luck. "Ken Land" <kland1@neuralog1.com> wrote in message news:vj2cblrm4st563@news.supernews.com... > > Hi, > > This is a high level question about IP Core business models. > I know about the "free" cores at opencores.org and I know you can pay > someone $15,000.00 to license a USB core. > > What I'm looking for are companies that are in the middle whose pricing > competes with dedicated chips. > > For example I need a USB 2.0 port on a project. I can call my NetChip rep > and for $8-$15 (Qty. 30-50) a pop put a USB port in my design. Now for > annual quantities in the low 100's the IP Core's $15,000 startup fee is out > of the question. > > So my question is, are there any IP Core companies that compete with NetChip > (or Cypress etc.) on pricing models? > > Thanks, > Ken > >Article: 59043
The Icarus Verilog -tfpga is gaining generic LPM family support, to be used as a least common demoninator default library. It is of course always nice to test software I write, so I'm on the hunt for tools that read in EDIF netlists that use LPM devices. I'd be highly biased towards Linux software. I have Windows 2000 off to the side here, but it's a chore. Ideally, the software that can read my EDIF/LPM output would be able to in turn emit Verilog that I can use to regression test my code generator and synthesizer. Any suggestions? (I have a feeling Altera and Lattice may support this sort of thing, but I hate IDEs and I *hate* MS Windows.) -- Steve Williams "The woods are lovely, dark and deep. steve at icarus.com But I have promises to keep, http://www.icarus.com and lines to code before I sleep, http://www.picturel.com And lines to code before I sleep."Article: 59044
Hi, I do agree gate counting is a silly work especially when our ASIC group only have function specifications and no RTL codes. They just can say their logic may be ### NAND gates. Unfortunately my boss don't think so, and I have to build whole proto board even before the ASIC group can finish all codes. Anyway, thanks for your kindly comment. It's very helpful to me. Best Regards Jay "Andrew Paule" <lsboogy@qwest.net> ??????:3F3131B9.5050602@qwest.net... > Hi Peter: > > I agree 100% (an RS is the most fundamental valid flop) - and for a D > type you do need two more gates. > I guess that the whole premis here is that there is some talk going > around trying to make an FPGA - ASIC conversion "standard", being able > to count the whatevers in an FPGA and relate that to whatever type of > gate the ASIC manufacturer is doing. Until there is an understnding of > the ASIC type being targeted, and the FPGA type being used to proto, > there cannot be any sort of gate counting relationship, but I don't want > to jerk the poor guys chain too hard. I think that he's been assigned > the task, and is trying to learn some fundamentals, albeit in the wrong > frame. > > Andrew > > Peter Alfke wrote: > > >Andrew Paule wrote: > > > > > >> <snip>Let's say that this is a 2 input nand case - you need two of these for a simple flop, and can build logic accordingly - > >> > >> > > > >Wow, a flip-flop out of two 2-input NANDs ? > >Yes, you can make them into a latch with independenr SET and RESET > >(active Low), but you need 2 more gates to make it a D input, and you > >double the whole thing to get from a latch to a flip-flop. And then > >there is Clock Enable, and perhaps asynchronous CLEAR and/or PRESET, > >plus perhaps Clock inversion. > >You get all that in FPGA flip-flops "for free". > > > >I agree gate count is silly in FPGAs, but let's not distort the argument > >even further. > >Peter Alfke, Xilinx > > > > >Article: 59045
Austin, Great news! R Austin Lesea wrote: > > Rob, > > Even the 2.5V Vccaux parts are 3.3V JTAG compatible (ie Virtex II Pro, > Spartan 3). > > The JTAG inputs are designed to be 3.3V tolerant (special cells), and the > JTAG outputs are open drain, and use external pullup resistors to 3.3V. > The outputs are also special cells (not regular IOBs). > > Austin > > Rob Judd wrote: > > > Hi y'all, > > > > Right, we're making some progress on parts sourcing, thanks in no small > > way to some of you out there who shall remain nameless to avoid > > embarrassment. (Thanks!) > > > > What has come up next is the requirement for a JTAG programmer. I've > > found one here: > > > > http://www.ee.latrobe.edu.au/~djc/PALS/SMALL_PALS.htm > > > > but wonder whether using it on devices only capable of 3v3 or lower may > > kill them. I'm also wondering whether some of the chips I'm considering > > (Actel APA150, Altera EP1C3/EP1C6, Atmel AT94K05, Xilinx > > XC2S200E/XC3S200 and Lattice OR3T80) have particular programming needs > > that make a generic JTAG pod unworkable. If it merely requires level > > translation, I'm golden. > > > > Comments? > > > > RobArticle: 59046
From the 5.0 version, ISE doesn't support Nt. You have to upgrade to Win2000 or Xp if you want to upgrade. Another way is to use Red Hat Linux and wine but I never tried it. I hear that the new release 6.x, that will be available in the end of 2003, support Linux native, but I'm not sure. Regards Giuseppe "Jim Wu" <jimwu88NOOOOSPAM@yahoo.com> ha scritto nel messaggio news:QSdYa.15959$mZ6.13063@nwrdny02.gnilink.net... > I am currently using Xilinx Webpack 4.1 on a WinNT (SP6) machine and > thinking to upgrade to version 5.2. The web site does not say v5.2 supports > WinNT. I was wondering if anyone has tried the latest webpack on WinNT. > > Thanks > Jim > >Article: 59047
When I synthesize the following test code in Webpack 5.1 I get the following warnings. Am I misunderstanding something here? Note that the code below is a silly example as I tried to simplify my actual code to understand the warning by removing parts that don't cause the error. WARNING:Xst:646 - Signal <e> is assigned but never used. WARNING:Xst:646 - Signal <f> is assigned but never used. WARNING:Xst:646 - Signal <g> is assigned but never used. WARNING:Xst:646 - Signal <h> is assigned but never used. module test(a,b,c,d); input [1:0] a, b; output c, d; reg c, d; reg e, f, g, h; always@ (a or b) begin e = a[1]; f = a[0]; g = b[1]; h = b[0]; c = e ^ g; d = f ^ h; end endmoduleArticle: 59048
On Thu, 07 Aug 2003 06:14:05 GMT, "Prasanth Kumar" <lunix@comcast.net> wrote: >When I synthesize the following test code in Webpack 5.1 >I get the following warnings. Am I misunderstanding >something here? Note that the code below is a silly example >as I tried to simplify my actual code to understand the >warning by removing parts that don't cause the error. > >WARNING:Xst:646 - Signal <e> is assigned but never used. >WARNING:Xst:646 - Signal <f> is assigned but never used. >WARNING:Xst:646 - Signal <g> is assigned but never used. >WARNING:Xst:646 - Signal <h> is assigned but never used. > >module test(a,b,c,d); >input [1:0] a, b; >output c, d; > >reg c, d; >reg e, f, g, h; > >always@ (a or b) >begin > e = a[1]; > f = a[0]; > g = b[1]; > h = b[0]; > > c = e ^ g; > d = f ^ h; >end > >endmodule > It's possible that the verilog mapper rewrites the assignments to c & d so that they refer to a & b directly so e, f, g, h are not used to calculate c & d and they are not used any where else either so the warning. Muzaffer Kal http://www.dspia.com ASIC/FPGA design/verification consulting specializing in DSP algorithm implementationsArticle: 59049
I've been debating for several days whether or not to post this message. Well...here it goes, we'll see what develops. I read a disturbing article this last week in Time magazine. It seems to be available online at http://www.time.com/time/magazine/article/0,9171,1101030804-471198,00.html . This article describes the alarming rate at which many types of jobs are being exported to countries such as India, where the work gets done for darn near 1/10th. the cost, or less. Now, before anybody beats me over the head with a digital club, please know that my intention here is to understand the trend and what it might mean in general. As a small business owner facing the need to hire engineers (FPGA/embedded) within the next six to twelve months I have to ask myself if my competitors have exported these jobs? If that were to be the case, competitive forces alone would almost dictate that I (and others in my position) look for offshore solutions. Of course this isn't an issue just in the U.S. I imagine it affects other markets where wages and the cost of living and doing business is higher than for some of the offshore providers. What is interesting and ironic is that some of the technologies that have enabled this (I'm thinking Internet) were invented, funded, deployed and developed by the U.S. Now, improved communications and all related technologies make the all but most barriers to doing business evaporate. The same applies to software, operating systems, tools, etc. That's another issue: software piracy. The widespread offshore availability of very expensive software for virtually nothing is certainly a factor in shifting the business equation in favor of these providers. I've had to pay tens of thousands of dollars for all of my development software and I know that there's someone out there who paid $6 (if at all) for what cost me $10K. A level playing field it is not, by far. Where is this going? I'm all for globalization and economic prosperity at every point on the globe, but there are ways of doing it right and, it seems to me, this isn't one of them. This feels like a nasty big knife cutting our own throats on a daily basis. How do we do this so that everyone wins? And, how does someone like me support his local talent pool without going out of business? -- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ Martin Euredjian To send private email: 0_0_0_0_@pacbell.net where "0_0_0_0_" = "martineu"
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