Custom Search
Site Home Archive Home FAQ Home How to search the Archive How to Navigate the Archive
Compare FPGA features and resources
Threads starting:
Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z
Martin Euredjian wrote: > The constraint guide indicates that the TIG constraint can be used in HDL > (Verilog in my current design). However, an attempt to use it produces the > following error: > > ERROR:Xst:1582 - The constraint 'tig=' is not supported neither in BEGIN > MODEL/END section in the XCF file, nor in HDL code. > > I have not been able to find further information on this error message or > issue in the Xilinx site. Does anyone know if TIG is truly supported in > HDL? I'd hate to place it in the UCF file, to me it feels much more > approprite to have this constraint move with the HDL source. > > The form I'm using is: > > // synthesis attribute TIG of <net_name> is ""; > > As a point of interest, the nets in question are the output of the registers > of a microprocessor interface. The values are only sampled a few times per > second by the receiving module. There is not need to have any of these nets > meet nanosecond level timing constraints as other parts of the design must. > Is there a better approach than "TIG"? Hi Martin, I think this old thread answers your question: http://groups.google.com/groups?threadm=3dbd0daa%241_1%40lon-news.intensive.net Regards, Allan.Article: 59626
"Allan Herriman" wrote: > > The constraint guide indicates that the TIG constraint can be used in HDL > > (Verilog in my current design). However, an attempt to use it produces the > > following error: > > > > ERROR:Xst:1582 - The constraint 'tig=' is not supported neither in BEGIN > > MODEL/END section in the XCF file, nor in HDL code. > > ... > > I think this old thread answers your question: > http://groups.google.com/groups?threadm=3dbd0daa%241_1%40lon-news.intensive.net Thanks, I did see that thread during my search prior to deciding to post. Although the answer might very well be the same, what I'm seeing, I believe, is different. I'm getting an error message that seems to say that "TIG" is not supported in HDL. -- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ Martin Euredjian To send private email: 0_0_0_0_@pacbell.net where "0_0_0_0_" = "martineu"Article: 59627
Hi, I notice that the maximum recommended Virtex2pro Vbatt is 2.63V. Lithium cells put out more than that. What are other designers doing about this? Is the solution as simple as a series Si diode on the Vbatt line? Thanks, Allan.Article: 59628
I see what you mean, off course you can't cover all telcom situations. But it is frustrating to use lots of logic to implement an AUTO-RESET. Let me put it this way - It would have been a nice feature if the DCM could have an "regain lock" option. Do you have a smart way to implement an "AUTO-RESET" function with a minimum of FPGA resources? /HakonArticle: 59629
Hi I am starting to design with Xilinx Spartan family XCS100. Does any know where can I find any esquematic of any evaluation board? My email is: o.alegria@montelec.net Thank you.Article: 59630
Hi, physical synthesis tools for FPGAs are being introduced by a few vendors. Have you read, evaluated or seen a presentation about these tools: Synplicity's Amplify: http://www.synplicity.com/products/amplify/index.html Mentor's Precision: http://www.mentor.com/precisionphysical/ Hier Design's Plan Ahead: http://www.hierdesign.com Do you have any thoughts about what you would be looking for in an FPGA floorplanner from a 3rd party (not the FPGA manufacturer)? Do you use Altera's or Xilinx floorplanner now? Thanks for you input, *** Alfredo.Article: 59631
Hakon, How about an OR gate of the status bits indicating a failure to a flip flop that genreates a one clock long reset pulse? Lots of logic? three gates and a FF or two? The 'Auto-Lock' suggestion is a good one. We will keep that in mind. Austin Hakon Lislebo wrote: > I see what you mean, off course you can't cover all telcom situations. > But it is frustrating to use lots of logic to implement an AUTO-RESET. > Let me put it this way - It would have been a nice feature if the DCM > could have an "regain lock" option. Do you have a smart way to > implement an "AUTO-RESET" function with a minimum of FPGA resources? > /HakonArticle: 59632
But, After you are done, in slave mode, the CCLK pin is an input (still). Austin Antti Lukats wrote: > pablobleyer@hotmail.com (Pablo Bleyer Kocik) wrote in message news:<bb2f07d6.0308242212.6707fd90@posting.google.com>... > > Hello. > > > > I know this has been asked several times before but I am struggling > > to get this straight and I still don't find a definite answer. > > > > I have a Spartan-II device connected to a small 5V micro which does > > the configuration process. I want to multiplex the same micro's pin > > for CCLK generation during Spartan-II configuration and as a timer > > ASFAIK CCLK is dedicated pin that can not be used are user IO at all. > if you need to use the same pin from micro as io to your user logic > in the fpga then you need to connect some regular io pin parallel > to cclk pin. > > anttiArticle: 59633
Allan, Yes, it is as simple as two series 1N914 or 1N4148 diodes (to make sure the voltage is dropped as the current is so low). Austin Allan Herriman wrote: > Hi, > > I notice that the maximum recommended Virtex2pro Vbatt is 2.63V. > Lithium cells put out more than that. > > What are other designers doing about this? > > Is the solution as simple as a series Si diode on the Vbatt line? > > Thanks, > Allan.Article: 59634
"Nagaraj" <nagaraj_c_s@yahoo.com> wrote in message news:91710219.0308242329.6562eaff@posting.google.com... > Hi all, > I am using XST (ISE 5.1i sp3) for my logic synthesis. If I write a > piece of VHDL code as in " c <= a + b ", an N-bit adder will be > inferred (assuming a,b,c are N bits). > As there are many types of adder algorithms/implementations > available (like Carry Look Ahead, Carry Save etc.), I want to know > which one does XST infer? Can I have a control over the type of adder > ? > > Regards, > Nagaraj It will use the ripple carry adder because there are dedicated paths in the Xilinx FPGA to implement a ripple carry chain faster than most other adder algorithms in the general case.Article: 59635
What do you mean by "context switch"? And, CMOS is not slow. We build 10 gigabit/second serial interfaces; and the LUT and flip-flop response is well below 1 ns. Do you call that "slow"? Peter Alfke, Xilinx =========================== Kuan Zhou wrote: > > Hi, > I am wondering how fast can the Virtex does the context switch. > I heard it's slow because the CMOS response very slowly. Is it true? > > Thank you very much! > > sincerely > ------------- > Kuan Zhou > ECSE departmentArticle: 59637
Srisurya, ISE WebPACK does not include CoreGen, so you can't run that tutorial. I'll have to check and see which tutorial you are supposed to run. Steve Srisurya Konduri wrote: >Hi, >I am using ISE webpack 5.2i, I recently downloaded from the web, I am >going through the in-depth tutorial. I am stuck at the point of >generating a core using the core generator. The manual says to open >COREGEN and go into basic elements and then counters but the counters >sub entry is not available. I would really appreciate if you could >help me out in telling me how to add these elements and from where. >Thanks > >Article: 59638
"rickman" <spamgoeshere4@yahoo.com> wrote in message news:3F46E816.96EF198B@yahoo.com... > I am designing a FPGA interface for an MCU which uses only async > strobes. However they are not truely async, in reality the timing to > the clock is simply not spec'd. So if I understand metastability > correctly, I can not use the standard circuit to reduce the failure rate > to insignificant rates. Since there is a fixed relationship between the > clock and the command strobes (even though it is unknown) no matter how > I choose to clock the circuit, I may end up balancing the pencil well > enough on end that I will see a much higher failure rate than predicted > by the standard formula. > > My understanding is that the standard formula assumes that the two > signals are not related in frequency. So the probability that they will > be at the right point to cause a failure depends on the rate of each and > the width of the "failure window". In my case the probability of the > event being in the failure window can be very high if the timing is just > right. > > Other than the obvious of using a separate clock for the FPGA, how can I > design this circuit and get a low enough failure rate? I guess adding > more time will reduce the failure rate, but how do I know how much time > is enough since the standard formula does not apply? The formula assumes independent clocks. What you end up with is an even distribution of edges sampling times across the window. If there's absolutely no noise in your clocks (femtosecond jitter?) and there's no thermal, schottky, or johnson noise in your circuit, you might be able to balance the pencil just on the edge. If you can make a jitter assumption, you might come up with an equivalent "fraction" of the clock period where your sample will be landing. Assuming this window is centered directly at the indecision point, you might get an idea what failure rates to expect from that formula. > In this particular circuit I expect the strobes to change on the rising > edge of the clock at about 50 MHz. Since I know nothing about the > actual relationship between the clock and the strobes, I have picked the > falling edge to clock the strobes into the chip. I assume that if the > outputs change slightly before the clock rising edge, it will not be > much and if they change later, it may be short enough to still give me > close to the 3 ns setup time I need. Then a rising edge FF syncs the > signal to the rest of the circuit and provides some 7 ns (out of 10 ns > clock difference) for settling. If metastability were an issue, every nanosecond you wait to do the second sample in your input register pair is a huge difference in failure rates. Rather than falling edge input, rising edge resample, then about 7ns for settling, consider moving the gap to the front end so all your "settling" takes place there. This way the logic following the second flop can have multiple destinations that are all properly covered by the timing constraints; only the gap between the two flops needs special treatment for settling. > I have no idea how good of an assumption this is. The output delays on > the CPU may be enough to put the strobe edge right in the critical point > to cause a failure. Even if I use an emperical approach and see which > edge to clock on to make the circuit work, I don't know that this will > operate over temperature, process, etc... > > I believe that some of the posts here have indicated that the "failure > window" in terms of time is in the low ps (or was it fs?) range. If my > circuit allows some 7 ns for settling, will this be enough to put the > MTBF above 100 years in a worse case situation? Is it possible to > balance the pencil well enough to make a circuit like this fail > frequently? If you're using Virtex-II, you could use the DCM to nudge the sampling clock by about 50ps increments to try to force some instability into the sampling. You can sample with the 90 degree before and 90 degree after phases to braket the value to figure out when your sampling is on the before side or the after side. > -- > > Rick "rickman" Collins > > rick.collins@XYarius.com > Ignore the reply address. To email me use the above address with the XY > removed. > > Arius - A Signal Processing Solutions Company > Specializing in DSP and FPGA design URL http://www.arius.com > 4 King Ave 301-682-7772 Voice > Frederick, MD 21701-3110 301-682-7666 FAXArticle: 59639
> > pablobleyer@hotmail.com (Pablo Bleyer Kocik) wrote in message news:<bb2f07d6.0308242212.6707fd90@posting.google.com>... > > > Hello. > > > > > > I have a Spartan-II device connected to a small 5V micro which does > > > the configuration process. I want to multiplex the same micro's pin > > > for CCLK generation during Spartan-II configuration and as a timer > > > output to another device after that. The CCLK signal is 5V -- I know I think what's he's asking is whether the FPGA will care if the CCLK line is toggling after configuration - note the phrase "same micro's pin ... output to another device after". AFAIK, This would be no problem - the FPGA ignores CCLK after its DONE goes active so that a chained serial configuration mode works.Article: 59640
Looking at our recent Virtex-IIPro metastability tests, I figured out the metastability capture window: Using a 300 MHz clock, and a roughly 50 MHz data rate, we get one 1.5 ns delay ( that is clock-to-Q plus short routing plus set-up time) per second. And similarily one 2.0 ns delay per million seconds. For the 1.5 ns delay, the capture window is thus 3.3 ns / 50 million = 0.07 femtosecond For the 2.0 ns delay, the capture window is a million times smaller, and for 2.5 ns it's another million times smaller ... Light travels 0.3 m in a ns, 0.3 mm in one ps, and 0.3 micron in one femtosecond. Peter Alfke, Xilinx ApplicationsArticle: 59641
The & is used to allow identifiers to begin with an _ or a number. Make sure your files are purely structural. EDIF2NGD only supports EDIF 2.0.0. What's worse: the error messages can be off by thousands of lines either direction. What's worse than that: the memory efficiency of the tool is terrible. As far as a "conversion tool" is concerned, get the parser from www.edif.org for the 2.0.0 files. Run your code in and out of there. The pretty printed version from that should work better. I have plenty of EDIF files that will work with the EDIF2NGD tool Xilinx ships. Here's an example: (edif Test (edifVersion 2 0 0) (edifLevel 0)(keywordMap (keywordLevel 0))(status(written (timeStamp 2003 5 20 15 25 35)(author "SBS")(program "SBS" (version "Whoopee")))) (library Test (edifLevel 0) (technology (numberDefinition )) (cell GND (cellType GENERIC) (view net (viewType NETLIST) (interface (port G (direction OUTPUT)) (property LEVEL (string "XILINX"))(property LIBVER (string "2.0.0")) ) ) ) (cell VCC (cellType GENERIC) (view net (viewType NETLIST) (interface (port P (direction OUTPUT)) (property LEVEL (string "XILINX"))(property LIBVER (string "2.0.0")) ) ) ) (cell OR2 (cellType GENERIC) (view net (viewType NETLIST) (interface (port I0 (direction INPUT)) (port I1 (direction INPUT)) (port O (direction OUTPUT)) (property LEVEL (string "XILINX"))(property LIBVER (string "2.0.0")) ) ) ) (cell someOr (cellType GENERIC) (view net (viewType NETLIST) (interface (port In1 (direction INPUT)) (port In2 (direction INPUT)) (port Out1 (direction OUTPUT)) ) (contents (instance I234OR2 (viewRef net (cellRef OR2))) (net N1727(joined(portref O(instanceRef I234OR2) ) (portRef Out1))) (net N1728(joined(portref In1 ) (portRef I0(instanceRef I234OR2)))) (net N1729(joined(portref In2 ) (portRef I1(instanceRef I234OR2)))) ) ) ) ) (design Test (cellRef someOr (libraryRef Test))(property PART(string "xc2v6000ff1152-4") (owner "Xilinx")))) "Jon Elson" <jmelson@artsci.wustl.edu> wrote in message news:3F4524C3.2020408@artsci.wustl.edu... > Hello, > > Has anyone had any success with creating schematic pages with other > tools and then getting ise 4.1.03i to accept it (preferably as an edif > file)? > > I'm using Protel 99SE, which has a schematic entry package that I much > prefer to the GHASTLY xst. There are some differences in the way > they like to see schematics, though. Protel insists on ipads and opads, > while ise insists on just having ports on the top level sheet. > > There are some other problems, like Protel puts a '&' before every symbol > and pin name. Well, I just strip them in the editor. Oddly, Protel > makes the > ibuf and obuf parts disappear, so I'm converting the unwanted ipad and opads > to ibuf and obuf. It is close, but not quite there, yet. > > Does anyone know of a freeware solution, have written a converter or > have a procedure of what to do to make the conversion? > > Or, as another possibility, does anyone have a complete EDIF file that > is completely acceptable to ise? (There is exactly one EDIF file in the > entire examples dir, and it is a very complicated design, and not very > good to use as a reference on how to construct a valid edif. > > Thanks much for any help you can offer! > > Jon >Article: 59642
In article <3F4A3E1E.E3A9E335@xilinx.com>, Peter Alfke <peter@xilinx.com> wrote: >Looking at our recent Virtex-IIPro metastability tests, I figured out >the metastability capture window: >Using a 300 MHz clock, and a roughly 50 MHz data rate, we get one 1.5 ns >delay ( that is clock-to-Q plus short routing plus set-up time) per >second. And similarily one 2.0 ns delay per million seconds. Does this mean that, thanks to routing delay, you could just do a 3 flip-flops in parallel for capturing, voting circuit on the other side, and not have to worry about it? >For the 1.5 ns delay, the capture window is thus 3.3 ns / 50 million = >0.07 femtosecond >For the 2.0 ns delay, the capture window is a million times smaller, >and for 2.5 ns it's another million times smaller ... > >Light travels 0.3 m in a ns, 0.3 mm in one ps, and 0.3 micron in one >femtosecond. > >Peter Alfke, Xilinx Applications -- Nicholas C. Weaver nweaver@cs.berkeley.eduArticle: 59643
The Physical synthesis and SVP tools from 3rd parties are not just mere Floorplanners. In a nutshell, Amplify and Precision Physical do something called "Placement Aware Synthesis", which is the most important thing to do to bring down the routing delays...whereas SVP tools like the one from Hier help provide final representation of the PLD design early in the design stage. Floorplanning is just one of the many features built into these tools, though an important one, to help achieve performance goals and reducing the compile time of the design by working closely with the P&R tools... Feel free to correct me if I am wrong... --Neeraj "Alfredo" <alherrer@nortelnetworks.com> wrote in message news:bid6ib$mfa$1@zcars0v6.ca.nortel.com... > Hi, > physical synthesis tools for FPGAs are being introduced by a few vendors. Have > you read, evaluated or seen a presentation about these tools: > Synplicity's Amplify: http://www.synplicity.com/products/amplify/index.html > Mentor's Precision: http://www.mentor.com/precisionphysical/ > Hier Design's Plan Ahead: http://www.hierdesign.com > > Do you have any thoughts about what you would be looking for in an FPGA > floorplanner from a 3rd party (not the FPGA manufacturer)? > > Do you use Altera's or Xilinx floorplanner now? > > Thanks for you input, > > *** > Alfredo. > >Article: 59644
Sounds reasonable to me... Peter Alfke "Nicholas C. Weaver" wrote: > Does this mean that, thanks to routing delay, you could just do a 3 > flip-flops in parallel for capturing, voting circuit on the other > side, and not have to worry about it? > > >For the 1.5 ns delay, the capture window is thus 3.3 ns / 50 million = > >0.07 femtosecond > >For the 2.0 ns delay, the capture window is a million times smaller, > >and for 2.5 ns it's another million times smaller ... > > > >Light travels 0.3 m in a ns, 0.3 mm in one ps, and 0.3 micron in one > >femtosecond. > > > >Peter Alfke, Xilinx Applications > > -- > Nicholas C. Weaver nweaver@cs.berkeley.eduArticle: 59645
In article <3F4A4A96.18037049@xilinx.com>, Peter Alfke <peter@xilinx.com> wrote: >Sounds reasonable to me... >Peter Alfke Just realized. How does a LUT input react to a metastable input (to do the voting circuit)? -- Nicholas C. Weaver nweaver@cs.berkeley.eduArticle: 59646
Thanks Neeraj, I have some notion of the benefits of these tools but I do not fully understand how to differentiate them and how to choose one for a specific task: which one is better for IP immersion, which one help manage better for stitching blocs at the top level (modular design), which one interfaces better with STA tools for timing closure, ... I think I'll need to run some testbenches to get a good grasp on these tools and how to better use them. Does anyone have a book or documetation that I can read to learn more about this subject? The only documentation I have now is what the vendors are providing. Thanks, *** Alfredo. "Neeraj Varma" <neeraj@cg-coreel.com> wrote in message news:bidh5u$8762p$1@ID-159439.news.uni-berlin.de... > The Physical synthesis and SVP tools from 3rd parties are not just mere > Floorplanners. In a nutshell, Amplify and Precision Physical do something > called "Placement Aware Synthesis", which is the most important thing to do > to bring down the routing delays...whereas SVP tools like the one from Hier > help provide final representation of the PLD design early in the design > stage. > > Floorplanning is just one of the many features built into these tools, > though an important one, to help achieve performance goals and reducing the > compile time of the design by working closely with the P&R tools... > > Feel free to correct me if I am wrong... > > --Neeraj > > > > > > > > > > "Alfredo" <alherrer@nortelnetworks.com> wrote in message > news:bid6ib$mfa$1@zcars0v6.ca.nortel.com... > > Hi, > > physical synthesis tools for FPGAs are being introduced by a few vendors. > Have > > you read, evaluated or seen a presentation about these tools: > > Synplicity's Amplify: > http://www.synplicity.com/products/amplify/index.html > > Mentor's Precision: http://www.mentor.com/precisionphysical/ > > Hier Design's Plan Ahead: http://www.hierdesign.com > > > > Do you have any thoughts about what you would be looking for in an FPGA > > floorplanner from a 3rd party (not the FPGA manufacturer)? > > > > Do you use Altera's or Xilinx floorplanner now? > > > > Thanks for you input, > > > > *** > > Alfredo. > > > > > >Article: 59647
Peter Alfke <peter@xilinx.com> wrote: : What do you mean by "context switch"? Probably he meant the time needed for reprogramming... -- Uwe Bonnes bon@elektron.ikp.physik.tu-darmstadt.de Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt --------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------Article: 59648
Brannon King wrote: >The & is used to allow identifiers to begin with an _ or a number. > My problem is more with Protel than Xilinx ISE. Protel's pld software is so broken that I don't even know where to start. For instance, I put in a 16-bit shift register, and all that comes out in the EDIF file are the Q outputs of the FFs. No clock, data in or anything else show up. Fortunately, their basic schematic code works better, and the right stuff comes out, but there's extra junk, and some really inconsistent stuff. > Make sure >your files are purely structural. EDIF2NGD only supports EDIF 2.0.0. What's >worse: the error messages can be off by thousands of lines either direction. > Yes, but the net names and such pretty quickly bring you to the trouble spot. >What's worse than that: the memory efficiency of the tool is terrible. As >far as a "conversion tool" is concerned, get the parser from www.edif.org >for the 2.0.0 files. Run your code in and out of there. The pretty printed >version from that should work better. > I had planned on checking this as a base when I got to the point of making a converter program, but didn't think of using it as is to clean up the EDIF. Thanks! > I have plenty of EDIF files that will >work with the EDIF2NGD tool Xilinx ships. Here's an example: > > > Thanks for the example! I think I have the EDIF format that Xilinx needs pretty well figured out, now. JonArticle: 59649
On Mon, 25 Aug 2003 18:25:30 +0000 (UTC), nweaver@ribbit.CS.Berkeley.EDU (Nicholas C. Weaver) wrote: >In article <3F4A4A96.18037049@xilinx.com>, >Peter Alfke <peter@xilinx.com> wrote: >>Sounds reasonable to me... >>Peter Alfke > >Just realized. How does a LUT input react to a metastable input (to >do the voting circuit)? Voting circuits don't work as a metastability cure. Imagine a 2-out-of-3 circuit that's looking at three flip-flops. If one FF is HIGH, another is LOW, and the third is metastable, what's the output of the voting circuit? Back in the early 80's, UCSD professor Leonard Marino wrote a paper in which he very thoroughly analyzed a number of alleged metastability cures, one of which was the voting circuit. I can't find my copy of the paper, but it must have appeared in IEEE Transactions on Computers. Bob Perlman Cambrian Design Works
Site Home Archive Home FAQ Home How to search the Archive How to Navigate the Archive
Compare FPGA features and resources
Threads starting:
Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z