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"Richard Iachetta" <iachetta@us.ibm.com> wrote in message news:MPG.19b83b577df3e40d989823@ausnews.austin.ibm.com... > In article <rzt3b.288788$uu5.63948@sccrnsc04>, gah@ugcs.caltech.edu says... > > I used to hear stories, though I am not sure that I believe them, of people > > seeing metastability effects on the PDP-10 (KA10), which used self timed > > logic. Supposedly they could see it stop processing, and then start again > > with no ill effect. How they know it wasn't in I/O wait, or some other such > > state, I have no idea. > > Sorry for being skeptical, but they "saw" it stop processing for approximately > 10 to 100 ns that the metastability would resolve and then they saw it start > again? Well, I am skeptical, too, but logic was somewhat slower in those days, and the resolving time may be much longer. Not that logic speed and resolution time are proportional. Also, the metastability pathways in self-timed logic are somewhat different. -- glenArticle: 59826
I used to do some early xilinx and amd mach parts in abel - too far in the neither regions of my brain to remember if this was before I started down the view logic xilinx path - ain't verilog grand. Other thing to do might be to grep around for the old source files, but, alas, I would suspect this has already been done. If tis is still the case (no jed2abl, no source) call xilinx - the rep in your area, not the disti - they might be abel (he he) to help. Andrew Mark Moyer wrote: >JEDEC files are very device and architecture specific. It is very >unlikely that jed2abl would support anything more than the 22V10 or >16V8 type of devices. If Data I/O, the original authors of ABEL, >supported the XC9536 then you might have a shot. If not, then you >will have to go to Xilinx and I don't think the programmable logic >companies like to give out JEDEC disassembelers, even if they have >them > >Andrew Paule <lsboogy@qwest.net> wrote in message news:<zp63b.37$ib4.39820@news.uswest.net>... > > >>see if you can find jed2abl around - many of the abel compilers had this >>feature - converted jedec files to abel code >> >>Andrew >> >>yusuke wrote: >> >> >> >>>Hi, >>>Is it possible to convert jedec to logical equations? I've got a jed >>>file for a xilinx cpld(XC9536xl) and I'm trying to recover a job done >>>a long time ago. Or, is it possible to discover the pinout based on >>>the jed file? This would be quite useful too. >>> >>>Thanks in advance, >>>yusuke >>>PS: Sorry for my poor English skills. >>> >>> >>> >>>Article: 59827
Ahah - DataIO sold the rights to ABEL to Xilinx - and XAPP075 gives notes about how to use abel for the cpld's of the time - now part of the XABEL interface in foundation - also includes a jed to abel conversion utility. Just run your jed files into the webpack if that's what you run. Andrew Andrew Paule wrote: > I used to do some early xilinx and amd mach parts in abel - too far in > the neither regions of my brain to remember if this was before I > started down the view logic xilinx path - ain't verilog grand. Other > thing to do might be to grep around for the old source files, but, > alas, I would suspect this has already been done. If tis is still the > case (no jed2abl, no source) call xilinx - the rep in your area, not > the disti - they might be abel (he he) to help. > > Andrew > > Mark Moyer wrote: > >> JEDEC files are very device and architecture specific. It is very >> unlikely that jed2abl would support anything more than the 22V10 or >> 16V8 type of devices. If Data I/O, the original authors of ABEL, >> supported the XC9536 then you might have a shot. If not, then you >> will have to go to Xilinx and I don't think the programmable logic >> companies like to give out JEDEC disassembelers, even if they have >> them >> >> Andrew Paule <lsboogy@qwest.net> wrote in message >> news:<zp63b.37$ib4.39820@news.uswest.net>... >> >> >>> see if you can find jed2abl around - many of the abel compilers had >>> this feature - converted jedec files to abel code >>> >>> Andrew >>> >>> yusuke wrote: >>> >>> >>> >>>> Hi, >>>> Is it possible to convert jedec to logical equations? I've got a jed >>>> file for a xilinx cpld(XC9536xl) and I'm trying to recover a job done >>>> a long time ago. Or, is it possible to discover the pinout based on >>>> the jed file? This would be quite useful too. >>>> >>>> Thanks in advance, >>>> yusuke >>>> PS: Sorry for my poor English skills. >>>> >>>> >>>> >>> >Article: 59828
Acutally Lattice does have parts larger that the XCR3512XL. If you are looking for 256 fpBGA you can get up 768 macrocells in that package using their ispXPLD family. Not only that but each logic block can alternately be made into a large memory element so you will have plenty of room to spare. "Neeraj Varma" <neerajNOSPAMM@cg-coreel.com> wrote in message news:<3f2dc715@shknews01>... > Cypress is anyway getting out of the PLD business... > http://www.eet.com/semi/news/OEG20030730S0063 > > > "rickman" <spamgoeshere4@yahoo.com> wrote in message > news:3F2A84FE.20106575@yahoo.com... > > Marc Randolph wrote: > > > > > > rickman <spamgoeshere4@yahoo.com> wrote in message > news:<3F29C212.EC74896B@yahoo.com>... > > > > I have been given a very good price on the Coolrunner XCR3512XL, but > > > > even with 512 macrocells, including small FIFOs (8 bits x 16 words, > two > > > > FIFOs) uses up half the chip. > > > ^^^^^^^^^^^^^ > > > Unless the design is complete and you can verify that it fits AND you > > > have a pinout, this would scare the hell out of me. I have to admit > > > not having used the Coolrunnner, but over the past six years, we have > > > had an absolutely horrible time making very minor changes to > > > moderately full 95xxx series Xilinx CPLD's. Again, this may not apply > > > as much to the Coolrunner, since it is a completely different family - > > > but I'd still verify it first. > > > > > > I agree with the other poster - what about the Cypress or Lattice > > > devices? I realize that gets you away from your "all Xilinx" board, > > > but is there really a good reason for desiring that (except maybe you > > > can get all parts from one distributor)? > > > > No, sticking with Xilinx is not a strong desire since the software is > > not common anyway. But Lattice has nothing that will fit this socket > > and I have not been able to get a decent price on a Cypress part. I > > guess that is also part of my goal to use Xilinx. I have gotten some > > really great pricing on the parts I have discussed with them. They are > > working with me, so it makes me want to work with them. > > > > But I agree that using the XCR3512XL is scaring me as well. That is why > > I am asking about other Xilinx alternatives. > > > > I am sure I looked at the Cypress parts. I need about 170+ IOs in a 256 > > FBGA. The insides are not real important since that many IOs almost > > always means a larger part than what I need, say 20,000 gates or 1000 > > LUT/FF. The memory is optional since with that many FFs I can make my > > own FIFOs easily. Any idea of what a real price in a Cypress part would > > run? I don't really see much that will fit the socket unless I am > > missing something. > > > > -- > > > > Rick "rickman" Collins > > > > rick.collins@XYarius.com > > Ignore the reply address. To email me use the above address with the XY > > removed. > > > > Arius - A Signal Processing Solutions Company > > Specializing in DSP and FPGA design URL http://www.arius.com > > 4 King Ave 301-682-7772 Voice > > Frederick, MD 21701-3110 301-682-7666 FAXArticle: 59829
> John Lee wrote: > > > > Hi all, > > > > What is the price for a maximux of 50K system gates, IO counts is not > > an issue, with more than 100K volumn per year? We look at cyclone and > > spartan series because Xilinx and Altera claimed they are cheap. > > 100K is the minimum. 1) ask the disties for pricing, well for 100K they probably need to contact the factory anyway. 2) you may also ask for Actel for APA075 it has nonvolatile config so you probably save on the configuration. one off price for APA075 what I have seen is 17 EUR, and I think I did see a price estimate for smallest ProAsicPlus (eg APA075) to be around $7 I guess the smallest spartan III and cyclone devices should also come down below 10$ but then S3-50 does not have BRAM and both Spartan and Cyclone do require config memory to be present what may add significant amount to the final price (both money as board estate, etc) anttiArticle: 59830
"Christos" <chris_saturnNOSPAM@hotmail.com> wrote in message news:<bil9f7$4o2$1@sunnews.cern.ch>... > The sum or average of a certain number of samples (for ex. the last 100 > values received) have to be checked constantly against a threshold. Do you require that each of the previously recieved values are considered equally in the average calculation? If you can assume that the current samples are more important than those recieved a long time ago then you can calculate an "average" via an exponentially weighted moving average filter. Or in other words, us a 1st-order LPF. a_k = (1/(n+1))*s_k + (n/(n+1))*a_k-1 where: s_k = sample input at instant k, n = number of samples in moving-average window, a_k = average at instant k, and a_k-1 = average at instant k-1 As you can see this is quite easy to implement, requiring to multiplies, one addition, and one register for a_k-1 storage. If you choose n+1 do be a power of two then one of the multiplications (or I guess it is a divide) becomes a simple shift operation. -Jack StoneArticle: 59831
Robert Abiad wrote: > > Hello, > > I'm wondering if anyone wants to offer up their opinion of Mentor's HDL > Designer series or FPGA Advantage (Designer + simulation&synthesis)? I > recently acquired it, but am wondering about the quality of the > resulting code. It looks like it might be very easy to produce stuff > with it, but does it save time coding in the end? > > Thanks, > -robert > Hi Robert, I am a HDL user from 4 years. Now, I cannot do design without HDL. From CPLD design to big Virtex-II, HDL is the best I found. Yes you can continue to write your complet VHDL in text in your favorite Text Editor, but do you know the hours for the documentation ? With HDL designer, the documentation is automatic when you designing, the documentation is ready to send to your customers (in html treeview or other format). Maybe, the winners of the next year will be in the reuse design methodology. HDL is, for me, the first KEY. Regards, Laurent Gauch www.amontec.comArticle: 59832
I've been learning to use it for a month or so.. and I think the suggestion below is rather limited in its thought. HDL designer is an good tool for maintaining the libraries and (now) working with VHDL projects. It gives a graphical representation of VHDL code and allows the entry of state diagrams, flow diagrams as well as block diagrams (schematics). Add a third party editor like code-writer, and you get a good VHDL entry tool that is integrated into HDL.. then add modelsim and you've got a good simulator.. and Leonardo or precision and you've got VHDL (and verilog?) compile and simulate. We actually went the simplicity / VHDL way as its supposed to be a better tool.. but I think that's the guy who 'evaluated' the software's decision as his preference. I've not noticed a lot of bugs in HDL designer but it does have a few.. it can be a bit of a pig to set up too.. This has to be the case as we have a company policy of not installing it to its default directory.. I think it doesn't like spaces in names.. such as "program files" .. but then again .. I can only go by how I was told to set it up. The editor isn't too bad but is not company policy so It only gets used when HDL hides files with bugs in them.. hear no evil .. see no evil I think. The text editor really doesn't like you editing a file outside it when the text editor is open thou.. killed HDL twice today doing that :-) It also integrates with visual source safe but hopefully with others cause using VSS from within HDL designer runs like a dog with no legs. I've been told this is VSS's fault not HDL designer.. but everybody blames Microsoft Modelsim is an expensive piece of crappy software full of bugs that I couldn't live without. It certainly speeds up the design process even if it crashes 3-4 times a day. I'm sure someone who knows it better will correct me where I'm wrong.. or mislead .. but no flames please :-) Simon "Mike Treseler" <mike.treseler@flukenetworks.com> wrote in message news:3F4E6D87.6050705@flukenetworks.com... > > > Robert Abiad wrote: > > > > Hello, > > > > I'm wondering if anyone wants to offer up their opinion of Mentor's HDL > > Designer series or FPGA Advantage (Designer + simulation&synthesis)? I > > recently acquired it, but am wondering about the quality of the > > resulting code. It looks like it might be very easy to produce stuff > > with it, but does it save time coding in the end? > > > It may be usefully for a schematic oriented designer or > someone learning an hdl. > > Once you learn an hdl, you may prefer your own > text editor without all the graphical overhead. > > > -- Mike Treseler >Article: 59833
Antti Lukats <antti@case2000.com> wrote: : I guess the smallest spartan III and cyclone devices should also come down : below 10$ but then S3-50 does not have BRAM and both Spartan and Cyclone : do require config memory to be present what may add significant amount to : the final price (both money as board estate, etc) XC3S50 _will_ have BRAM, only the first batch didn't have. Bye -- Uwe Bonnes bon@elektron.ikp.physik.tu-darmstadt.de Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt --------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------Article: 59834
Peter Alfke <peter@xilinx.com> wrote: : Click at : http://www.xilinx.com/xcell/xl24/xl24_20.pdf : This circuit allows totally asynchronous selection between two clock sources. : But remember: both clock must be wiggling (however slowly). You cannot : use this circuit to enable/disable a clock, which is actually a far : simpler problem. : The BUFGMUX in Virtex is not quite this clever, it has a set-up time : requirement on the S control input. :-( Peter, what happens if this setup time is violated? Will the BUFGMUX stall (no more output clock until some reset), will it produce a runt ( some clock pulse smaller than any of both input clocks) or will it switch clocks only delayed? I didn't find anything in the datasheet. Nye -- Uwe Bonnes bon@elektron.ikp.physik.tu-darmstadt.de Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt --------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------Article: 59835
Hi, A moving average (which is slightly different from a moving sum) can be implemented as e.g. in RFC 2960, page 74. In a moving sum, all entries have the same significance, while in a moving average, the older entries have less significance the newer entries (which is what you really want in most cases). If you get a new entry (aka sample), then the new moving average is computed from the old moving average and the new sample: new_ave = alpha*old_ave + (1 - alpha)*new_sample alpha is between 0.5 and 1; the closer it is to 1, the slower the moving average changes, which has the effect of a long FIFO in your example. Of course, you dont want to really multiply by alpha, but instead choose alpha = 1 - 2**-k for some integer k (** meaning to the power of): new_ave = old_ave - (old_ave >> k) + (new_sample >> k). Hence, 2 adders plus a register for storing the average will suffice. Kind Regards, JuergenArticle: 59836
Initializing the whole mess must also be considered. While the starting sum can be zero, all the values in memory must be preset to zero and the comparison to a threshold must be declared invalid until 'n' new values have been accumulated. -- Greg readgc.invalid@hotmail.com.invalid (Remove the '.invalid' twice to send Email) "Christos" <chris_saturnNOSPAM@hotmail.com> wrote in message news:bil9f7$4o2$1@sunnews.cern.ch... > Hi to all, > > > > The sum or average of a certain number of samples (for ex. the last 100 > values received) have to be checked constantly against a threshold. > > > > I thought of implementing this by keeping a "Moving Sum" which will work by > adding the new value and subtracting the oldest. I think that can be > implemented by adding to a register the value just arriving and subtracting > the value coming out of an 100 word deep shift register. > > > > Now, if a longer sum has to be checked then there is a memory problem > because a lot of values have to be stored. In addition more than one "Moving > Sums" is needed so if I use the above implementation I will have in addition > to store the same data more than once (for ex. the 1000 word Shift Register > will include the 100 word S.R. data). > > > > Any idea of how this could be implemented? > > > > The final system will have to keep 10 moving sums with the largest being > 250,000 (8-bit) values for each of the 16 independent input channels. > > > > Help to the design problem will be appreciated and acknowledged. > > > Christos > > __________________________________________________ > > Christos Zamantzas > CERN, European Organization for Nuclear Research > Div. AB/BDI/BL tel: +41 22 767 3409 > CH-1211 Geneva 23 fax: +41 22 767 9560 > Switzerland christos.zamantzas@cern.ch > __________________________________________________ > >Article: 59837
Yes I use a 2V40 in that application (155Mb clock data switch/mux), and I have not found a simple way to multiplex the clock quality logic. We ended up with a combination of SW logic and HW logic for supervising of the DCM's. It works, but the SW guys dont like the extra lines of code! A picoBlaze is interesting for my next project, I'll take a deeper look at that one. Thank you for the conversation! Hakon Lislebo "Austin Lesea" <Austin.Lesea@xilinx.com> wrote in message news:3F4B78A5.6E3FEED8@xilinx.com... > Håkon, > > Well, sounds like you really do have a demanding application, and it therefore > it needs a well thought out and debugged solution. I would hate to try to match > our system design skills with yours (and get it wrong) so the cheapest and best > way to address thius is still using LUTs, SRL16s, and FFs. > > And what are you using, a 2V40? We are still talking about less than a few > hundred CLB's, which is a tiny number in a 2V1000 or larger. If it is a 2V40, > or a 2V80, I can see your point, as it might get a bit crowded. > > Is it possible to multiplex your clock quality logic among multiple DCMs? Sort > of a reset controller? Or use a picoBlaze to control all DCM resets? It is not > a function that needs the speed of the fabric, so one can replace it with > software, and a soft controller core like the picoBlaze. Might be an > advantageos trade-off. > > AustinArticle: 59838
Hi Antti, > 2) you may also ask for Actel for APA075 it has nonvolatile config so > you probably save on the configuration. one off price for APA075 what > I have seen is 17 EUR, and I think I did see a price estimate for smallest > ProAsicPlus (eg APA075) to be around $7 > Have you used the Actel FPGAs? Are there free tools? Can the flash also be used to store additional data? Looks like a good candidate for a soft core cpu (as for JOP :-) Martin ---------------------------------------------- JOP - a Java Processor core for FPGAs: http://www.jopdesign.com/Article: 59839
I have used FPGAdvantage for the past 2-3 years and despite some bugs that all SW systems have, I am very satisfied. I use block diagrams for the hierarchy only and use HDL text files edited in emacs for all behavioural code. The biggest problems with HDL text files only designs are to understand how all components is connected together. So the graphical block diagram is a very good way to navigate in the design. The code generated from block diagrams is ok, but a few colleagues have struggled with crappy code generated from state-machine diagrams and flow charts. Use them with care! We have integrated HDL designer with ClearCase and that works well. I have also struggled a bit with bugs in the interfacing between HDL designer and the synthesis tool. Now I start the synthesis tool stand-alone with my own scripts. ModelSim works fine though. When you learn have to use FPGAdvantage and how you should not use it, you will be satisfied! Hakon Lislebo "Robert Abiad" <abiad@ssl.berkeley.deletethisandaddedu> wrote in message news:3F4E6463.5030207@ssl.berkeley.deletethisandaddedu... > > Hello, > > I'm wondering if anyone wants to offer up their opinion of Mentor's HDL Designer > series or FPGA Advantage (Designer + simulation&synthesis)? I recently acquired > it, but am wondering about the quality of the resulting code. It looks like it > might be very easy to produce stuff with it, but does it save time coding in the > end? > > Thanks, > -robert >Article: 59840
Hi all, I have a problem. While trying to install old Xilinx Foundation Series F2.1i on Windows 2000, just at the beginning of installation I got the message: "The exception unknown software exception (0xe06d7363)occured in the application at location 0x77eab2f0". and the installation is ending. I know that this version of Xilinx enviroment was not designed for the Win2k but I saw once that one guy had it working on Win2k (I don't know how they done this on Win2k and don't have the contact with this people). Also I know, that Xilinx uses Java for installation. So I've tried to install Java Development kit v.1.1.8 but it doesn't helped. Do you know of any solutions for this, how to install this version on Win2k ??? Regards SebastianArticle: 59841
"Nicholas C. Weaver" <nweaver@ribbit.CS.Berkeley.EDU> wrote in message > > Can you cheat? That is, instead of having a 250,000 deep moving sum, > have it be 250,000 deep but only at intervals of every 1000 samples? I have thought also of this but the idea was rejected as it increases the total system error. In order to make an interval you have to wait to receive all of its samples before you add the interval to the sum. Thus, you update the sum slower which increases the system error. For a similar reason it is not possible to use a Low-Pass Filter. I guess to have an average of the 250,000 values you need as many taps. > > The other option is once you have to go off-chip for memory for the > FIFO's, the size doesn't matter much because you can easily just throw > ~1GB of DRAM on the other side. A sync. SRAM (probably 2Mx36b) will be available to the board. I have been calculating and I think that it is enough. ---------------------------------------------------------------------------- --- "Ray Andraka" <ray@andraka.com> wrote in message news:3F4E55BB.FC8A993A@andraka.com... > Look for "CIC filter". CIC is a Cascaded integrator Comb filter. It is a > recursive implementation of a moving sum. I have never heard of the CIC filter I will investigate. > For the depth you are looking at, you'll need to use off chip memory > for the storage (you might fit it into the bulk storage on an Altera Stratix). > You did not mention the sample rate. If the data rate is sufficiently low, you > can time multiplex the data in/out of the external memory so that you can trade > memory width for depth, which might get you a lower parts count. The FPGA will be a Stratix, the sample rate is slow enough: 25 KHz (acquisition every 40us) and external SRAM. The data are already received multiplexed, but I don't get why it is better storing with larger width than depth. Probably because I have no idea how to implement the Sratix - SRAM communication. Any Ap.Note or book? Thanks a lot to all, ChristosArticle: 59842
Håkon Lislebø <hakon.lislebo@ericsson.no> wrote in message news:bin51p$7k$1@newstree.wise.edt.ericsson.se... > I have used FPGAdvantage for the past 2-3 years and despite some bugs that > all SW systems have, I am very satisfied. > I use block diagrams for the hierarchy only and use HDL text files edited in > emacs for all behavioural code. The biggest problems with HDL text files > only designs are to understand how all components is connected together. So > the graphical block diagram is a very good way to navigate in the design. > > > Hakon Lislebo Hakon, If just using the tool for top level block diagrams does it offer any advantages over a top level schematic in Quartus (Altera's tool)? The automatically generated documentation in HTML as mentioned in another post sounds useful. If you do generate code from state machine diagrams etc does it comment the resulting source code at all? Nial Stewart ------------------------------------------------ Nial Stewart Developments Ltd FPGA and High Speed Digital Design www.nialstewartdevelopments.co.ukArticle: 59843
"Seba" <sduszyk@poczta.fm> ha scritto nel messaggio news:bin8b4$dhm$1@atlantis.news.tpi.pl... > Also I know, that Xilinx uses Java for installation. So > I've tried to > install Java Development kit v.1.1.8 but it doesn't > helped. There is a know problem with the Java runtime environment shipped with foundation 2.1i and Pentium 4. It doesn't matter if you install a newer version of JRE, since the Xilinx installer uses its own copy on the CD. I remember I managed to install foundation 2.1i on a Pentium 4 by changing the JRE directly on the Xilinx installation CD (i.e. copy all of the contents of CD into another CD but with another version of JRE). I tried various versions, it worked only with one (not the newest one, maybe it was the first version with the P4 bug fixed). -- LorenzoArticle: 59844
Hi All,
I need help regarding use of configuration in vhdl. In my design,
one entity has got multiple architectures. Through Configuration I am trying to bind a partcular architecture. But it seems that it always taking the last compiled architecture and doing default binding. I am using cadence NCSIM SIMULATOR.
where the problem might be? If anyone has used Ncvhdl/ncelab can you tell me whether I need to set a flag for using this configuration?
Sudip Saha.
Article: 59845Hi, I'm using ISE 5.2.03, using XST Verilog flow. I can't turn keep_hierarchy on in the Project Manager. There is no field to do so in the Process - Properties - Synthesis Options dialog (which is where the documentation says it should be). My problem is that my RLOCs don't work because XST flattens the hierarchy and puts all my macros into the one HSET! I would like to try with keep_hierarchy on, but the *&(#$% GUI won't let me. Help! Allan.Article: 59846
thanks a lot, finally I got something interesting about this. It would be great if I knew what version of java works with this soft. Maybe you could remember ??? If so, please let me know. Thanks once again - I will do some experiments about this. regards "Lorenzo" <lorenzol@despammed.com> wrote in message news:binf91$b7g26$1@ID-202895.news.uni-berlin.de... > "Seba" <sduszyk@poczta.fm> ha scritto nel messaggio > news:bin8b4$dhm$1@atlantis.news.tpi.pl... > > > Also I know, that Xilinx uses Java for installation. So > > I've tried to > > install Java Development kit v.1.1.8 but it doesn't > > helped. > > There is a know problem with the Java runtime environment shipped with > foundation 2.1i and Pentium 4. It doesn't matter if you install a newer > version of JRE, since the Xilinx installer uses its own copy on the CD. I > remember I managed to install foundation 2.1i on a Pentium 4 by changing the > JRE directly on the Xilinx installation CD (i.e. copy all of the contents of > CD into another CD but with another version of JRE). I tried various > versions, it worked only with one (not the newest one, maybe it was the > first version with the P4 bug fixed). > > -- > Lorenzo > >Article: 59847
Hi Allan under "edit->preferences->process" you can switch to "advanced property mode" than you can change it happy coding stefan "Allan Herriman" <allan.herriman.hates.spam@ctam.com.au.invalid> schrieb im Newsbeitrag news:3f4f4d0b@dnews.tpgi.com.au... > Hi, > > I'm using ISE 5.2.03, using XST Verilog flow. > > I can't turn keep_hierarchy on in the Project Manager. There is no > field to do so in the Process - Properties - Synthesis Options dialog > (which is where the documentation says it should be). > > My problem is that my RLOCs don't work because XST flattens the > hierarchy and puts all my macros into the one HSET! I would like to try > with keep_hierarchy on, but the *&(#$% GUI won't let me. > > Help! > Allan. >Article: 59848
Nial, I am not familiar with the Quartus tool so I can not tell you. I use two or three levels of hierarchy in my designs and the schematichs is also very handy to disconnect and reconnect signals. Also if you suddenly want to route a debug signal up several levels to the top. I dont remember the commenting of the generated state machine code. HDL designer is a pretty good project manager as well. And you can write your own pearl plug-ins. > > Hakon, > > If just using the tool for top level block diagrams does it offer > any advantages over a top level schematic in Quartus (Altera's > tool)? > > The automatically generated documentation in HTML as mentioned > in another post sounds useful. > > If you do generate code from state machine diagrams etc does it > comment the resulting source code at all? > > > > Nial Stewart > ------------------------------------------------ > Nial Stewart Developments Ltd > FPGA and High Speed Digital Design > www.nialstewartdevelopments.co.uk > >Article: 59849
> Have you used the Actel FPGAs? Are there free tools? Can the flash also be > used to store additional data? Looks like a good candidate for a soft core > cpu (as for JOP :-) used not (yet, about too) free YeS NO, for APA075 it is free for others you need license and thats a yearly license that requires updates what cost almost full. full license is 2500+ USD for time limited its possible to buy a starterkit for 239 approx it contains dev board, programmer and libero gold license total over 800$ value would say. and for those who attent MSC PCI seminars the kit is available for 150 EUR (+german tax) there is one BADTHING the current ProAsic+ do require +16,5 and -13,5 power supplies during programming ! (programming is JTAG stapl) next version (G3?) should have onchip charge pump next next version (G4?) should have embedded flash-BROMs this is prelim information. when G4 comes reality it would be real cool platform for embedded fpga soft core SOC designs. there might be some more info available for those who manage to get accepted for Actel EAP (Early Access Program) antti
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