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Sudip Saha wrote: > Hi All, > I need help regarding use of configuration in vhdl. In my design, > one entity has got multiple architectures. Through Configuration I am > trying to bind a partcular architecture. But it seems that it always > taking the last compiled architecture and doing default binding. I am > using cadence NCSIM SIMULATOR. With modelsim, you have to invoke the configuration by name, and not mention the entity/architecture names directly. The configuration must be compiled into the same directory. -- Mike TreselerArticle: 59876
[exponential weighted averaging] > a_k = (1/(n+1))*s_k + (n/(n+1))*a_k-1 >As you can see this is quite easy to implement, requiring to >multiplies, one addition, and one register for a_k-1 storage. If you >choose n+1 do be a power of two then one of the multiplications (or I >guess it is a divide) becomes a simple shift operation. The other multiply/divide turns into a shift and subtract. -- The suespammers.org mail server is located in California. So are all my other mailboxes. Please do not send unsolicited bulk e-mail or unsolicited commercial e-mail to my suespammers.org address or any of my other addresses. These are my opinions, not necessarily my employer's. I hate spam.Article: 59877
"George" <george_mercury@hotmail.com> wrote in message news:6d167a0a.0308300945.eaf9b2a@posting.google.com... > Hello! > I am using the WebPack ( VHDL ) and the 9500 family CPLD. I would like > to make a SPI interface. So now I need a VHDL description of an 8 bit > parallel-in serial-out shift register with MSB shifting out first. So > far I haven't had any luck so I am asking you for help. I thank you in > advance for your efforts. You need to do a little work bud. Go to the Xilinx website and read through some of the application notes. Also, in Webpack, find a menu entry called "Library Templates". This is FULL of all sorts of examples and templates you can use. You can even do a Google/Yahoo/whatever search of this newsgroup and/or the 'net in general and find loads of examples and tutorials on FPGA's, Verilog, VHDL and other topics. There's no such thing as a dumb question, but I think that most newsgroup participants appreciate it when a poster does a little bit of work before asking for help. -- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ Martin Euredjian To send private email: 0_0_0_0_@pacbell.net where "0_0_0_0_" = "martineu"Article: 59878
> My first question is, which of these choices of MMC is least likely >to produce metastability at the output FF? >1) The MMC is a 4 FF long shift register clocked at 1000MHz. >2) The MMC is 4 FFs, each clock enabled every second clock. You should also consider 1 FF clocked as late as you can wait. Each FF has a setup time and a clock-output delay. I'm talking about the actual measured time, not the data book worst case times. If you chain FFs together, that time gets subtracted from the settling time. The settling time is in an exponent. Waiting a little bit longer helps a lot. -- The suespammers.org mail server is located in California. So are all my other mailboxes. Please do not send unsolicited bulk e-mail or unsolicited commercial e-mail to my suespammers.org address or any of my other addresses. These are my opinions, not necessarily my employer's. I hate spam.Article: 59879
>This is a kind of religion, I don't believe in "not possible", only in >"I don't know how to do". Yes, but there are several types of problems. A few of them are "well known" to be impossible. Examples include traveling faster than light and perpetual motion machines. I think metastability is one of these. Sure, I'll keep an eye open for new results, but I won't waste any time if I'm working on an engineering problem with current technology and I will use claims/suggestions of a solution as an idiot filter unless they are backed up by some amazing evidence. A usenet post isn't good enough. We're talking Nobel Prize class work. -- The suespammers.org mail server is located in California. So are all my other mailboxes. Please do not send unsolicited bulk e-mail or unsolicited commercial e-mail to my suespammers.org address or any of my other addresses. These are my opinions, not necessarily my employer's. I hate spam.Article: 59880
>this has nothing to do with quantization, until you get into QED, but is >a matter of statistical thermal noise on two cells that are used to jam >the outputs of a flop. You need the noise, but that has nothing to do >with undergrad quantum mechanics. Read Peter's stuff - he's quite good >and knowledgable. Do I need noise? Why? I thought the normal exponential decay was well modeled (Spice?) without noise. Perhaps you need it if the FF is "perfectly" ballanced but that has a vanishingly small probability in the real world. -- The suespammers.org mail server is located in California. So are all my other mailboxes. Please do not send unsolicited bulk e-mail or unsolicited commercial e-mail to my suespammers.org address or any of my other addresses. These are my opinions, not necessarily my employer's. I hate spam.Article: 59881
Hi Kevin, Thanks for your answer! The requirement of output throughput is 33-50MHz, i.e., it should output 33 million to 50 million 12-bits element per second, and each 5 inputs correspond to 10x10=100 such 12-bits element outputs... The technology I am going to use is 0.25u. I think the inputs are naturally serial, but I can let them be parallel, since there are only 5 of them, but again, I am not sure how to do the parallel-serial partition of the internal MACs... and how to pace the outputs... Seems inputs are faster than the outputs, maybe I should let the input wait after fed into the unit? Can you give some further advice on how to do this architecture? how to do the timing? I think it is really difficult...and point me to some resources? Thanks very much, -Walala "Kevin Neilson" <kevin_neilson@removethistextcomcast.net> wrote in message news:O854b.133933$2x.38873@rwcrnsc52.ops.asp.att.net... > You don't mention a very important parameter--speed. Depending upon the > bandwidth you require you can probably timeslice the MACs, saving hardware. > -Kevin > > "walala" <mizhael@yahoo.com> wrote in message > news:bipbje$51c$1@mozo.cc.purdue.edu... > > Dear all, > > > > I want to design an arithmatic datapath unit for digital signal processing > > using VHDL and/or Verilog. > > > > The input are 5 elements(either sequential or parallel) each having 8 > bits. > > It needs to multiply each of these 5 inputs with a predefined constant > > matrix(10x10, floating point scaled and round to integer). The output will > > be a 10x10 matrix summing the above five matrices up, each element having > 12 > > bits). So for each element of the matrix, I can have a MAC unit. The > > internal computation will be 16 bits. > > > > Hence for each 5 inputs x1, x2, x3, x4, x5, the output matrix > > > > Y=x1*C1+x2*C2+x3*C3+x4*C4+x5*C5 where Y, C1, C2, C3, C4, C5 are matrices; > > > > If I put an MAC for each element, I will have a purely parallel > > architecture, but I need 100 16bits MAC units, which will be too resource > > consuming. > > > > I am considering to make a parallel-serial architecture, at each time, it > > outputs one row, which will be 10x12 bits... so the output will be > > row-by-row. > > > > I also need to consider to streamlize the datapath operation. Since there > > will be a stream of 5 elements input in a non-stop fashion, the output > will > > also be non-stop streaming. So after one row is outputted, that row can be > > used for computation/storage of the results for the next 5 input elements. > > > > I am ok so far in thinking... but further thinking makes me confused and > > perplexed... how to do sequential timing control(how to what to do at > which > > cycle)? do I need to pipelining? how to design the architecture? I mean, I > > know pipelining theoratically from one semester course, but now I am going > > to implement one, I am totally lost... > > > > Finally, how to program this? Is there any examples for this? > > > > Please help me! > > > > Thanks a lot, > > > > -Walala > > > > > >Article: 59882
Hal Murray wrote: > > >this has nothing to do with quantization, until you get into QED, but is > >a matter of statistical thermal noise on two cells that are used to jam > >the outputs of a flop. You need the noise, but that has nothing to do > >with undergrad quantum mechanics. Read Peter's stuff - he's quite good > >and knowledgable. > > Do I need noise? Why? I thought the normal exponential decay > was well modeled (Spice?) without noise. Perhaps you need > it if the FF is "perfectly" ballanced but that has a vanishingly > small probability in the real world. I think you are right. There is only one point on a continuous range that will be perfectly balanced. The probability of that is in essence the inverse of infinity which I don't know that it even has meaning. If you require noise to shift you out of metastability, then the people who argue that more noise will get you out quicker could then be right. -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAXArticle: 59883
On Sat, 30 Aug 2003 23:15:18 -0400, rickman <spamgoeshere4@yahoo.com> wrote: >Hal Murray wrote: >> >> >this has nothing to do with quantization, until you get into QED, but is >> >a matter of statistical thermal noise on two cells that are used to jam >> >the outputs of a flop. You need the noise, but that has nothing to do >> >with undergrad quantum mechanics. Read Peter's stuff - he's quite good >> >and knowledgable. >> >> Do I need noise? Why? I thought the normal exponential decay >> was well modeled (Spice?) without noise. Perhaps you need >> it if the FF is "perfectly" ballanced but that has a vanishingly >> small probability in the real world. > >I think you are right. There is only one point on a continuous range >that will be perfectly balanced. The probability of that is in essence >the inverse of infinity which I don't know that it even has meaning. > >If you require noise to shift you out of metastability, then the people >who argue that more noise will get you out quicker could then be right. A metastable failure doesn't require that you land exactly on the balance point. There may be only one point that keeps you in the metastable state forever, but there's a range of points that will delay FF settling long enough to make your design fail. The more time you give the design to settle, the shorter that range of points is. Accordingly, noise doesn't have to kick the FF to that perfect balance point. It need only force you close enough that the FF output transition is sufficiently delayed to hose over the circuit. Bob Perlman Cambrian Design WorksArticle: 59884
The EDK reference design for ML300 is now directly downloadable from http://www.xilinx.com/ise/embedded/EDK/ml300_edk1.zip You can reach the same link as "example 21" from http://www.xilinx.com/ise/embedded/edk_examples.htm - Peter Antti Lukats wrote: > Hi > > those who want to build a linux hardware ref. platfrom for Virtex 2Pro > ML300 the reference desing for Xilinx EDK does exist - just received it. > it should be sufficient to run Montavista distribution, but I guess > denx ELDK would also work with minor patching. > > antti > this reference design really is available from your local Xilinx FAE! > (I didnt believe it until got it)Article: 59885
george_mercury@hotmail.com (George) wrote in message news:<6d167a0a.0308300945.eaf9b2a@posting.google.com>... > Hello! > I am using the WebPack ( VHDL ) and the 9500 family CPLD. I would like > to make a SPI interface. So now I need a VHDL description of an 8 bit > parallel-in serial-out shift register with MSB shifting out first. So > far I haven't had any luck so I am asking you for help. I thank you in > advance for your efforts. > > Best regards > George Mercury Here's what I cooked up: library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; -- 8-bit load, 1-bit shift out (msb first) -- -- if load is '1', a new value is loaded from d. -- if shift_out is '1', next bit is shifted out (msb first). -- entity shft4_1 is port (d: in std_logic_vector(7 downto 0); load: in std_logic; shift_out: in std_logic; clk: in std_logic; reset: in std_logic; q: out std_logic ); end entity; architecture Behavioral of shft8_1 is signal data: std_logic_vector(7 downto 0); begin process (d, load, clk, reset) begin if reset = '1' then data <= "00000000"; elsif rising_edge(clk) then if load = '1' then data <= d; elsif shift_out = '1' then data <= data(6 downto 0) & '0'; end if; end if; end process; q <= data(7); end Behavioral;Article: 59886
Problem Description: --------------------------------------- I have created the parallel cable III from the design that is online at the xilinx website. i am trying to configure my xc95108 but i cant and i receive an error message Error Message: --------------------------------------- Error: impact:1210 - '1':Boundary scan chain test failed at bit position '1'. a problem may exist in the hardware configuration..... My parallel cable is very short,and my parallel port works perfectly fine,since the printer is working. i don't have the cable over a monitor. i am in despair. i don't know what to do. if i don't program my CPLD i can't go on. could anyone help?Article: 59887
Thanassis Roubies <aroubies@hotmail.com> wrote: : Problem Description: : --------------------------------------- : I have created the parallel cable III from the design that is online : at the xilinx website. i am trying to configure my xc95108 but i cant : and i receive an error message : Error Message: : --------------------------------------- : Error: impact:1210 - '1':Boundary scan chain test failed at bit : position '1'. a problem may exist in the hardware configuration..... : My parallel cable is very short,and my parallel port works perfectly : fine,since the printer is working. i don't have the cable over a : monitor. i am in despair. i don't know what to do. if i don't program : my CPLD i can't go on. could anyone help? Debug with an oscilloscope at the xc95108 that all signals arrive andare the right ones... Bye -- Uwe Bonnes bon@elektron.ikp.physik.tu-darmstadt.de Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt --------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------Article: 59888
Hi, From a CLKDLL, how do I gate the CLKDV signal with LOCKED without getting the following warning when implementing: WARNING:NgdBuild:477 - clock net 'buffered10m' has non-clock connections. These problematic connections include: pin i0 on block u4_u1_clkout1 with type LUT2 I want to gate all the startup/synchronising clocks from the CLKDV signal until locked is achieved. My aim is to block the startup/synchronising waveform from getting to an external IC until the locked is achieved. The startup/synchronising takes about 24usec, during which time about 240x 10mhz clock edges are received by the external IC. Id like to only provide the external IC with 10mhz when the locked signal is achieved. Am I worrying about nothing? The IC (KAC1310) does not have an enable. I understand I can use the LOCKED signal as a nRESET to sub-modules, therefore this startup/synchronising waveform does not affect sub-modules. ISE 5.02.2i, SPARTAN-II, KAC1310. Thanks, Ben.Article: 59889
I'm new to Quartus II, and all I have done with it so far is walking through the tutorials. But there is one thing that I can't figure out: Is there a way to link the contents of a block in a schematic block diagram to another schematic block diagramm file, in order to get a hierarchy of schematic block diagrams, where finaly the bottom-most sbd-files are linked to hdl-source-files, like it is in say FPGA Advantage? Hopefully -"Panic"Article: 59890
I need an overview of FPGA boards and solutions describing the communication between the boards and PC applications. This would include reconfiguration and communication in operating mode. Thanks in advance.Article: 59891
Hi, I am a colledge student,one of my dreams is to design a 16-bit CPU,it has some basic functions,such as arithmatic and MMU and so on. But I don't have any idea how to get it.Can you give some suggestions about it? I mean,what steps should I take to obtain this dream,and at each step,which book should I read,how long will I get the dream? Any help appreciated!! This is a cry from a puzzled student for your help. Chen BinArticle: 59892
Bob Perlman wrote: > > On Sat, 30 Aug 2003 23:15:18 -0400, rickman <spamgoeshere4@yahoo.com> > wrote: > > >Hal Murray wrote: > >> > >> >this has nothing to do with quantization, until you get into QED, but is > >> >a matter of statistical thermal noise on two cells that are used to jam > >> >the outputs of a flop. You need the noise, but that has nothing to do > >> >with undergrad quantum mechanics. Read Peter's stuff - he's quite good > >> >and knowledgable. > >> > >> Do I need noise? Why? I thought the normal exponential decay > >> was well modeled (Spice?) without noise. Perhaps you need > >> it if the FF is "perfectly" ballanced but that has a vanishingly > >> small probability in the real world. > > > >I think you are right. There is only one point on a continuous range > >that will be perfectly balanced. The probability of that is in essence > >the inverse of infinity which I don't know that it even has meaning. > > > >If you require noise to shift you out of metastability, then the people > >who argue that more noise will get you out quicker could then be right. > > A metastable failure doesn't require that you land exactly on the > balance point. There may be only one point that keeps you in the > metastable state forever, but there's a range of points that will > delay FF settling long enough to make your design fail. The more time > you give the design to settle, the shorter that range of points is. > > Accordingly, noise doesn't have to kick the FF to that perfect balance > point. It need only force you close enough that the FF output > transition is sufficiently delayed to hose over the circuit. I don't think you understand the point. We are not saying that balance or noise are required to demonstrate metastability. It was pointed out that in a simulation of the effect, something would be needed to move the FF off the balance point and noise was suggested. But in the real world the "balance point" is so vanishing small, it would never actually happen. That is not saying that the FF can not go metastable without being balanced. -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAXArticle: 59893
Hi,all I use synplify or Quartus to do the synthesis. What files should I pass to Modelsim to do the timing simulation? Thanks ans Regards.Article: 59894
On Sun, 31 Aug 2003 10:55:19 -0400, rickman <spamgoeshere4@yahoo.com> wrote: >Bob Perlman wrote: >> >> On Sat, 30 Aug 2003 23:15:18 -0400, rickman <spamgoeshere4@yahoo.com> >> wrote: >> >> >Hal Murray wrote: >> >> >> >> >this has nothing to do with quantization, until you get into QED, but is >> >> >a matter of statistical thermal noise on two cells that are used to jam >> >> >the outputs of a flop. You need the noise, but that has nothing to do >> >> >with undergrad quantum mechanics. Read Peter's stuff - he's quite good >> >> >and knowledgable. >> >> >> >> Do I need noise? Why? I thought the normal exponential decay >> >> was well modeled (Spice?) without noise. Perhaps you need >> >> it if the FF is "perfectly" ballanced but that has a vanishingly >> >> small probability in the real world. >> > >> >I think you are right. There is only one point on a continuous range >> >that will be perfectly balanced. The probability of that is in essence >> >the inverse of infinity which I don't know that it even has meaning. >> > >> >If you require noise to shift you out of metastability, then the people >> >who argue that more noise will get you out quicker could then be right. >> >> A metastable failure doesn't require that you land exactly on the >> balance point. There may be only one point that keeps you in the >> metastable state forever, but there's a range of points that will >> delay FF settling long enough to make your design fail. The more time >> you give the design to settle, the shorter that range of points is. >> >> Accordingly, noise doesn't have to kick the FF to that perfect balance >> point. It need only force you close enough that the FF output >> transition is sufficiently delayed to hose over the circuit. > >I don't think you understand the point. We are not saying that balance >or noise are required to demonstrate metastability. It was pointed out >that in a simulation of the effect, something would be needed to move >the FF off the balance point and noise was suggested. But in the real >world the "balance point" is so vanishing small, it would never actually >happen. That is not saying that the FF can not go metastable without >being balanced. Whoever said, "If you require noise to shift you out of metastability, then the people who argue that more noise will get you out quicker could then be right," could you explain further? Are you saying that noise is required to resolve the metastable state, or is this a counter-argument to the "noise may get you out faster" claim? Or is it something else entirely? Bob Perlman Cambrian Design WorksArticle: 59895
yes, VHLD would be nice too. I'm still green in VHDL so I don't want to publish code that might be wrong or ugly. If someone translates anything, fell free to send in! Jean "John Williams" <jwilliams@itee.uq.edu.au> wrote in message news:bigoij$bs8$1@bunyip.cc.uq.edu.au... > Jean Nicolle wrote: > > my manager said it couldn't be done. So just to prove him wrong :-) > > There is no better reason! :-) > > > http://www.fpga4fun.com/PWM_DAC.html > > > > Well, pretty simple stuff anyway. > > Nice work Jean, it's a great thing you're doing with that site. > > Ever considered putting VHDL and verilog side-by-side for your examples? > > Regards, > > John > >Article: 59896
Pawel Kolodziej wrote: > In article <a2214fd40dcc30b0380a43f3441e0804@news.teranews.com>, Rene Tschaggelar wrote: > >>Yes. >>I'd get the peche melba by saving my time by not spending a >>few hours on the internet looking for free samples of 4$ parts. > > > Could someone tell me what is price of Altera Cyclone devices ? > In Poland EP1C3T100C7 costs about 30$ (When I want to buy only 1 > piece). I think it's to expensive. I did a search on EBV : http://www.ebv.com , a European distributor, it was listed there for 25,72 Euros. Their prices are about right I think. There are also distributors here with a minimum billing value of 100 Euros. EBV is not one of them, IIRC. Rene -- Ing.Buero R.Tschaggelar - http://www.ibrtses.com & commercial newsgroups - http://www.talkto.netArticle: 59897
Right click on the block you created. You can use use the Create Design File
From Selected Block. to generate a lower level Schematic file (bdf), VHDL
file (vhd), Verilog File (v) or AHDL (tdf) file for the selected Block.
These generated files will contain the I/O definitions that were defined by
the block. You can then open the generated file and enter the rest of the
design.
For example my schematic had a block called block_name with 4 ports. I right
clicked on the block and used the Create Design File From Selected Block
command to generate the file block_name.vhd file. The contents of the
generated block_name.vhd is as follows:
.....Copyright text
-- Generated by Quartus II Version 3.0 (Build Internal Build 225 08/11/2003)
LIBRARY ieee;
USE ieee.std_logic_1164.all;
-- Entity Declaration
ENTITY block_name IS
-- {{ALTERA_IO_BEGIN}} DO NOT REMOVE THIS LINE!
PORT
(
a : IN STD_LOGIC;
b : IN STD_LOGIC_VECTOR(2 downto 0);
c : OUT STD_LOGIC;
d : OUT STD_LOGIC_VECTOR(3 downto 0)
);
-- {{ALTERA_IO_END}} DO NOT REMOVE THIS LINE!
END block_name;
-- Architecture Body
ARCHITECTURE block_name_architecture OF block_name IS
BEGIN
-- Enter your logic here
END block_name_architecture;
Hope this helps.
- Subroto Datta
Altera Corp.
"Panic" <panic74@hotmail.com> wrote in message
news:Zxm4b.18758$os2.258386@news2.e.nsc.no...
> I'm new to Quartus II, and all I have done with it so far
> is walking through the tutorials. But there is one thing that
> I can't figure out:
>
> Is there a way to link the contents of a block in a schematic
> block diagram to another schematic block diagramm file, in
> order to get a hierarchy of schematic block diagrams, where
> finaly the bottom-most sbd-files are linked to hdl-source-files,
> like it is in say FPGA Advantage?
>
> Hopefully
> -"Panic"
>
>
Article: 59898At the risk of starting a toolset discussion, I would recommend www.aldec.com and their ActiveHDL product. Its mainly a very user friendly simulator (still not perfect, but a lot friendlier than Modelsim and on a par with its power and speed) but it also does much of the design entry and state machine generation/ testbench generation and project management as well. It also integrates very well with a large number of synthesis tools so that you never need to leave ActiveHDL to synthesise and then simulate the finalised P&R product. I believe you can get a reduced price Altera-only or Xilinx-only version. My 2 pence worth :) Having used it for real for a year or so. No affiliation with the company etc. etc. Paul Baxter "Robert Abiad" <abiad@ssl.berkeley.deletethisandaddedu> wrote in message news:3F4E6463.5030207@ssl.berkeley.deletethisandaddedu... > > Hello, > > I'm wondering if anyone wants to offer up their opinion of Mentor's HDL Designer > series or FPGA Advantage (Designer + simulation&synthesis)? I recently acquired > it, but am wondering about the quality of the resulting code. It looks like it > might be very easy to produce stuff with it, but does it save time coding in the > end? > > Thanks, > -robert >Article: 59899
> This will be your friend for long URLs. > http://tinyurl.com/ Please also include the full/long URL so google gets it. Shortcuts age and die after a while. -- The suespammers.org mail server is located in California. So are all my other mailboxes. Please do not send unsolicited bulk e-mail or unsolicited commercial e-mail to my suespammers.org address or any of my other addresses. These are my opinions, not necessarily my employer's. I hate spam.
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