Custom Search
Site Home Archive Home FAQ Home How to search the Archive How to Navigate the Archive
Compare FPGA features and resources
Threads starting:
Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z
"Alan Fitch" <alan.fitch@doulos.com> wrote in message news:<bhi66c$83i$1$8302bc10@news.demon.co.uk>...
> "Slawek" <piran125@interia.pl> wrote in message
> news:dd729dc8.0308141443.3e517b07@posting.google.com...
> > I am trying to simulate small VHDL project (which I syntheze before
> > with Exemplar logic) and recive errors like below:
> >
> > # Loading project
> > vcom -reportprogress 300 -work work
> > {C:/SystemDesigner/designs/dyplom/DZIELNIKZEGARA_PRZEZ3.VHD}
> > # Model Technology ModelSim ATMEL vcom 5.5a Compiler 2001.04 Apr 5
> > 2001
> > # -- Loading package standard
> > # -- Loading package std_logic_1164
> > # ERROR: Could not find exemplar.exemplar
> > # ERROR:
> C:/SystemDesigner/designs/dyplom/DZIELNIKZEGARA_PRZEZ3.VHD(8):
> > cannot find expanded name: exemplar.exemplar
> > # ERROR:
> C:/SystemDesigner/designs/dyplom/DZIELNIKZEGARA_PRZEZ3.VHD(8):
> > Unknown field: exemplar.
> > # ERROR: Could not find exemplar.exemplar_1164
> > # ERROR:
> C:/SystemDesigner/designs/dyplom/DZIELNIKZEGARA_PRZEZ3.VHD(9):
> > cannot find expanded name: exemplar.exemplar_1164
> > # ERROR:
> C:/SystemDesigner/designs/dyplom/DZIELNIKZEGARA_PRZEZ3.VHD(9):
> > Unknown field: exemplar_1164.
> > # ERROR:
> C:/SystemDesigner/designs/dyplom/DZIELNIKZEGARA_PRZEZ3.VHD(11):
> > VHDL Compiler exiting
> >
> >
> > Can You please advise how to show Modelsim the missing packages?
> > Where to take them from?
> > I am using these tools as parts of Atmel's System Designer for
> FPSLIC
> >
> > Thx for any ideas,
> > Slawek
>
>
> You should find the source code (VHDL) for the missing packages
> in the Leonardo installation. It's in the file
>
> <path to leonardo>\data\exemplar.vhd
>
> In modelsim, you need to compile that file into a library called
> exemplar. From the modelsim command prompt
>
> vlib exemplar
> vmap work exemplar
> vcom <path to leonardo>\data\exemplar.vhd
>
> vmap work <your normal library>
>
>
> That should work. However if you use Modelsim Projects, they have
> a stupid "feature" of creating a "work" library in a folder called
> "work",
> which will probably cause my instructions above to fail :-(
>
> So you might find it easier to do this
> vlib exemplar
>
> Click the modelsim "Compile" icon.
> From the drop-down list of libraries select "exemplar"
> Browser to exemplar.vhd
> click OK
>
> Then when you compile your normal code, select "work" from
> the drop-down list.
>
> When you start simulation, you should be able to see to libraries,
> your normal work library, and the library called "exemplar". If you
> click on "exemplar" you should see a letter P (for Package) next to
> a package called exemplar.
>
> Hope this helps,
>
> kind regards
>
> Alan
>
> --
> Alan Fitch
> Consultant
Thank You Alan,
It works!!!
Best regards,
Slawek
Article: 59351I've only been using this for a few months now. So it's hard to say. Perhaps not that reliable for getting archived in Google groups, but then, even a full link doesn't seem to stand the test of time these days. I have to constantly delete or modify my bookmarks folder for broken links. "Jon Harris" <jon_harrisTIGER@hotmail.com> wrote in message news:3f3ad2ce$1_1@newsfeed... > That toolbar method is pretty neat! The only thing I wonder about is how > long the URL redirection will work. And of course it assumes that the > tinyURL server is always up. > > "Bhaskar Thiagarajan" <bhaskart@deja.com> wrote in message > news:bhgrnu$lln6$1@ID-82263.news.uni-berlin.de... > > Jon > > > > This will be your friend for long URLs. > > http://tinyurl.com/ > > You can create a toolbar button and click that after a long link web page > > and it voila, out pops the smaller one. > > For example... > > http://tinyurl.com/k1x6 > > > > Cheers > > Bhaskar > > > > "Jon Harris" <jon_harrisTIGER@hotmail.com> wrote in message > > news:3f3a9180$1_1@newsfeed... > > > You can find the patent here: > > > > > > http://patft.uspto.gov/netacgi/nph-Parser?Sect1=PTO1&Sect2=HITOFF&d=PALL&p=1 > > > > > > &u=/netahtml/srchnum.htm&r=1&f=G&l=50&s1=5528736.WKU.&OS=PN/5528736&RS=PN/55 > > > 28736 > > > (Watch the word wrap--I wish I knew how to get shorter URLs out of the > > USPTO > > > site.) > > > > > > Clay, I interpreted his statement about "100% HW utilization" to mean > that > > > it packed well into current FPGA architectures, allowing (near) 100% > > > utilization of the FPGA, not that it required 100% of any particular HW > > > device. > > > > > > -Jon > > > > > > "Clay S. Turner" <physicsNOOOOSPPPPAMMMM@bellsouth.net> wrote in message > > > news:sVw_a.7804$_3.5732@fe02.atl2.webusenet.com... > > > > Hello Seung, > > > > > > > > If you have 100% hardware utilization, doesn't this present a problem > if > > > you > > > > make a change to the design?? > > > > > > > > Curious what is the # for your patent?? > > > > > > > > Clay > > > > > > > > > > > > "Seung" <kim.seung@sbcglobal.net> wrote in message > > > > news:fdf92243.0308131136.74aff961@posting.google.com... > > > > > Hello > > > > > > > > > > I have a patent and recently added one more on innovative FFT > > > > > algorithm and architecture. > > > > > If you're a business minded expert on FPGA with interests in DSP, > this > > > > > is a great opportunity. Our FFT is 'the' optimal HW solution as > > > > > follows: > > > > > > > > > > 1. Minimum HW complexity: 100% HW utilization > > > > > 2. Suitable for super fast pipelined FFT: only local data flow - not > > > > > based on butterfly algorithm > > > > > 3. Minimum clock cycles: baseline architecture needs N clock for > > > > > N-point FFT > > > > > 4. Scalable to arbitrary large FFT size > > > > > 5. Multi-dimension extension: world's first 'intrinsic' > > > > > multi-dimensional FFT algorithm & architecture (not relay on 1-D > FFTs) > > > > > : great for 2-D/3-D real-time medical imaging, SAR, etc. > > > > > > > > > > If you're interested in building a business together based on this > > > > > innovation, > > > > > please contact me with your resume. It'll be ideal if you have > > > > > contacts for potential customers. > > > > > > > > > > Any help on this matter from FPGA/DSP group members will be > > > > > appreciated. > > > > > > > > > > > > > > > Thanks. > > > > > > > > > > Seung P. Kim, Ph.D > > > > > Silicon Computing, Inc. > > > > > Mountain View, CA > > > > > > > > > > > > > > > > > > > > > > > >Article: 59352
"Jon Harris" <jon_harrisTIGER@hotmail.com> wrote in message news:<3f3a9180$1_1@newsfeed>... > You can find the patent here: > http://patft.uspto.gov/netacgi/nph-Parser?Sect1=PTO1&Sect2=HITOFF&d=PALL&p=1 > &u=/netahtml/srchnum.htm&r=1&f=G&l=50&s1=5528736.WKU.&OS=PN/5528736&RS=PN/55 > 28736 > (Watch the word wrap--I wish I knew how to get shorter URLs out of the USPTO > site.) > Try www.tinyurl.com With that utility, the url became: http://tinyurl.com/k1x6 > Clay, I interpreted his statement about "100% HW utilization" to mean that > it packed well into current FPGA architectures, allowing (near) 100% > utilization of the FPGA, not that it required 100% of any particular HW > device. > > -Jon > > "Clay S. Turner" <physicsNOOOOSPPPPAMMMM@bellsouth.net> wrote in message > news:sVw_a.7804$_3.5732@fe02.atl2.webusenet.com... > > Hello Seung, > > > > If you have 100% hardware utilization, doesn't this present a problem if > you > > make a change to the design?? > > > > Curious what is the # for your patent?? > > > > Clay > > > > > > "Seung" <kim.seung@sbcglobal.net> wrote in message > > news:fdf92243.0308131136.74aff961@posting.google.com... > > > Hello > > > > > > I have a patent and recently added one more on innovative FFT > > > algorithm and architecture. > > > If you're a business minded expert on FPGA with interests in DSP, this > > > is a great opportunity. Our FFT is 'the' optimal HW solution as > > > follows: > > > > > > 1. Minimum HW complexity: 100% HW utilization > > > 2. Suitable for super fast pipelined FFT: only local data flow - not > > > based on butterfly algorithm > > > 3. Minimum clock cycles: baseline architecture needs N clock for > > > N-point FFT > > > 4. Scalable to arbitrary large FFT size > > > 5. Multi-dimension extension: world's first 'intrinsic' > > > multi-dimensional FFT algorithm & architecture (not relay on 1-D FFTs) > > > : great for 2-D/3-D real-time medical imaging, SAR, etc. > > > > > > If you're interested in building a business together based on this > > > innovation, > > > please contact me with your resume. It'll be ideal if you have > > > contacts for potential customers. > > > > > > Any help on this matter from FPGA/DSP group members will be > > > appreciated. > > > > > > > > > Thanks. > > > > > > Seung P. Kim, Ph.D > > > Silicon Computing, Inc. > > > Mountain View, CA > > > > > >Article: 59353
I'm working on a FPGA that is to have a few R/W registers on a VME bus. Anybody have some VHDL code they would like to share? If I use your ideas then your name will forever be in lights! Thanks!Article: 59354
Jeff Sampson <jsampson@pobox.com> writes: > So unless I find some in 1 or 2 quantity at a reasonable price (this > is for a prototyping system so I would prefer 5V parts) I guess I'll > go with Spartan II and use level translators on the outputs. Why do you need level translators? The Spartan II has 5V-tolerant I/Os. If you wanted to use the Spartan-IIE or Spartan-3 with 5V signals, you would need series resistors, clamping with quickswitches, or level converters.Article: 59355
I am not sure what True 5V parts are and my board is definetely on the 3.3V side of technology. I would suppose that most fpgas would have FIFO macros. I would rather have dedicated hardware as in the Cypress chips because I am handling some long video streams and need a lot of space. Thanks though. > True 5V parts, supported by current software, and FIFOs are available > as standard macros. >Article: 59356
Hi all, I'm giving away a bunch of free stuff. Basically it's a CPU suitable for small FPGAs with some compilation and simulation tools. It's at: http://www.tinyboot.com/cd16 -- Brad EckertArticle: 59357
Eric Smith wrote: > Jeff Sampson <jsampson@pobox.com> writes: > >>So unless I find some in 1 or 2 quantity at a reasonable price (this >>is for a prototyping system so I would prefer 5V parts) I guess I'll >>go with Spartan II and use level translators on the outputs. > > Why do you need level translators? The Spartan II has 5V-tolerant I/Os. > > If you wanted to use the Spartan-IIE or Spartan-3 with 5V signals, you > would need series resistors, clamping with quickswitches, or level > converters. The inputs are 5V tolerant. But the outputs can only be driven with 3.3V (at the VCCO pin). Or am I wrong? If I can drive the outputs with 5V that would save lots of screwing around. I don't remember right of hand where I saw that. But I'll go back and track it down. I did end up buying Spartan II parts. -- Jeff Sampson http://tcrobots.org/members/jsamp.htmArticle: 59358
Hello everyone, I have a design which has a FSM acting as a controller for an algorithm. It has 25 states but three of them are used for: state 5 --Reading data from the block ram by setting the en, rw, address signals and using a variable name data which is declared as 'reg' in the state machine to latch data out of the ram. state 6-- add a constant value to 'reg data' and set set the dataout equall to that eg dataout = data +5; then set en, rw and address variables so that this value gets written in ram. state7- wait a clk cycle. The variable are defined in the statemachine module as reg [15,0] data; // its further defined as input reg [15,0] address; // its further defined as output reg [15,0] dataout; // its further defined as output and so on these variables are also assigned a value of zero in default state to avoid latches But only three states use them and rest do not. PROBLEM functional simmulation is fine Place and route tool is removing the ram saying that all the above signals are sourceless. Although i can see them connected correctly after synthesis. Question; Why is data and rest of the signals becomming a latch since i have it assigned a value both in reset and default state and its being utilized in state 5 ,6 ,7. Thanks for the helpArticle: 59359
Jeff Sampson wrote: > > Eric Smith wrote: > > Jeff Sampson <jsampson@pobox.com> writes: > > > >>So unless I find some in 1 or 2 quantity at a reasonable price (this > >>is for a prototyping system so I would prefer 5V parts) I guess I'll > >>go with Spartan II and use level translators on the outputs. > > > > Why do you need level translators? The Spartan II has 5V-tolerant I/Os. > > > > If you wanted to use the Spartan-IIE or Spartan-3 with 5V signals, you > > would need series resistors, clamping with quickswitches, or level > > converters. > > The inputs are 5V tolerant. But the outputs can only be driven with 3.3V (at the > VCCO pin). Or am I wrong? If I can drive the outputs with 5V that would save > lots of screwing around. I don't remember right of hand where I saw that. But > I'll go back and track it down. > > I did end up buying Spartan II parts. You may still have to screw around. It depends on whether you really need outputs to go up to 5 volts. The Spartan II parts clamp just above the 3.3 volt rail. So the output will not go to 5 volts no matter what you do. But you can use one of the various techniques to interface the part to 5 volt signals. -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAXArticle: 59360
On Fri, 15 Aug 2003 20:46:32 -0700, rickman wrote: > Jeff Sampson wrote: >> >> Eric Smith wrote: >> > Jeff Sampson <jsampson@pobox.com> writes: >> > >> >>So unless I find some in 1 or 2 quantity at a reasonable price (this >> >>is for a prototyping system so I would prefer 5V parts) I guess I'll >> >>go with Spartan II and use level translators on the outputs. >> > >> > Why do you need level translators? The Spartan II has 5V-tolerant >> > I/Os. >> > >> > If you wanted to use the Spartan-IIE or Spartan-3 with 5V signals, >> > you would need series resistors, clamping with quickswitches, or >> > level converters. >> >> The inputs are 5V tolerant. But the outputs can only be driven with >> 3.3V (at the VCCO pin). Or am I wrong? If I can drive the outputs with >> 5V that would save lots of screwing around. I don't remember right of >> hand where I saw that. But I'll go back and track it down. >> >> I did end up buying Spartan II parts. > > You may still have to screw around. It depends on whether you really > need outputs to go up to 5 volts. The Spartan II parts clamp just above > the 3.3 volt rail. So the output will not go to 5 volts no matter what > you do. But you can use one of the various techniques to interface the > part to 5 volt signals. Actually thats not true for SpartanII, Inputs will draw no appreciable current with 5V in. (I've measured it) Because of this you can get 5V output swing (slowly) by using pullup resistors (to 5V) and using an open drain type output configuration. One thing you need to be careful of is that if you have 5V Pullup resistors, dont set the outputs to drive high because in that case they will drive to VCCO and worse, the pullup current will flow into the output clamp, possibly raising your VCCO to dangerous levels if it is supplied by a regulator that only supplies VCCO (regulators do not expect reversed current flow) Peter WallaceArticle: 59361
Most On Semi, Arizona, cypress etc. ECL components use about 7 Ohms output impedance. You will find that the majority of us old ECL designers just plop a 43 Ohm on a 50 Ohm line. Why is it that your ECL outs (PECL is just a rail definition) are under this? Andrew Austin Lesea wrote: >5.6 ohms.... > >Again from the terminator wizard. Where did you get 7 ohms? From the midpoint of >the IV curve (which is pretty close to the estimate from hyperlynx which looks at >the transistion region and averages the R). > >Austin > >Andrew Paule wrote: > > > >>Is the PECL 7 Ohms? >> >>Andrew >> >>Austin Lesea wrote: >> >> >> >>>22.6 ohms, typical corners of PVT >>> >>>This can be found by using the "terminator Wizard" in Hyperlynx, or by taking >>>the V/I in the IV tables directly from the ASCII IBIS model. >>> >>>Austin >>> >>> >>> >>>Jeremy Whatley wrote: >>> >>> >>> >>> >>> >>>>Can anyone tell me what kind of output impedance I should expect to see from >>>>a Xilinx Virtex II XC2V1000-FF896 FPGA? The Digitally Controlled Impedance >>>>feature was not used for this design. The signals in question are LVTTL >>>>12mA fast slew rate (I think that's default). >>>> >>>>Thanks! >>>> >>>>Jeremy Whatley >>>>jeremyw@erlangtech.com >>>> >>>> >>>> >>>> >>> >>> >>> > > >Article: 59362
alison wrote: > > Hello everyone, > > I have a design which has a FSM acting as a controller for an > algorithm. > It has 25 states but three of them are used for: > > state 5 --Reading data from the block ram by setting the en, rw, > address signals > and using a variable name data which is declared as 'reg' in the state > machine > to latch data out of the ram. > > state 6-- add a constant value to 'reg data' and set set the dataout > equall to that eg dataout = data +5; > then set en, rw and address variables so that this value gets written > in ram. > > state7- wait a clk cycle. > > The variable are defined in the statemachine module as > > reg [15,0] data; // its further defined as input > reg [15,0] address; // its further defined as output > reg [15,0] dataout; // its further defined as output > > and so on > > these variables are also assigned a value of zero in default state to > avoid latches > > But only three states use them and rest do not. > > PROBLEM functional simmulation is fine > > Place and route tool is removing the ram saying that all the above > signals are sourceless. Although i can see them connected correctly > after synthesis. > > Question; Why is data and rest of the signals becomming a latch since > i have it assigned a value both in > reset and default state and its being utilized in state 5 ,6 ,7. > > Thanks for the help I'm not certain what you are saying, but if you mean that the data signal is not assigned a value in the *other* states (i.e. 1 through 4 and 8 through 25) then it will form a latch. You need to assign these signals a value in *all* cases. You *are* using a case statement, right? BTW, another, perhaps simpler way to do this, is to take the data path statements out of your case statement and instead decode your state control signals. Then everything will be combinatorial for sure. -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAXArticle: 59363
As rickman pointed out, assignments in the default state of a decoder
do not apply to all the states.
Looks like you're using Verilog, so I'd suggest the following style
for the default assignments:
dataout = your_default_value;
case (state)
STATE1:
STATE2:
STATE3:
STATE4:
STATE5: dataout = value_in_state_5;
STATE6: dataout = value_in_state_6;
STATE7: dataout = value_in_state_7;
default: dataout = your_default_value;
endcase
This should take care of the latch inference problem.
Jim Wu
jimwu88NOOOSPAM@yahoo.com
verilogquestion@yahoo.com (alison) wrote in message news:<4fe9efd7.0308151808.5dd21f51@posting.google.com>...
> Hello everyone,
>
> I have a design which has a FSM acting as a controller for an
> algorithm.
> It has 25 states but three of them are used for:
>
> state 5 --Reading data from the block ram by setting the en, rw,
> address signals
> and using a variable name data which is declared as 'reg' in the state
> machine
> to latch data out of the ram.
>
> state 6-- add a constant value to 'reg data' and set set the dataout
> equall to that eg dataout = data +5;
> then set en, rw and address variables so that this value gets written
> in ram.
>
> state7- wait a clk cycle.
>
> The variable are defined in the statemachine module as
>
> reg [15,0] data; // its further defined as input
> reg [15,0] address; // its further defined as output
> reg [15,0] dataout; // its further defined as output
>
>
> and so on
>
> these variables are also assigned a value of zero in default state to
> avoid latches
>
> But only three states use them and rest do not.
>
>
> PROBLEM functional simmulation is fine
>
> Place and route tool is removing the ram saying that all the above
> signals are sourceless. Although i can see them connected correctly
> after synthesis.
>
>
> Question; Why is data and rest of the signals becomming a latch since
> i have it assigned a value both in
> reset and default state and its being utilized in state 5 ,6 ,7.
>
>
>
>
>
> Thanks for the help
Article: 59364Jeff Sampson <jsampson@pobox.com> writes about the Spartan II: > The inputs are 5V tolerant. But the outputs can only be driven with > 3.3V (at the VCCO pin). Or am I wrong? Yes, but 3.3V CMOS output drive is acceptable for use with most 5V systems. Most 5V components have TTL-compatible inputs, which only require Vih of 2.0V. The exceptions are devices with true CMOS inputs, such as 74HC and 74AC parts (as opposed to 74HCT and 74ACT). Most CMOS memories and peripheral chips have TTL-compatible inputs.Article: 59365
jimwu88NOOOSPAM@yahoo.com (Jim Wu) wrote in message news:<70223a9.0308160833.140fa73d@posting.google.com>... > As rickman pointed out, assignments in the default state of a decoder > do not apply to all the states. > > Looks like you're using Verilog, so I'd suggest the following style > for the default assignments: > > dataout = your_default_value; > > case (state) > STATE1: > STATE2: > STATE3: > STATE4: > STATE5: dataout = value_in_state_5; > STATE6: dataout = value_in_state_6; > STATE7: dataout = value_in_state_7; > default: dataout = your_default_value; > endcase > > This should take care of the latch inference problem. > > Jim Wu > jimwu88NOOOSPAM@yahoo.com > > verilogquestion@yahoo.com (alison) wrote in message news:<4fe9efd7.0308151808.5dd21f51@posting.google.com>... > > Hello everyone, > > > > I have a design which has a FSM acting as a controller for an > > algorithm. > > It has 25 states but three of them are used for: > > > > state 5 --Reading data from the block ram by setting the en, rw, > > address signals > > and using a variable name data which is declared as 'reg' in the state > > machine > > to latch data out of the ram. > > > > state 6-- add a constant value to 'reg data' and set set the dataout > > equall to that eg dataout = data +5; > > then set en, rw and address variables so that this value gets written > > in ram. > > > > state7- wait a clk cycle. > > > > The variable are defined in the statemachine module as > > > > reg [15,0] data; // its further defined as input > > reg [15,0] address; // its further defined as output > > reg [15,0] dataout; // its further defined as output > > > > > > and so on > > > > these variables are also assigned a value of zero in default state to > > avoid latches > > > > But only three states use them and rest do not. > > > > > > PROBLEM functional simmulation is fine > > > > Place and route tool is removing the ram saying that all the above > > signals are sourceless. Although i can see them connected correctly > > after synthesis. > > > > > > Question; Why is data and rest of the signals becomming a latch since > > i have it assigned a value both in > > reset and default state and its being utilized in state 5 ,6 ,7. > > > > > > > > > > > > Thanks for the help Thanks alot guys i will give it a try. alisonArticle: 59366
I have a VHDL design for an Altera Stratix EP1S80 that compiles under SynplifyPro 7.2, but the SynplifyPro Mapper runs endlessly and fails to finish. The log file shows that optimization was performed, but then nothing more. The same design compiled for a Xilinx Virtex part compiles and maps successfully. Any ideas? Thanks!Article: 59367
John,
Have you tried contacting Synplicity Technical support? You may want to
try the VHDL Synthesis that is available as part of Quartus II 3.0 in the
meantime, if you are stuck.
- Subroto Datta
Altera Corp.
"John Jerz" <jjerz@joimail.com> wrote in message
news:cdd844fb.0308161622.41d0d818@posting.google.com...
> I have a VHDL design for an Altera Stratix EP1S80 that compiles under
> SynplifyPro 7.2, but the SynplifyPro Mapper runs endlessly and fails
> to finish.
>
> The log file shows that optimization was performed, but then nothing
> more.
>
> The same design compiled for a Xilinx Virtex part compiles and maps
> successfully.
>
> Any ideas?
>
> Thanks!
Article: 59368In article <3F3BB5FB.E37C74BC@xilinx.com>, Peter Alfke <peter@xilinx.com> wrote: >Jeff, if you want to maintain or upgrade an existing board or box, your >question makes sense, and Austin gave you some advice. > >If you plan a new design, throw these devices and their software away. >New devices, be they Spartan or Virtex-II, are so much cheaper, and so >much more powerful and feature-rich, and the software is so much better... > >If you found a '286-based computer, would you start using it?? > >Using my formula of one FPGA-year = 15 human years, these devices are >>180 years old Civil War veterans. Give them a degnified burial... >Peter Alfke Actually, I would use an old 286. There are DOS programs I use that are still more functional and less demanding of the power they need than half the stuff sold nowadays. Advancement doesn't always mean better. LTArticle: 59369
Mike Treseler <mike.treseler@flukenetworks.com> wrote in message news:<3F3D2D05.5040005@flukenetworks.com>... > > # ERROR: Could not find exemplar.exemplar > > # ERROR: Could not find exemplar.exemplar_1164 > > > Try commenting out the USE commands containing exemplar. > There is a good chance that these are not really being referenced. > > If they are, consider fixing up the code to use > the standard ieee packages: > > library ieee; > use ieee.std_logic_1164.all; > use ieee.numeric_std.all; > > There is no longer much upside to using > vendor specific packages. > > -- Mike Treseler I am using them as I increment bit_vectors (and exemplar overloads "+" for bit_vectors). As I remamber numeric doesn't allow it. Best regards, SlawekArticle: 59370
I want to work from home on my University project. The University uses Foundation 4.2 and I want to know if any of the free downloads (i.e Webpack) will be compatitble so that I can take me designs into Uni done from home and have no trouble simulating on their platform. I am sure this question has been asked and answered many times. Apologies if so. DaveArticle: 59371
Hi Group,
This is a question related to custom memory array implementaion.
I need to implement two memory array which alternate for read and
write according to the following:
Writing input into Array:
Every clock cycle a module produces a 256 bit wide data. At the end of
128 clock cycles, this data fills the memory array and no read takes
places till that point. R127 has to hold the value in first clock
cycle, Rn has to hold the value in 128-n clock cycle,R0 has to hold
the value in 128 th clock cycle.I can use a 1 to 128 (256 bit wide)
DeMux which select address decreases from 127 to 0.
Reading: Basically two arrays alternate for read and write.
A 128 to 1 (256 bit wide) MUX reads one of the data items in the array
(which was written 128 clock cycles earlier) based on MUX select
signal which is produced some where else. Reading is not in any
particular order.
Input ---------------
--/-- |DeMux| | R0 |
256 ---------------
---------------
| R1 |
---------------
:
:
---------------
| R127 |
--------------- ---|MUX| --/--
256
Now my question is :
I can steer the input into array using a 128 to 1 demux (256 bit
wide). However since I know the order in which the data goes, I don't
necessairly need to use a demux. Every clock cycle I write into R0
only.I will have shift bit associated with each data location except
at R127 called 's' in the below figure. 's' in R0 is always set to 1,
enabling that R0 can be shifted down in the next clock cycle. 's' in
the remaining locations will be set sequentailly and will be reset at
the end of 128 clock cycles to prevent unnecessary shifts.
(In the each clock cycle following, a new value will be written into
R0 and the old value in R0 will be shifted to R1; and at the same time
's' in R0 will be shifted down from 's' in R1 so that R1 can be shited
in the next clock cycle. Like wise in third clock cycle 's' in R2 is
automatically set from the 's' in R1.)
Input ---------------
--/------------| R0 |[s]
256 ---------------
|
---------------
| R1 |[s]
---------------
:
: [s]
|
---------------
| R127 |
--------------- ---|MUX| --/--
200
The switching switching activity is now 127*(127+1)/2 [=n*(n+1)/2]=
127*64 ==>
64 times higher than the usual switching activity in the array.
So is this worth for saving some wires (127*256) and few gates in the
form of 1 to 128 (256 bit wide)Demux ?
Thanks for your time.
Regards,
Choudhary
Article: 59373Dear People, I have found that by adding the option "-r" to the command line of the Xilinx mapping tools, I can route larger designs than previously possible. Although, this is only through the command-line. Does anybody know a way of doing this through the Xilinx ISE? (It is not available in the options menu under map - I've already checked?) Regards PETE MASHArticle: 59374
hI, I have a project. I need to realise the serial communication between PC and Altera APEX20KE FPGA in c or c++. The function of UART in FPGA is working well. It can send data through uart to PC. For PC, The task is to receive the data from FPGA UART and give the control signal to FPGA through the serial port in pc. My operating system is win2000. Does anybody know how to realise it in c or c++? Thanks. Sarah
Site Home Archive Home FAQ Home How to search the Archive How to Navigate the Archive
Compare FPGA features and resources
Threads starting:
Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z