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Thanks Mike, That's we are already doing. The problem is that I want to synthesize the sopc project before and just perform the P&R during the course to speed up the whole process. So I have to synthesize the sopc project with leonardo or Quartus. In this later case, is it possible to just perform a synthesis with Quartus ? What can I do ? thanks a lot. Stéphane On Mon, 13 Oct 2003 11:17:37 -0700, Mike Treseler wrote: > Mancini Stephane wrote: >> Hi all, >> I'm wondering how to synthesize the VHDL from SOPC Builder of quartus 2.2 >> with Leonardo. >> Indeed, I would like to perform a synthesis separated from the Quartus P&R >> for a course (I have a limited time and doing the both is far too long). >> The idea is to provide students an already synthesized system : they just >> have to complete some peripherals so I can pre-synthesize the whole system >> , students do synthesize peripherals and the pieces are put together for P&R with quartus. > > > Consider leaving the sopc code alone. > > Write and sim the peripheral code separately in my_wrapper.vhd. > In this code, include an unbound component > instance representing connections to the sopc top level entity. > > Compile my_wrapper.vhd in leo to make my_wrapper.edf. > Add my_wrapper.edf to the quartus file list containing the sopc files. > > > -- Mike TreselerArticle: 61851
Hi I had the same with an EPC2. Take a closer look to the routing of the TDO-Line. This line has no pullup or -down resitor. So this was my problem. The TDO-line was to close and to long by an other clock line. i hope it helps. Thomas "Steven" <sleischo@scires.com> schrieb im Newsbeitrag news:c3cc9b26.0310130613.6f053388@posting.google.com... > I have a design with a JTAG chain consisting of APEXII, EPC16UC88, > MERCURY, EPC16UC88. > > I have built the design 3 previous times and been able to program my > boards, no problems. > > Now I have 3 boards, one works fine, one will not accept a .POF file > into the second EPC16 part, and the third will not accept a .POF into > either of the EPC16 parts. > > What happens is Quartus starts erasing the part and after about 45 > seconds kicks out with an error "Error Operation Failed" > > I would think I have a bad part, but that would mean I have 3 bad > parts out of six (and they are ball grids so not easy to swap out). > > I think the JTAG chain is OK, I can do .SOF programs and everything > works great. > > Any ideas on what else to check or try, or could I have a batch of bad > parts???? > > I have tried this under Quartus 2.8 and 3.0. I have also tried using > a jam file under MaxPlus 10.2. I have tried it with different length > cables from my parallel port, I have tried it with different Byte > Blasters, and on different computers. > > > > ThanksArticle: 61852
Does anybody familiar with a development board containing an FPGA with Sun picojava. 10xArticle: 61853
Hi, I am new to linker scripts. Can someone explain me program headers (phdrs) ? Thanks, TomArticle: 61854
Steven- Thanks for the quick response. It seems you corrected the other (similar) bank indication problems. It didn't matter much, but was a bit confusing at first. Jake "Steven K. Knapp" <steve.knappNO#SPAM@xilinx.com> wrote in message news:<bmfb4q$g391@cliff.xsj.xilinx.com>... > The Spartan-3 pinout tables have now been updated to correct this mistake. > The mistake in the data sheet is strictly the bank indication in the pinout > table. The pin name and pin number in the data sheet is correct as is the > PQ208 footprint diagram. > > The correct information for the PQ208 footprint table is available via > either of the following two links. > > Spartan-3 1.2V FPGA Pinout Descriptions (pinout tables only) > http://direct.xilinx.com/bvdocs/publications/ds099-4.pdf > > Spartan-3 Complete Data Sheet (All four modules) > http://direct.xilinx.com/bvdocs/publications/ds099.pdf > > The electronic ASCII-text footprint tables were not affected by this > mistake. > http://direct.xilinx.com/bvdocs/publications/s3_pin.zip > > --------------------------------- > Steven K. Knapp > Applications Manager, Xilinx Inc. > General Products Division > Spartan-3/II/IIE FPGAs > http://www.xilinx.com/spartan3 > --------------------------------- > Spartan-3: Make it Your ASIC > > > "Jake Janovetz" <jakespambox@yahoo.com> wrote in message > news:d6ad3144.0310082043.43d07d9a@posting.google.com... > > Hi folks- > > > > This isn't a significant note, but it seems there is a slight typo in > > the PQ208 package pinout for the Spartan 3. Namely, Bank 1 includes > > the following that I believe should be listed as Bank 0: > > > > IO_L32N_0/GCLK7 > > IO_L32P_0/GCLK6 > > > > Although the suffix (_0) indicates they belong in Bank 0, I wanted to > > make sure they follow Bank 0 power supplies. Also, the table at the > > end of the listing puts two GCLKs in Bank0 and two in Bank1, so that > > seems to reinforce the typo. > > > > Correction? > > > > JakeArticle: 61855
Hi. Well it is not just a bridge, and thats why I cant buy an ASSP. In the Half Bridge application note from Xilinx, there is specific chapter dealing with bridging between several PCI-X cores. I do not need the core to be fully PCI bridge compliant, nor have PCI bridge configuration header within it. What I need is that the core will capture type 1 configuration cycles and reflect them on the user application side of the core. In this way I could have my own logic to translate those transactions to type 0 configuration transaction on other busses I have connected to our FPGA. ThankX, NAHUM Eric Crabill <eric.crabill@xilinx.com> wrote in message news:<3F8AF3B7.BFD97D10@xilinx.com>... > Hello, > > To get a better answer, you'll have to be more specific > about what you want to build. Are you trying to build a > fully compliant PCI(-X) to PCI(-X) bridge? If that is > the case, you should buy an ASSP to do the job. > > The Xilinx PCI and PCI-X LogiCOREs, as you might buy them > over the web, have Type 0 configuration spaces and are not > suitable for compliant bridging applications. However, > there are other options and it depends on what you are > trying to do. > > What exactly are you trying to do? > Eric > > > Hi. > > > > I'm considering Xilinx LogiCORE PCI-X core, and Xilinx > > HalfBridge core for building a PCI-X bridge. > > > > Can anyone share experience with these cores for PCI bridge > > application? Does these cores deal with the address > > translation from "type 1" to "type 0" ? > > > > ThankX > > NAHUMArticle: 61856
Hello, One of the possibility could be due to interference on the JTAG port you can try the following to see if it resolves the problem: 1. Provide a pull up on the JTAG pins 2. Use the security bit, by which the contents cannot be read or changed, the device can only be erased. Regards Sandeep "Dennis Binder" <dennis.binder@ipm.fhg.de> wrote in message news:bmgeum$bvb$1@news.BelWue.DE... > Hello, > > we encounter problems with a XC18v01. > In which way is it possible, that the prom loses > information ? > Most time everything works fine. But after delivering > the mashine to the customer, the content of the XC18v01 has changed. > We have no idea how this can happen. > All the JTAG-Signals of the prom are left open and we supply the > whole electronic with two seperated external power-supplies (3.3V 5V). > 3.3V for FPGA and Prom. > 5V for the digital electronic which interfaces to the FPGA. > > I would be glad if anybody can help ! > > Dennis >Article: 61857
I have VHDL. I want to create a bitfile for a Xilinx XC5210. What tool(s?) do/can I use? I have ISE webpack 6.1, but it does not seem to support this device.Article: 61858
Rick, The IBIS models are based on the foundry spice models, which are pretty mature now, as the same transistors used for the IOs have been manufactured now for almost a year. Just because others have absolutely lousy IBIS models out there does not mean we do: We continually check the quality of the models. Yes, Spartan 3 has preliminary models but only because it is not released to production yet -- it is still int he ES phase. This allows us to make changes easily as we discover issues. So far, no issues with IBIS. Austin rickman wrote: > lecroy wrote: > > > > Surely as hard as you Xilinx guys pushed simulation as the answer for > > this, you would know the details of the S3 models. Are you looking > > into it? Is the part just to new and there is no information > > available at your level? > > No one has responded to my posting here. This is not the sort of > question you can expect a good answer from by the hotline. So unless my > local rep can give me some straight talk, I will assume that the IBIS > models are still very preliminary and not of any real value for > simulation yet. BTW, I am having breakfast with my rep and sales person > today. We'll see what they have to say about the IBIS models and the > partial reconfiguration issues. > > -- > > Rick "rickman" Collins > > rick.collins@XYarius.com > Ignore the reply address. To email me use the above address with the XY > removed. > > Arius - A Signal Processing Solutions Company > Specializing in DSP and FPGA design URL http://www.arius.com > 4 King Ave 301-682-7772 Voice > Frederick, MD 21701-3110 301-682-7666 FAXArticle: 61859
Thanks for the answer. Austin Lesea wrote: > > Rick, > > The IBIS models are based on the foundry spice models, which are pretty > mature now, as the same transistors used for the IOs have been manufactured > now for almost a year. > > Just because others have absolutely lousy IBIS models out there does not > mean we do: We continually check the quality of the models. Yes, Spartan 3 > has preliminary models but only because it is not released to production yet > -- it is still int he ES phase. This allows us to make changes easily as we > discover issues. So far, no issues with IBIS. > > Austin > > rickman wrote: > > > lecroy wrote: > > > > > > Surely as hard as you Xilinx guys pushed simulation as the answer for > > > this, you would know the details of the S3 models. Are you looking > > > into it? Is the part just to new and there is no information > > > available at your level? > > > > No one has responded to my posting here. This is not the sort of > > question you can expect a good answer from by the hotline. So unless my > > local rep can give me some straight talk, I will assume that the IBIS > > models are still very preliminary and not of any real value for > > simulation yet. BTW, I am having breakfast with my rep and sales person > > today. We'll see what they have to say about the IBIS models and the > > partial reconfiguration issues. > > > > -- > > > > Rick "rickman" Collins > > > > rick.collins@XYarius.com > > Ignore the reply address. To email me use the above address with the XY > > removed. > > > > Arius - A Signal Processing Solutions Company > > Specializing in DSP and FPGA design URL http://www.arius.com > > 4 King Ave 301-682-7772 Voice > > Frederick, MD 21701-3110 301-682-7666 FAX -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAXArticle: 61860
Hi all, Could anyone tell me of universities in the US that are strong in IC design and/or DSP design? -- Brad Eckert brad1.methinksnot@tinyboot.comArticle: 61861
"Martin Euredjian" <0_0_0_0_@pacbell.net> wrote in message
news:UjNib.930$wL5.424@newssvr27.news.prodigy.com...
> If you are right in that you cannot mix RPM_GRID with standard grid
> nomenclature, then, does that mean that you must convert all of your old
> RPM's to use RPM_GRID? A top module might contain RPM's built out of
other
> RPM's. How do you deal with that?
No, no, no, no.... You cannot mix the regular RPMs and RPM grids *within
one macro* but should be able to mix the two with complete freedom (in your
UCF, not necessarily the floorplanner).
If you check the constraints guide for the RPM_GRID.... Dang. It's not
there. Okay, if you read the comment in XAPP416, it mentions that
"In addition to the RLOC constraints, one symbol in the
macro must have the following constraint applied:
RPM_GRID = GRID"
The diction makes this a *per macro* constraint. I never intended to imply
that everything must be RPM_GRIDed across your design. Old macros should
drop in and work. If you want to add a multiplier to an existing RPM, then
things aren't pretty but this shouldn't be a problem most people have to
deal with.
Did I miss something and all your macros broke when you included only one
RPM_GRID macro? Mix and match. Go crazy.
- John_H
Article: 61862I had a meeting with my local salesperson, rep and FAE and they got me to take another look at the SpartanXL for the 5 volt tolerant socket on my board. The part looks pretty good in most respects, but there are two flies in the ointment. One is the lack of support in the current tools. I know Xilinx still provides the "classic" tool set which should work ok, but I am not comfortable using a different tool and would have to buy a third party synthesis tool to support this. The other problem is that I would have to use the XCS40XL-5CS280 to get the density in a small package. But they don't offer an industrial temp version in this package. Is there a thermal reason that this package won't support the industrial temp range, or is this just a matter of space on the shelf for yet another chip version? Any way to get around this issue? Is there a spread sheet for calculating the power consumption? I have a design that I can extract data from to drive a power consumption model if I can get a model. -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAXArticle: 61863
Adam, why do you want to use such an old device? Unless you have very special circumstances, it is best to throw away such old parts and design with and for newer devices like Virtex and Spartan. One year in the life of an FPGA equals 15 years in human life. That means your 5210 really belongs in the old folks' home. Rest assured that we still sell XC3000, 4000 and 5200 devices for replacement purposes. But we discourage new designs with them. Newer devices are so much better and cheaper, and supported by better software. Peter Alfke =============== Adam wrote: > > I have VHDL. I want to create a bitfile for a Xilinx XC5210. > What tool(s?) do/can I use? > > I have ISE webpack 6.1, but it does not seem to support this device.Article: 61864
Hi to all, I'm trying to make an electronic dice (3 die). Basically the dice has 3 seven-segment displays and the 3 dice values will run randomly so that we would always get different values combinations. However I tried and was unable to write the program in VHDL . I need help urgently .. Anyone know how to write the program ? Thanks a lot :-)Article: 61865
John, the last time Xilinx printed a data book covering all our programmable devices was in the year 2000. After that, we have decided to mainly rely on the web, on DataSource CDs, and on single-family printed books. Our product lines have expanded so much, and the technical evolution is so fast, that big printed books are incomplete or obsolete the moment they leave the printing press. A CD may be you best choice, and I can send you the newest one (600 MB, equivalent to several thousand printed pages) if you e-mail me your snail-mail address. Peter Alfke ========================= John wrote: > > I would like to obtain a hard copy of the Programmable Logic Design > Handbook (featuring FPGAs and CPLDs). I cannot find one listed on the > Xilinx web site, though I might have missed it. The downloadable pdf > probably works for most people, but I prefer having a book to thumb > through. Thanks, > JohnArticle: 61866
José F. da Rocha <jose_rocha@yahoo.com> wrote in message news:ee806ea.-1@WebX.sUN8CHnE... Hello. I'm new at the FPGA/CPLDs world and I'm currently subscribed to receive Xilinx email communications. I would like to know if is there some FPGA/CPLD incorporating some few analog functions or analog blocks like instrumentation amplifiers, OPerational AMPlifiers/(analog amplification), ADCs (Analog-to-Digital-Converter) and DACs? Thank you very much if you are kindly enough to answer. (jose_rocha@yahoo.com) Take a look at Zetex's TRAC product. See www.zetex.com.Article: 61867
"Amstel" <lange360@hotmail.com> wrote in message news:56f7756d.0310140824.7d8fe744@posting.google.com... > I'm trying to make an electronic dice (3 die). Basically the dice has > 3 seven-segment displays and the 3 dice values will run randomly so > that we would always get different values combinations. However I > tried and was unable to write the program in VHDL . Do you have any idea how incredibly hard this is? I guess you are expecting to use a fast oscillator, and let the dice "roll" very rapidly for as long as someone holds their finger on the button. But of course you need 3 separate oscillators, so that the three dice don't stay in lockstep. Next you need to ensure that the three oscillators don't in any way influence one another. This is amazingly hard, requiring very sophisticated engineering of the oscillators and their power supplies; they will need extremely careful shielding from one another, and you will need to ensure that any inductors in each oscillator's signal path are mutually perpendicular to inductors in the other two oscillators. (Presumably that's why you have been asked for only 3 dice, because adding a fourth would make the mutual-perpendicularity constraint quite hard to achieve in this universe). Once you have your three uncoupled oscillators, you will need to condition the user push button in such a way that it cannot affect the oscillators' behaviour, and it enables the counts in a way that is protected against the inevitable metastability you will see given that the oscillators and pushbutton are all asynchronous. There are also some tricky issues about whether the LED currents may affect the oscillators (via power supply coupling effects) in such a way that the outcome is biased. Oh... and once you've done all that, you have to create the trivial counters, enable logic and 7-segment decode. But I'm sure that you can do that easily, after all the other challenges. It's nice to see people posting these really exciting research-level problems on the group. -- Jonathan Bromley, Consultant DOULOS - Developing Design Know-how VHDL * Verilog * SystemC * Perl * Tcl/Tk * Verification * Project Services Doulos Ltd. Church Hatch, 22 Market Place, Ringwood, Hampshire, BH24 1AW, UK Tel: +44 (0)1425 471223 mail: jonathan.bromley@doulos.com Fax: +44 (0)1425 471573 Web: http://www.doulos.com The contents of this message may contain personal views which are not the views of Doulos Ltd., unless specifically stated.Article: 61868
Mancini Stephane wrote: > The problem is that I want to synthesize the > sopc project before and just perform the P&R during the course to speed up the whole > process. If you set [Quartus II, Assignments, Settings, Mode, Smart Compilation] then the P&R is mainly limited to changes from the previous run. > So I have to synthesize the sopc project with leonardo or > Quartus. Leave the sopc stuff in quartus for synthesis, unless you want to rewrite it. > In this later case, is it possible to just perform a synthesis > with Quartus ? Yes, but it is an Altera-only .vqm netlist, not .edf. [Quartus II, Assignments, Settings, Compiler Settings, Synthesis, save a node level netlsit] And Quartus can't do leo's rtl viewer. You don't need to use leo for your wrapper file unless you want to. > What can I do ? You could benchmark the different methods and pick the best: 1. add the leo netlist wrapper.edf to sopc file list 2. add the source files for wrapper.vhd directly to sopc file list 3. use the source files for wrapper.vhd with the quartus netlist sopc.vqm 4. use the leo netlist wrapper.edf with the quartus netlist sopc.vqm -- Mike TreselerArticle: 61869
Rick, SpartanXL is an XC4000XL-derivative, while Spartan-II is Virtex-derived. That means it is a big generation-step younger, more modern, better supported. All the devices mentioned have 3.3V I/O that are 5-V tolerant. Take a look at the younger parts, they may give you more flexibility. I hate to contradict your FAE :-( Peter Alfke ============= rickman wrote: > > I had a meeting with my local salesperson, rep and FAE and they got me > to take another look at the SpartanXL for the 5 volt tolerant socket on > my board. The part looks pretty good in most respects, but there are > two flies in the ointment. One is the lack of support in the current > tools. I know Xilinx still provides the "classic" tool set which should > work ok, but I am not comfortable using a different tool and would have > to buy a third party synthesis tool to support this. > > The other problem is that I would have to use the XCS40XL-5CS280 to get > the density in a small package. But they don't offer an industrial temp > version in this package. Is there a thermal reason that this package > won't support the industrial temp range, or is this just a matter of > space on the shelf for yet another chip version? Any way to get around > this issue? Is there a spread sheet for calculating the power > consumption? I have a design that I can extract data from to drive a > power consumption model if I can get a model. > > -- > > Rick "rickman" Collins > > rick.collins@XYarius.com > Ignore the reply address. To email me use the above address with the XY > removed. > > Arius - A Signal Processing Solutions Company > Specializing in DSP and FPGA design URL http://www.arius.com > 4 King Ave 301-682-7772 Voice > Frederick, MD 21701-3110 301-682-7666 FAXArticle: 61870
Vinh Pham wrote:
> try searching for "inferring ram" in XST's user manual or on xilinx's web
> site. they should give you a template of how to word your VHDL such that
> XST can properly infer your ram.
Thanks for the tip, I found a synthesis guide on the xilinx website that
provided me with the information I needed.
-- Joe Lawrence
remove the zz's for email
Article: 61871Hi, Jonathan, let me disagree. I would run this with a single 200 MHz oscillator, and drive the indicators with a simple counter ( three mod 6 counters cascaded). The counter goes through all its 216 values once per microsecond, and I am sure that the human hand cannot cheat with fractional microsecond accuracy. Peter Alfke Jonathan Bromley wrote: > > "Amstel" <lange360@hotmail.com> wrote in message > news:56f7756d.0310140824.7d8fe744@posting.google.com... > > I'm trying to make an electronic dice (3 die). Basically the dice has > > 3 seven-segment displays and the 3 dice values will run randomly so > > that we would always get different values combinations. However I > > tried and was unable to write the program in VHDL . > > Do you have any idea how incredibly hard this is? > > I guess you are expecting to use a fast oscillator, and let > the dice "roll" very rapidly for as long as someone holds their > finger on the button. But of course you need 3 separate > oscillators, so that the three dice don't stay in lockstep. > > Next you need to ensure that the three oscillators don't in any > way influence one another. This is amazingly hard, requiring > very sophisticated engineering of the oscillators and their > power supplies; they will need extremely careful shielding > from one another, and you will need to ensure that any > inductors in each oscillator's signal path are mutually > perpendicular to inductors in the other two oscillators. > (Presumably that's why you have been asked for only 3 dice, > because adding a fourth would make the mutual-perpendicularity > constraint quite hard to achieve in this universe). > > Once you have your three uncoupled oscillators, you will need > to condition the user push button in such a way that it cannot > affect the oscillators' behaviour, and it enables the counts > in a way that is protected against the inevitable > metastability you will see given that the oscillators and > pushbutton are all asynchronous. > > There are also some tricky issues about whether the LED > currents may affect the oscillators (via power supply > coupling effects) in such a way that the outcome is > biased. > > Oh... and once you've done all that, you have to create > the trivial counters, enable logic and 7-segment decode. > But I'm sure that you can do that easily, after all the > other challenges. > > It's nice to see people posting these really exciting > research-level problems on the group. > -- > Jonathan Bromley, Consultant > > DOULOS - Developing Design Know-how > VHDL * Verilog * SystemC * Perl * Tcl/Tk * Verification * Project Services > > Doulos Ltd. Church Hatch, 22 Market Place, Ringwood, Hampshire, BH24 1AW, UK > Tel: +44 (0)1425 471223 mail: jonathan.bromley@doulos.com > Fax: +44 (0)1425 471573 Web: http://www.doulos.com > > The contents of this message may contain personal views which > are not the views of Doulos Ltd., unless specifically stated.Article: 61872
Nitin wrote: > I have a question, which I think you people can answer. For my > research, I would like to implement a transmission gate into a FPGA. > Can it be done? If yes could you tell me how? If you need cover voltage levels other than logic '1' and '0' see these guys: http://www.analog.com/ http://www.linear.com/ If you mean to transmit or not transmit specified logic levels in one direction at a time, then an FPGA will work fine. -- Mike TreselerArticle: 61873
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