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> if (EnableDiv3) then Just spotted the typo! Should be (EnableDiv3 = '1').Article: 62276
I just released Confluence 0.7.1, which includes a few minor language improvements and a new installation package. Confluence is a functional programming language for RTL logic design. The Confluence compiler generates synthesizable Verilog and VHDL and cycle-accurate C and Python models. And with 0.7, Confluence also integrates with the open-source SPIN Model Checker to conduct formal verification, random simulation, and equivalence checking. Downloads: http://www.launchbird.com/download.html http://spinroot.com/ Regards, Tom -- Tom Hawkins Launchbird Design Systems, Inc. 952-200-3790 http://www.launchbird.com/Article: 62277
Hi Frank,
Frank wrote:
> I've succesfully build a microblaze system with external interrupt and my
> own IP core (using the opb slave template in the EDK). The interrupt is
> connected to a dip-switch. In the ISR I'm writing some data to my own IP
> core (which is an OPB slave). My OPB slave is reading some other
> dip-switches and put the result to some LEDs (yes I'm using an evaluation
> board ;). So far everything is ok. Now comes the problem: the expected
> behaviour is dependent of the code in the ISR. If I've the following ISR:
>
> void dip_isr(void)
> {
> *(opb_mycore_base) = 0x12345678;
>
> // Write the value of j to the LED
> // XGpio_DiscreteWrite(&gp_out, 0);
>
> #ifdef USE_INTC
> XIntc_mAckIntr(XPAR_MY_INTC_BASEADDR, XPAR_SYSTEM_MY_INT_MASK);
> #endif
> }
>
> it's not working.
Can you define what you mean by "not working"?
> But if I enable the XGpio write, it is working.
And similarly, what do you mean by "working"?
> And at
> last, if I do the XGpio write first and than the write to the OPB slave
> (opb_mycore) it's again not working anymore.
> In all three situations, the
> code is coming in the ISR (I see that, because there is no output at the
> uart anymore, which is done in the main program).
I would hesitate to use that fact as proof that the code is entering the
ISR...
Anyway it almost suggests like you have some issues with the OPB address
decoding in your slave. Either that, or some kind of bus timeout issue
maybe. Have you tried simulating your core?
Also, are you using the IPIF example that comes with edk3.2? Someone
here in our lab very recently had problems with that, the IPIF address
decoding wasn't doing anything like what he expected. When he dropped
IPIF and did the OPB interface manually, it got a lot better.
Regards,
John
Article: 62278"WIlfredo Falc=F3n" <wfalcon@eps.mondragon.edu> wrote in message news:ee80a02.-1@WebX.sUN8CHnE... Hello, In which reports of time can I see the maximum frequency or haw can I to calculate it?. I am working with ISE 5.1i and for the synthesis I use xst. Thanks, Falc=F3n. Choose the "text based post-place and route timing report". This reports the minimum period and the max freq.Article: 62279
dbeberman@earthlink.net (David) wrote in message news:<366a0905.0310230935.1e6ef60@posting.google.com>... > Hi, I've searched the archive for this newsgroup, and read the FAQ. > I'm wondering if anybody can help me locate an 802.11a or g phy VHDL, > Verilog or other implementation. > > Thanks, > > David > dbeberman@earthlink.net This is the FPGA group. We tend to be digital. Are you aware that the phy (as in "physical") tends to be an analog endeavor? Do you mean that you want a MAC (Media Access Controller) to interface to a known external phy? Most manufacturers that present 802.11 solutions do so with chipsets. You may see some single-chip solutions for 802.11a/b/g in the near future but it looks like they aren't out quite yet.Article: 62280
Allan Herriman <allan.herriman.hates.spam@ctam.com.au.invalid> wrote in message news:<219epvsvimu881ldkou9r98n7htdrc4guu@4ax.com>... > On 22 Oct 2003 10:24:06 -0700, Bassman59a@yahoo.com (Andy Peters) > wrote: > > >"David Brown" <david@no.westcontrol.spam.com> wrote in message news:<bn0j25$91g$1@news.netpower.no>... > >> I'm using the downloadable version of ispLever for a verilog project on a > >> Lattice Mach 4 CPLD chip. The software has both Synplify and Leonardo > >> Spectrum available for synthesis. I can build the code (so far, anyway) > >> with either tool. Is there any reason why I should choose one over the > >> other? > > > >Well, the full-up version of Leonardo lets you set Verilog parameters > >from the GUI or from a TCL script, whereas Synplify does not. This > >makes parameterized designs impossible in Synplify, so that tool's > >disqualified until that very important feature is added. (Ummmm, > >haven't parameters been a part of the language since the beginning???) > > Yes, and you have been able to set them (along with VHDL generics) in > Synplify since version 7.3. Ah! So I sent a quick note to QuickLogic asking them when they were going to release a 7.3.x version of Synplify Lite, and I got a note back right away saying, "You can ftp it from [ftp site address]." So I did and it works. So, I take back what I said! It also lets one set `defines from the GUI, too. --aArticle: 62281
Hi Mr. Collins, I sent the complete file to your personal E-mail address. If you have the tools, executing "partgen -v xc3s400fg456" generates an ASCII text file called "3s400fg456.pkg". A snippet from the file is shown below, just to provide some context on the fields. pin PAD2 B4 0 IO_L01N_0/VRP_0 X1Y63 115S 0 pin PAD3 A4 0 IO_L01P_0/VRN_0 X1Y63 115M 0 <type> <pad number> <package pin number> <bank> <pin name> <closest CLB location> <LVDS pair info> <?> My apologies, I didn't see your original reply to the last posting on this thread. --------------------------------- Steven K. Knapp Applications Manager, Xilinx Inc. General Products Division Spartan-3/II/IIE FPGAs http://www.xilinx.com/spartan3 --------------------------------- Spartan-3: Make it Your ASIC "rickman" <spamgoeshere4@yahoo.com> wrote in message news:3F96E9F1.AD9558D5@yahoo.com... > Marc Baker wrote: > > > > rickman wrote: > > > > > "Steven K. Knapp" wrote: > > > > > > > > The Spartan-3 pinout tables have now been updated to correct this mistake. > > > > The mistake in the data sheet is strictly the bank indication in the pinout > > > > table. The pin name and pin number in the data sheet is correct as is the > > > > PQ208 footprint diagram. > > > > > > > > The correct information for the PQ208 footprint table is available via > > > > either of the following two links. > > > > > > > > Spartan-3 1.2V FPGA Pinout Descriptions (pinout tables only) > > > > http://direct.xilinx.com/bvdocs/publications/ds099-4.pdf > > > > > > > > Spartan-3 Complete Data Sheet (All four modules) > > > > http://direct.xilinx.com/bvdocs/publications/ds099.pdf > > > > > > > > The electronic ASCII-text footprint tables were not affected by this > > > > mistake. > > > > http://direct.xilinx.com/bvdocs/publications/s3_pin.zip > > > > > > Steven, > > > > > > I am looking at partial/modular reconfiguration in Spartan 3 and I > > > realize that there are some issues with IO that I am not sure how to > > > resolve. To get an understanding of how to approach the problem I need > > > to know what IO pads and pins are mapped to what CLB columns. I am > > > looking at using the XC3S400 in the 456 pin BGA package. Where can I > > > get info on how the IOs are mapped to the CLB columns? > > > > The relative location of pins to CLBs can be seen graphically in PACE or put into > > a text file using "partgen -v xc3s400fg456" > > I think you have a leg up on me. I am not familiar with a program > called PACE. I am guessing that is the chip editor? If so, I do not > currently have the full ISE tools and so do not have the chip editor. > How else can I get this file? > > -- > > Rick "rickman" Collins > > rick.collins@XYarius.com > Ignore the reply address. To email me use the above address with the XY > removed. > > Arius - A Signal Processing Solutions Company > Specializing in DSP and FPGA design URL http://www.arius.com > 4 King Ave 301-682-7772 Voice > Frederick, MD 21701-3110 301-682-7666 FAXArticle: 62282
It seems I have a strange problem with my timing constraints, I have recently generated a tsi report using the xilinx trace tool(using ISE 5.2), trce -tsi file.tsi file.ncd file.pcf -v 5 -u 5 -skew -o file.v.twr The report states that a considerable number of nets in our design fall under the constraint "Unconstrained path analysis". We have multiple clock domains in our design so I initially assumed that the unconstrained nets would be on the synchronisation buffers (which might not be completely covered by the period constraints we have assigned for all of our clocks), however when I checked the offending nets I found that many reffered to FFS whose input and output connections were all on the same clock domain. I am unsure at this stage how these nets got into the unconstrained section as their inputs and outputs only feed FFS on the same domain. The reason this is a problem is that there is a constraints intersection issue between the unconstrained section and my other constraints. DenisArticle: 62283
Based on feedback from our UNIX (Solaris, Linux and HP) users, we have intentionally made our UNIX installs simple and script based. UNIX environments can be diverse and a script based approach allows power users to step in and fix things as needed to let them do their job, rather than wait on factory support for trivial items. A script based approach has also proven to be very robust and has virtually eliminated all support calls for installation issues. Also based on feedback from our UNIX users we have invested substantial resources in improving our command line interfaces and procedural (Tcl based) scripting capabilities in Quartus II 3.0 and in the upcoming releases. More on this in a future post. As usual we welcome your feedback and in helping make Quartus a better product for you. - Subroto Datta Altera Corp. "Petter Gustad" <newsmailcomp6@gustad.com> wrote in message news:87smljd8i6.fsf@zener.home.gustad.com... > uselinux2000@yahoo.com (linux user) writes: > > > > Altera has very talented engineers, and there is no doubt in my > > mind that very soon a nice install, possibly similar to the one of > > Open Office (GUI based) will be available for Linux. > > I've been a Linux user since 1993 and I'm very happy to see that Linux > support from the major FPGA vendors is improving. > > However, I would like Altera and Xilinx to spend their efforts on other > things than a GUI based install program. I recall all the problems I > have had over the years with the Xilinx GUI based install program > under Solaris. It would sit there for days flashing cute ads without > installing anything :-( A simple tar would done the job. Of course you > most likely need a way of specifying which devices and parts to > install, but that's about it. Sometimes I install Linux software on > file servers which don't even have X11. > > I would rather have better scripting capabilities, support for > distributed processing (e.g. synthesis and place and route using a > cluster to improve throughput), device programming support under > Linux, Opteron 64-bit support, etc. > > > > 4) Suse 9.0: did anyone try? > > I have tried on a SuSe 8 AMD64 system. Quartus II 3.0SP1 bails out > with the message: > > Unknown Linux processor > MWARCH: Undefined variable. > > But I think it should be possible to get it to run by hacking the > scripts so that it will find its dynamic libraries, etc. > > Petter > > -- > A: Because it messes up the order in which people normally read text. > Q: Why is top-posting such a bad thing? > A: Top-posting. > Q: What is the most annoying thing on usenet and in e-mail?Article: 62284
Petter, Your 2 cents and several more from our customers big and small, have added up to a full dollar. Take a look at AN 312: http://www.altera.com/literature/an/an312.pdf which is fully supported in Quartus II 3.0. This is the new Tcl API which Altera will support, document and add to going forward. It addresses the issues you have mentioned below. The old API will also be supported for backwards compatibility, but it is recommended that new projects use the new Tcl API exclusively. We have added more functions than the ones listed in App Note 312 for the next version of Quartus. Some of these are: project_new project_open is_project_open project_close project_exists project_archive project_restore set_project_settings get_project_settings project_settings_exist set_parameter get_parameter get_all_parameters set_global_assignment get_global_assignment get_all_global_assignments set_instance_assignment get_instance_assignment get_all_instance_assignments set_location_assignment get_location_assignment export_assignments create_base_clock create_relative_clock foreach_in_collection set_multicycle_assignment set_timing_cut_assignment and the parameters to these functions have a -keyword <value> syntax. They are not position dependent anymore. To make it easy for new users to learn this API, the entire Quartus Project can be written out as a Tcl script (of course from the GUI :-), archived and used to recreate the project from scratch each time. Regards, Subroto Datta - Altera Corp. "Petter Gustad" <newsmailcomp6@gustad.com> wrote in message news:87oew7d5zt.fsf_-_@zener.home.gustad.com... > Petter Gustad <newsmailcomp6@gustad.com> writes: > > > I would rather have better scripting capabilities, support for > > I prefer to have my scripts under a source control system to be able > to generate reproducible results. Not a designs which accidentally did > or did not work because somebody on the project checked off an option > several levels down in a GUI dialog box(1) (if DUI is "driving under > influence", what is GUI?). For floorplanners and waveform viewers I > use GUI's, but for plain synthesis, place and route, etc. I prefer > scripts. > > I would like to say that Altera have spend quite a bit of effort > putting scripting capabilities into Quartus. Quartus have TCL support, > but the way you write your "code" is kind of weird: > > project add_assignment $top "" "" $clk GLOBAL_SIGNAL ON > > In order to check that the command had succeeded you have to check if > the above command returned something like "assignment made". It also > seems that the names and values for the various assignments might > change from different Quartus releases. > > In later versions of Quartus Altera has added several smaller tools > which do synthesis and elaboration, place and route, timing analysis, > etc. This is good, even though I can't really see why bash is more > suited than TCL to run the various commands/tools (assuming you make > tclsh do dynamic linking). > > However, these tools seem to use a CSF (compiler settings file) to > specify the various options to the different tools. This is a plain > text file. What I don't like about this approach is that you loose the > scripting ability. Of course you can write your own programs to > generate these files. What I fear is that their format might change in > future releases (please prove me wrong on this). > > What I would like is a *standard documented API* for the scripts. For > the project assignment mentioned above I would like to have a command > called something like "set_global_clock_signal $clk". If this command > returned 0 (or some other predefined value) it has succeeded. > Otherwise, I could a verbose error message by calling some other > command (e.g. with the command name and result code as arguments). > > It would have been even better if the vendor would proved different > scripting interfaces like TCL, Guile, Scheme, Perl, etc. to their > tools so the users could pick their favorite scripting language. If > the vendor provided the C API then users or others could generate a > shell (they could provide TCL as a minimum or example) for their > favorite language. > > Just my 2¢. > > Petter > 1) CSF (compiler settings files) would of course solve this issue. > > -- > A: Because it messes up the order in which people normally read text. > Q: Why is top-posting such a bad thing? > A: Top-posting. > Q: What is the most annoying thing on usenet and in e-mail?Article: 62285
On Tue, 21 Oct 2003, ted wrote: > Jaroslaw Guzinski <jarguz@sunrise.pg.gda.pl> wrote in message news:<Pine.GSO.4.58.0310210953060.27819@sunrise.pg.gda.pl>... > > In laboratory I have few boards with Altera Flex600. Boards are connected > > with PC using ByteBlaster. On PC I have Win98 OS. On the all PC is the > > same software. > > Problem is that on some computers after configuring ALTERA device after > > some time (sometimes very short) project in Altera is deleteted. > > How to solve that problems without disconnecting ByteBlaster after > > programming? > > > > > We had a similar problem some time ago. We suspected the PC pokes the > printer port every so often (something to do with polling > peripherals??), causing the nStatus line to reset. > > We much reduced the problem by removing the LPT1 entry in the PCs > device list, so that the PC doesn't know there is a printer port. YOu > could also try adding a toggle switch on the nStatus line betweeh the > ByteBlaster and the target. > I have removed th LPT port from device list but then I can not programing in Max+PlusII. PC doesnt see LPT port but Max+PlusII also doesnt se it. Jaroslaw GuzinskiArticle: 62286
>My design also has the following elements, which of these couldn't get >squeezed into a CPLD? > >4046 PLL's (Phase comparator 2) >various Comparators I suggest that you put that on the back burner to start with. You will have to read the data sheets for the CPLDs you are interested in, probably many times. While you are doing that, keep an eye out for things that match the data sheets of the parts you are trying to replace. Basically, CPLDs/PALs work great for traditional digital problems. That is: clumps of FFs (state machines, counters) have a max frequency FFs have setup/hold and clock to out gates/logic have prop times All that gets complicated by routing/placement. For the simple devices you can generally do it in your head. If you want to do analog-ish things, you have to find a circuit that will work given the specs you can find in the data sheet. (Sometimes you have to use your imagination and/or read between the lines.) If you can find the specs you need, then you can build your circuit. But I doubt if you will find much that helps for PLLs or comparators. -- The suespammers.org mail server is located in California. So are all my other mailboxes. Please do not send unsolicited bulk e-mail or unsolicited commercial e-mail to my suespammers.org address or any of my other addresses. These are my opinions, not necessarily my employer's. I hate spam.Article: 62287
I have always used a counter clocked on the global clk, and then used one of
the signals
that make up the counter's vector as my divided clk signal.
e.g.
signal cnt: std_logic_vector(7 downto 0);
process(...)
....
if rising_edge(clk) then
cnt<=cnt+1;
....
end;
--divided clk
dclk<=cnt(4);
How does the above code differ in terms of reliability or good code practice
too;
signal n: integer;
process(...)
....
if rising_edge(clk) then
if rst='0' or n=10 then
n<=0;
else
n<=n+1;
end if;
end if;
end process;
d_clk<='0' when n<=5 else '1';
....
Both produce divided clocks.
Matt
"Peter Molesworth" <noemail@anonymous.net> wrote in message
news:oprxidmzi40ve4v7@news.tiscali.co.uk...
> > Divided clock seems synchronous to original clk in terms it is stable on
> > clk
> > edage. On the other hand, synchronous signals should switch
simultaneusly
> > while divided signal is calculated on the clk egdage; hence, it switches
> > after Thold and the condition is not met. I understand principles of
> > asynchronous communication. Should I treat divided clock as an
> > asynchronous
> > clock domain? Any references are appretiated.
> >
> >
>
> Valentin,
>
> For all but the simplest of designs divided clocks should be treated as
> asynchronous and avoided if possible. There are several reasons for this.
>
> 1) Your divided clock will have a small delay relative to the real clock.
> If you use this to clock a register which takes in a signal clocked from
> the original clock domain it may be possible for the setup/hold to be
> violated or data to be taken when it shouldn't have been (i.e a clock
> early). I think you were implying this above.
>
> 2) If you have logic which works accross the two clock domains e.g. data
> clocked from main clock domain goes through logic and is registed on
> divided clock domain or vice-versa then the synthesis tool may have a hard
> time performing optimization on logic in that part of the design.
>
> 3) Unless you have spare high-speed global resources in your design and
> the target technology allows the connection of a register output onto
> these nets (most modern fpga's are okay with this!) then the divided clock
> may get routed on the normal routing nets. If you have lots of registers
> driven from the divided clock the fanout may start to become significant
> and hence the skew between the clock domains will get larger. If the skew
> starts to become significant it then becomes more difficult to ensure that
> the design will work over all temperature/voltage conditions as this will
> introduce skew between registers on the divided domain aswell as between
> the divided and main clock domain. To overcome this the
> synthesis/place&route tools may try to insert buffers to split down the
> net. This may in turn introduce more skew between some registers on your
> divided net.
>
> So to overcome these issues I would suggest trying alternative method of
> coding to reduce this problem to a minimum. The way I do things if I want
> a slower clock is as follows:
>
> For example, say I want a clock that is 1/3 the system clock, I would
> create a 2-bit counter that counts 0 to 2 and rolls over. When the counter
> equals 2 a signal EnableDiv3 is asserted to '1' (and is '0' for all other
> values). I then use this signal as a synchronous enable to the registers I
> want to run a 1/3 speed but still clock the registers off the system
> clock.
>
> EnableGen : process (nReset, Clock)
> begin
> if (nReset = '0') then
> EnableCount <= 0;
> EnableDiv3 <= '0';
> elsif rising_edge (Clock) then
> if (EnableCount = 2) then
> EnableCount <= 0;
> EnableDiv3 <= '1';
> else
> EnableCount <= EnableCount + 1;
> EnableDiv3 <= '0';
> end if;
> end if;
> end process;
>
> SomeRegister : process (nReset, Clock)
> begin
> if (nReset = '0') then
> MySignalReg <= '0';
> elsif rising_edge (Clock) then
> if (EnableDiv3) then
> MySignalReg <= MyDataValue;
> else
> MySignalReg <= MySignalReg;
> end if;
> end if;
> end process;
>
> This solves 1) and 2) above. For item 3) there is still the problem of
> high fan-out on the enable signal. This will be solved by the
> synthesis/place&route tool by inserting buffers. However, in this case the
> registers are still clocked by the system clock so any skew on enable will
> be okay so long as it dosen't violate setup/hold at the destination
> registers.
>
> I hope this is what you were asking for. If you need anything else please
> let me know.
>
> Cheers,
>
> Pete.
Article: 62288Hi everyone, Thanks a lot for showing interest in what I am doing. And I am really sorry for replying so late. Actually we are trying to implement a bypass bi-directional MOSFET transistor in a FPGA for bus purposes, which does not need a signal that controls the direction of signal flow, and acts like a switch. The transistor connects it's 2 terminals (Source and Drain) when enabled and allows signal flow in either direction depending on the strong value on a terminal. And tri-states it when disabled. Do you have any information in this regard. Actually as a part of my on-going research, I am faced with a new problem of implementing multi-valued logic in a FPGA which actually is an intricate part of the above issue of implementation of a MOSFET in a FPGA. Does anyone have information in this regard? Any types of comments or information is welcome. Does Xilinx provide such a facility? I am really thankful to Mr Rick, Mr. Mike and Mr. Jim for showing interest in this topic Thanks for all the help. I am looking forward for more mails on this issue. Thanks NitinArticle: 62289
vboykov@yandex.ru (vladimir) wrote in message news:<d6aed45c.0310220401.6fc8c49d@posting.google.com>... > www.hightech-td.com Try download it else.Article: 62290
Try use TBGenerator (www.hightech-td.com).
Jim Lewis <Jim@SynthWorks.com> wrote in message news:<3F9443C2.1060804@SynthWorks.com>...
> If you want to make a general purpose subprogram for
> testbenches and put it in a pacakge, you must have
> all of the IO on the subprogram interface. As a
> general rule of thumb for subprogram IO class
> use the following:
>
> Inputs:
> ------
> From UUT: Make them signals
> In general:
> If you use signal property ('event) must be a signal,
> otherwise make it a variable.
>
> Outputs, InOuts:
> ----------------
> To UUT: Make it a signal
> To process/other subprogram: variable (so value updates immediately)
> For synthesis:
> usually used directly in architecture, so make it a signal
>
> You can cheat temporarily by putting the subprogram declaration
> in the process, but once you have more than one test architecture
> this means you will have to multiple copies of your testbench.
>
> Cheers,
> Jim Lewis
> p.s. We have are offering our Comprehensive VHDL Introduction
> class in Huntsville, AL next week and we cover stuff just like
> the above. Details are at:
> http://www.synthworks.com/public_vhdl_courses.htm
> --
> ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
> Jim Lewis
> Director of Training mailto:Jim@SynthWorks.com
> SynthWorks Design Inc. http://www.SynthWorks.com
> 1-503-590-4787
>
> Expert VHDL Training for Hardware Design and Verification
> ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
>
>
>
>
> Dan Kuechle wrote:
>
> > I'm trying to use a subroutine (subprogram procedure) in my testbench to
> > (eventually) simulate processor reads and writes. When I compile and try to
> > simulate(Xilinx ISE 6.1i and Modelsim) I get "# ERROR: testbench.vhd(34):
> > Cannot drive signal in3 from this subprogram." Any idea why? Can it be
> > corrected?
> >
> > Thanks
> >
> > Dan
> >
> >
> > LIBRARY ieee;
> > USE ieee.std_logic_1164.ALL;
> > USE ieee.numeric_std.ALL;
> >
> > ENTITY testbench IS
> > END testbench;
> >
> > ARCHITECTURE behavior OF testbench IS
> > COMPONENT tb_subroutine
> > PORT( clk : IN std_logic;
> > reset : IN std_logic;
> > in1 : IN std_logic;
> > in2 : IN std_logic;
> > in3 : IN std_logic;
> > out1 : OUT std_logic;
> > out2 : OUT std_logic;
> > out3 : OUT std_logic
> > );
> > END COMPONENT;
> >
> > SIGNAL clk : std_logic;
> > SIGNAL reset : std_logic;
> > SIGNAL in1 : std_logic;
> > SIGNAL in2 : std_logic;
> > SIGNAL in3 : std_logic;
> > SIGNAL out1 : std_logic;
> > SIGNAL out2 : std_logic;
> > SIGNAL out3 : std_logic;
> >
> > procedure set_in3
> > --subroutine
> > begin
> > in3 <= '1';
> > end procedure set_in3;
> >
> > BEGIN
> >
> > gen_clk : process(clk)
> > begin
> > if (clk = '0') then
> > clk <= '1' after 6.25 ns; --12.5 period = 80mhz
> > else
> > clk <= '0' after 6.25 ns;
> > end if;
> > end process;
> >
> > uut: tb_subroutine PORT MAP(
> > clk => clk,
> > reset => reset,
> > in1 => in1,
> > in2 => in2,
> > in3 => in3,
> > out1 => out1,
> > out2 => out2,
> > out3 => out3
> > );
> >
> > -- *** Test Bench - User Defined Section ***
> > tb : PROCESS
> > BEGIN
> > reset <= '1';
> > in1 <= '0';
> > in2 <= '0';
> > in3 <= '0';
> > wait for 50 ns;
> > reset <= '0';
> > wait for 50 ns;
> > in2 <= '1';
> > wait for 50 ns;
> > in1 <= '1';
> > wait for 50 ns;
> > set_in3; --call
> > subroutine
> > wait for 50 ns;
> > in3 <= '0';
> > in2 <= '0';
> > in1 <= '0';
> > wait for 50 ns;
> >
> > END PROCESS;
> > -- *** End Test Bench - User Defined Section ***
> >
> > END;
> >
> >
Article: 62291TBGenerator - generates test benches which was described by Verilob or VHDL. Works with inout ports. Additional tools - convert time to frequency and frequency to time, create component declaration. Useful examles source code Verilog, VHDL, PLI, FLI, Tcl/Tk embedded interpreter. www.hightech-td.comArticle: 62292
Hi
Thanks for reading this. I have a schematic (top level) design
which has a data bus. This data bus has had IOB(63:0) and separate
Ibuf(63:0) and
OBUF(63:0) attached to an IO marker (bidirectional) and NOTHING else
in the
schematic. I get an error on synthesis that says: Signal is stuck at
GND
WARNING:Xst:528 - Multi-source in Unit <bcpm_top> on signal
<data_obuf_15>
not replaced by logic
Signal is stuck at GND
WARNING:Xst:528 - Multi-source in Unit <bcpm_top> on signal
<data_obuf_14>
not replaced by logic
Signal is stuck at GND
WARNING:Xst:528 - Multi-source in Unit <bcpm_top> on signal
<data_obuf_13>
not replaced by logic
Signal is stuck at GND
WARNING:Xst:528 - Multi-source in Unit <bcpm_top> on signal
<data_obuf_12>
not replaced by logic
Signal is stuck at GND Anybody seen this error??? I am using
primitives and not macros for the IOBufs Also I had created this
schematic under 4.1 and foolishly upgraded to take "advantage" 5.1...
the schematic synthed and routed fine under 4.1 Any Ideas??? Thanks;
Article: 62293Nitin <nitinyogi@hotmail.com> wrote in message news:b0ae9f4d.0310240018.2f66c14d@posting.google.com... > Hi everyone, > > Thanks a lot for showing interest in what I am doing. And I am > really sorry for replying so late. Actually we are trying to implement > a bypass bi-directional MOSFET transistor in a FPGA for bus purposes, > which does not need a signal that controls the direction of signal > flow, and acts like a switch. The transistor connects it's 2 terminals > (Source and Drain) when enabled and allows signal flow in either > direction depending on the strong value on a terminal. And tri-states > it when disabled. Do you have any information in this regard. This sounds like IDT's quickswitch functionality. Have a look at... http://www.idt.com/products/pages/Bus_Switches-PL115_Sub293_Dev412.html ...for more details. Nial Stewart ------------------------------------------------ Nial Stewart Developments Ltd FPGA and High Speed Digital Design www.nialstewartdevelopments.co.ukArticle: 62294
Stupid OE shows only your last message. Which newsreader do you use?Article: 62295
"Valentin Tihomirov" <valentin@abelectron.com> wrote in message news:3f991c5a$1_1@news.estpak.ee... > Stupid OE shows only your last message. Which newsreader do you use? Newsreader has nothing to do with this, it's the news server that you are connected to. You might try talking to your IP about the issue or use one of the free servers. A very good one is news.individual.net (someone recommended it to me earlier on this group). The only problem with it is that you have to register and it seems that they actually have a live person who does the registrations, so it may take 1-2 days. Their site is http://www.individual.net/ /MikhailArticle: 62296
"Nicholas C. Weaver" <nweaver@ribbit.CS.Berkeley.EDU> wrote in message news:bn6gq8$15i5$1@agate.berkeley.edu... > Luddite Me, who's forgotten most of the Verilog he once knew, needs to > start doing serious HDL-based design. No more schematic-orphans for > me. > > Are there good reference books for Verilog or VHDL? Ideally, > something akin to Java in a Nutshell (Java), the Post Script Red > (language reference) and Blue (tutorial and cookbook) series, or K&R? > > Thanks. > -- > Nicholas C. Weaver nweaver@cs.berkeley.edu This may be of use: http://www.vol.webnexus.comArticle: 62297
Do you have an Altera ByteblasterMV an do you want to programm the Configuration Device EPCS1 or EPCS4 for Cyclone ?? Use this: Make a new VisualBasic Form with one ProgrammButton Command1 and one CommonDialog1 add the source code below download the InpOut32.DLL from http://www.logix4u.cjb.net/ Modfify your Byteblaster/ByteblasterMV: connect PIN4 of your Printer SUBD25 Connector to PIN17 (2A4) of the 74HC244. Use the same Pull Up Resistors like on the other Pins. Disconnect the Pin from GND. connect PIN3 of 74HC244 to Pin8 of the JTAG Connector. Connect PIN4 of the JTAG to PIN6 to disable the cyclone device. ---------------- Option Explicit Private Declare Function Inp Lib "inpout32.dll" Alias "Inp32" (ByVal PortAddress As Integer) As Integer Private Declare Sub Out Lib "inpout32.dll" Alias "Out32" (ByVal PortAddress As Integer, ByVal Value As Integer) Dim bytebuffer(524288) As Byte Const ASNCONF = 2 Const ASD = 0 Const ASDIN = 64 Const ASCLK = 1 Const ASCS = 4 Const WRITE_ENABLE = 6 Const WRITE_DISABLE = 4 Const READ_STATUS = 5 Const READ_BYTES = 3 Const READ_ID = &HAB Const WRITE_STATUS = 1 Const WRITE_BYTES = 2 Const ERASE_BULK = &HC7 Const ERASE_SECTOR = &HD8 Private Sub Command1_Click() Dim filelength As Long Dim l As Long Dim ok As Boolean Dim rs As Byte Dim b As Byte Dim chipid As Byte For l = 0 To 524287 bytebuffer(l) = 255 Next l chipid = ReadID If chipid = 16 Then MsgBox "ChipID: EPCS1" Else If chipid = 17 Then MsgBox "ChipID: EPCS4" Else MsgBox "no configuration device found" Exit Sub End If End If CommonDialog1.CancelError = True On Error GoTo ErrHandler CommonDialog1.Flags = cdlOFNHideReadOnly CommonDialog1.Filter = "Alle Dateien (*.*)|*.*|" & "AS File (*.rbf)|*.rbf" CommonDialog1.FilterIndex = 2 CommonDialog1.ShowOpen Open CommonDialog1.FileName For Binary Access Read As #1 Seek #1, 1 filelength = LOF(1) For l = 0 To (filelength - 1) Get #1, l + 1, bytebuffer(l) Next l Close #1 WriteEnable EraseBulk Do rs = ReadStatus Loop Until (rs Mod 2) = 0 For l = 0 To (filelength - 1) WriteEnable b = bytebuffer(l) WriteB l, b Do rs = ReadStatus Loop Until (rs Mod 2) = 0 If (l Mod 100) = 0 Then Form1.Caption = "programming: " + Str(1 + l * 100 \ filelength) + "%" DoEvents End If Next l ok = True For l = 0 To (filelength - 1) If bytebuffer(l) <> ReadB(l) Then ok = False End If If (l Mod 100) = 0 Then Form1.Caption = "verifing: " + Str(1 + l * 100 \ filelength) + "%" DoEvents End If Next l If ok Then MsgBox "OK" Else MsgBox "NOT OK" End If Exit Sub ErrHandler: MsgBox "File Open Error" Close #1 End Sub Private Sub Form_Load() enablePar End Sub Private Sub ChipDeSelect() Out &H378, ASCS End Sub Private Sub ChipSelect() Out &H378, 0 End Sub Private Sub enablePar() Out &H37A, 2 End Sub Private Sub disablePar() ChipDeSelect Out &H37A, 0 End Sub Private Sub Form_Unload(Cancel As Integer) disablePar End Sub Private Sub WriteByte(b As Byte) Dim i As Integer Dim bit As Byte For i = 1 To 8 If b > 127 Then bit = ASDIN b = b - 128 Else bit = 0 End If b = b * 2 Out &H378, bit 'DoEvents Out &H378, bit + ASCLK 'DoEvents Next i End Sub Private Function ReadByte() Dim b, hb As Byte Dim i As Integer Dim bit As Byte b = 0 For i = 1 To 8 Out &H378, 0 'DoEvents b = b * 2 hb = Inp(&H379) hb = hb Mod 32 If (hb > 15) Then bit = 1 Else bit = 0 End If Out &H378, ASCLK 'DoEvents b = b + bit Next i ReadByte = b End Function Public Function ReadStatus() As Byte ChipSelect WriteByte READ_STATUS ReadStatus = ReadByte ChipDeSelect End Function Public Sub WriteEnable() ChipSelect WriteByte WRITE_ENABLE ChipDeSelect End Sub Public Sub WriteDisable() ChipSelect WriteByte WRITE_DISABLE ChipDeSelect End Sub Public Sub EraseBulk() ChipSelect WriteByte ERASE_BULK ChipDeSelect End Sub Public Sub WriteB(ad As Long, b As Byte) ChipSelect WriteByte WRITE_BYTES WriteByte (ad \ 65536) Mod 256 WriteByte (ad \ 256) Mod 256 WriteByte (ad \ 1) Mod 256 WriteByte b ChipDeSelect End Sub Public Function ReadB(ad As Long) As Byte ChipSelect WriteByte READ_BYTES WriteByte (ad \ 65536) Mod 256 WriteByte (ad \ 256) Mod 256 WriteByte (ad \ 1) Mod 256 ReadB = ReadByte ChipDeSelect End Function Public Function ReadID() As Byte ChipSelect WriteByte READ_ID WriteByte 0 WriteByte 0 WriteByte 0 ReadID = ReadByte ChipDeSelect End FunctionArticle: 62298
Recently I have updated my Picoblaze (tm Xilinx) development tool pBlazIDE and added some documentation. Additionally I have published some example code and demonstration files. Please feel free to check this out. Its all freeware. Check under 'Tools'. Regards, Henk van Kampen www.mediatronix.comArticle: 62299
"Subroto Datta" <sdatta@altera.com> writes:
> Your 2 cents and several more from our customers big and small, have added
> up to a full dollar. Take a look at AN 312:
> http://www.altera.com/literature/an/an312.pdf
Thank you for the link. I've read some previous documentation on
Quartus scripting, but I have not seen this one yet.
> which is fully supported in Quartus II 3.0. This is the new Tcl API which
> Altera will support, document and add to going forward. It addresses the
It looks like Altera is going in the right direction.
> and the parameters to these functions have a -keyword <value> syntax. They
> are not position dependent anymore. To make it easy for new users to learn
Great. Are all the assignment keywords documented anywhere?
If not in some cases it would have been easier to have a command
wrapper around the setting. I used the APP note as a guide to write an
improved quartus_sh script. I'm adding files using:
foreach f $flist {
set_global_assignment -name VERILOG_FILE $f
}
My problem is that most of the files will include another. So I get an
error saying that it can't find the include file. I had no idea what
the assignment name for this command was. If it was a command I could
have done "info commands" and search through the output and guess
which one did the job and run it with a -help argument to learn about
its parameters etc.
The way I figured out was to launch the GUI and generate a TCL script
to learn that the -name option I was looking for was USER_LIBRARIES...
Petter
--
A: Because it messes up the order in which people normally read text.
Q: Why is top-posting such a bad thing?
A: Top-posting.
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