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Hi Rajeshwary,
The uniSIM library is for simulation. It has verilog models of all the
primitives that, in your case, comprise a Spartan II, so that your simulator
knows what each primitive does. You don't want or need to synthesise this,
so don't include it in your compile list.
HTH, Syms.
<Rajeshwary> wrote in message news:ee80e57.-1@WebX.sUN8CHnE...
We are trying to implement a decoder design on a Spartan II(2s200), and when
I run the Synthesize process, the message window shows that all verilog
modules are being compiled, however the process seems to take forever when
it is trying the compile the unisim_comp.v file which is provided by ISE.
Can anybody guess what the problem could be and/or the possible solution.
Thanks in advance
Article: 62751> physical synthesis: > what do you mean ? In the FPGA world this means applying the same synthesis techniques like register re-timing, re-structuring and re-synthesis on a place and routed design. Have a look at Mentor's Precision Physical. I suspect that RTL, Place&Route and Physical will slowly merge into 1 synthesis engine. Given the "close to useless" estimates from wireload models this can't be to soon enough :-) Hans. www.ht-lab.com > regards, > fe > > "Nagaraj" <nagaraj_c_s@yahoo.com> wrote in message > news:91710219.0311050420.679a7a14@posting.google.com... > > I meant much more. For a detailed design flow, including code > > coverage, DFT, physical synthesis, etc. > > > > regards, > > nagaraj > > > > Mike Treseler <tres@tc.fluke.com> wrote in message > news:<3FA83665.9030100@tc.fluke.com>... > > > 1. Design entry > > > Tool1: emacs vhdl-mode, verilog mode > > > Tool2: Quartus block diagram > > > 2. Simulation > > > Tool1: Modelsim > > > Tool2: Aldec > > > 3. Synthesis > > > Tool1: Leo Spec > > > Tool2: Synplify Pro > > > Tool3: Quartus > > > Tool4: XST > > > 4. Place and Route > > > Tool1: Xilinx Place & Route + static timing > > > Tool2: Quartus Place & Route + static timing > > > > > > -- Mike Treseler > >Article: 62752
In article <3Tvqb.286$QC3.2240@newsfep4-glfd.server.ntli.net>, Hans <hansydelm@no-spam-ntlworld.com> wrote: >In the FPGA world this means applying the same synthesis techniques like >register re-timing, re-structuring and re-synthesis on a place and routed >design. Have a look at Mentor's Precision Physical. I suspect that RTL, >Place&Route and Physical will slowly merge into 1 synthesis engine. Given >the "close to useless" estimates from wireload models this can't be to soon >enough :-) >Hans. The problem with retiming in the FPGA world is not the delay model: You can do it after placement and have a really nice delay model, but the initial conditions model. If you say "keep initial conditions/Global set-reset", its a pain in the butt and needs to be before placement. If you say "Screw initial conditions/global set-reset" it becomes easy and nicely effective, and the designer just has to have his state machine take a startup/reset signal. -- Nicholas C. Weaver nweaver@cs.berkeley.eduArticle: 62753
Timothy Miller wrote:
>> BTW, I only looked quickly on the macro and it looks rather
>> complicated. Notice that you probably would better use arrays in
>> combination with the split() function. (What NEdit version do you
>> have? - latest would be 5.4)
>
> I'm not sure what you think I should use arrays for. Could you be
> more specific?
OK, I hacked quickly a much simpler alternative macro together that
does the same as yours (it doesn't consider tabs nor comments though):
define jf_test {
start = search("(", $cursor, "backward")
if (start != -1) {
start = start + 1
}
else {
beep()
return
}
end = search(")", $cursor)
if (end == -1) {
return
}
end = end - 1
text = get_range(start, end)
port = split(text, "(?n\\s*,\\s*)", "regex")
indent = search_string(port[0], "\\S", 0, "regex")
blank = jf_indent(indent)
newtext = ""
extent = 0
port[0] = substring(port[0], indent, length(port[0]))
for (i = 0; i < port[]; i++) {
extent = max(extent, length(port[i]))
}
for (i = 0; i < port[]; i++) {
newtext = newtext blank "." port[i] jf_indent(extent -
length(port[i]))\
blank "(" port[i] "),\n"
}
newtext = substring(newtext, 0, length(newtext) - 2) "\n"
replace_range(start + 1, end + 1, newtext)
}
define jf_indent {
blank = ""
for (i = 1; i <= $1; i++) {
blank = blank " "
}
return(blank)
}
Cheers,
Jörg
Article: 62754I'm designing a processor for one specific application and in my software I have need a counter. I have a problem figuring out how to make Add-with-carry work for this. I want to do v := v + i. v and i are both 32 bit values, my ALU is 16 bits wide. Everything is 2-complement. I would add the lower 16 bits, then add the higher 16 bits with carry. My problem: "i" may be positive or negative, so there are 3 things that can occur: - overflow - underflow - none of those If I have only one carry bit, those 3 possibilities cannot be represented. Am I right that in such an architecture it is impossible to achieve what I want? How do I have to change my ALU in order to do that? And how do I handle the sign bits in the "middle" of the 32 bit values? If possible, I would like to avoid an additional comparison and use only flags. I have looked at PicoBlaze as an example, but I could not figure out what I am doing wrong. Please help :) Thanks, DanArticle: 62755
I'm in the middle of a similar situation. I just reported a fatal, reproducible error on "My Support." Once the tech was able to reproduce the error, his response was that the bug would be "fixed in a future version..." Case closed. He also said that he successfully tested the design using the integrated FPGA Compiler II tool (I'm using Precision) and recommended that approach as a workaround. I tried it and found that my utilization jumped from ~75% with Precision to 116% with the integrated synthesis. Needless to say, I am not impressed. Joe ------------------------------------------------------------ Joe G. Thompson Phone: (603) 512-9003 joe@advancedprinciples.com Fax: (208) 730-5713 On 3 Nov 2003 01:05:37 -0800, rotemg@mysticom.com (Rotem Gazit) wrote: >Recently we decided to use Altera Cyclone part in a new design. When >we ran into problems I opened a web case using "Altera's my support". >After two days of silence I added an update explaining why the problem >is urgent. >After 10 days !!! I got the first response asking for the name of the >local FAE and providing no more information. >I answered the question and in exchange I got email saying "your >service request will be closed" .Article: 62756
In article <9Scqb.687$Uw1.83781670@newssvr21.news.prodigy.com>, Martin Euredjian <0_0_0_0_@pacbell.net> wrote: > > >I don't have any experience with ZBT SRAM, but in general terms I've been >using the DDR mechanism to generate outgoing source-synchronous bus clocks >and it's worked like a charm for frequencies approaching 200MHz. Of course, >careful board layout is a part of this as well. > ZBT interface is intended to use a single system synchronous clock. They require setup and hold time on the data after the clock to them and the data is valid quite late in the cycle on SRAM read and they don't provide a clock back to register the data. They also have tri-state requirements for the bus turnaround. For the output side using inverted clock and data DDR type would work but properly registering the input using that type of scheme isn't as easy which is why I was trying the single internal/external aligned clock. >Use FPGA Editor to bring the internal clock out to a pin as close to the >external clock as you can (to reduce board/layout/measurement errors). FPGA >Editor will give you routing delay information. I think it's accurate to >the pin. > I have only found how to get max delay from the tool and wasn't sure how much the actual will differ. We will see. Thanks, David GessweinArticle: 62757
Why do you use an ALU to implement a counter? Just use a counter macro that is 32 bits, and you don't have to think. Peter Alfke Kevin Becker wrote: > > I'm designing a processor for one specific application and in my > software I have need a counter. I have a problem figuring out how to > make Add-with-carry work for this. > > I want to do v := v + i. > v and i are both 32 bit values, my ALU is 16 bits wide. > Everything is 2-complement. > > I would add the lower 16 bits, then add the higher 16 bits with carry. > My problem: "i" may be positive or negative, so there are 3 things > that can occur: > - overflow > - underflow > - none of those > > If I have only one carry bit, those 3 possibilities cannot be > represented. Am I right that in such an architecture it is impossible > to achieve what I want? How do I have to change my ALU in order to do > that? And how do I handle the sign bits in the "middle" of the 32 bit > values? If possible, I would like to avoid an additional comparison > and use only flags. > > I have looked at PicoBlaze as an example, but I could not figure out > what I am doing wrong. Please help :) Thanks, DanArticle: 62758
Hi Kevin
"Kevin Becker" <starbugs@gmx.net> escribió en el mensaje
news:bbc55e92.0311061129.28af9d44@posting.google.com...
> I'm designing a processor for one specific application and in my
> software I have need a counter. I have a problem figuring out how to
> make Add-with-carry work for this.
>
> I want to do v := v + i.
> v and i are both 32 bit values, my ALU is 16 bits wide.
> Everything is 2-complement.
>
> I would add the lower 16 bits, then add the higher 16 bits with carry.
> My problem: "i" may be positive or negative, so there are 3 things
> that can occur:
> - overflow
> - underflow
> - none of those
Right for overflow/none. Can't see how could you get an underflow (a too
close too zero
to be represented value) as you're working with 2's complement integers.
All integers in the given range are representable.
As your numbers are 32-bit wide, and overflow condition is a flag
about the result of the _whole_ v := v + i operation, it can be determined
by the MSB bits only (that is, from columns 31 and 30 of the addition).
Let we call cy-n to the carry out of the n-th column, and number the bits
from 0 (lsb) to 31 (msb). Then, overflow = cy-31 xor cy-30.
What you have between columns 15 and 16 is a simple carry,
an intermediate bit of the operation. No (directly) related with the
overflow condition.
>
> If I have only one carry bit, those 3 possibilities cannot be
> represented. Am I right that in such an architecture it is impossible
> to achieve what I want? How do I have to change my ALU in order to do
No. See comments above
> that? And how do I handle the sign bits in the "middle" of the 32 bit
> values? If possible, I would like to avoid an additional comparison
> and use only flags.
>
> I have looked at PicoBlaze as an example, but I could not figure out
> what I am doing wrong. Please help :) Thanks, Dan
Step 1.- v(lo) := v(lo) + i(lo). Store the 16-bit carry out. Call it cy-16
Setp 2.- v(hi) := v(hi) + i(hi) + cy-16.
Step 3.- Check overflow using cy-32 and cy-31. These bits are cy-16 and
cy-15 of step 2 addition.
Now the question are:
a) Is your ALU capable to perform result (a 16 bits plus carry out) = x (a
16-bit value) + y (a 16-bit value) + c (1-bit value, previous carry-out)? If
not, many instructions will be needed to solve your problem.
b) Do you have separate access to the intermediate cy-31? (=cy-15 from step
2).
If not, the overflow condition will be difficult to check.
Hope this helps
Regards
Francisco
================================================================
Francisco Rodriguez Ballester (prodrig@disca.upv.es)
Postal address: Dept. DISCA, EUI - Univ. Politecnica de Valencia
c/Camino de Vera s/n, E-46022, VALENCIA (SPAIN)
tlf: +(34) 96 387 70 07 ext. 75759 - fax: +(34) 96 387 75 79
================================================================
Article: 62759In SVF files generated by impact there will be delay statements on the form: // Loading device with a 'ferase' instruction. ... RUNTEST 15000000 TCK; What is the minimum delay as a result of this statement, i.e. what is the assumed TCK frequency for impact generated SVF files? TIA Petter -- A: Because it messes up the order in which people normally read text. Q: Why is top-posting such a bad thing? A: Top-posting. Q: What is the most annoying thing on usenet and in e-mail?Article: 62762
Goran Bilski <goran@xilinx.com> wrote in message news:<bocq73$bgh1@cliff.xsj.xilinx.com>... > Hi, > > I have been following this thread with great interest. > > If you need a processor with links to/from the processor register file > then MicroBlaze could be the answer. > > MicroBlaze has 18 direct links (in the current version, the ISA allows > up to 2048) and 8 new instructions for sending > or receiving data to/from the register file. > > The connection is called LocalLink (or FSL) and has this features > - Unshared non-arbitrated communication > - Control and Data support > - Uni-directional point-to-point > - FIFO based > - 600 MHz standalone operation > - Hi Goran What I am really after is a speedy Transputer, better still many of them distributed inside & across FPGAs. Not the original with funny 8bit opcodes (partly my fault) but a modern design that is RISC & targeted to FPGA using MicroBlaze as a HW/performance reference. I would budget for about 2x the cost before thinking of FPU, still pretty cheap. The important part is the ISA supports process communication transparently with scheduler in HW. The physical links internal or external is only a part of it. Since many cpus now have these links, and serial speeds can be far in excess of cycle speed, thats nice, but no use if the programmer has to program them themselves. With an improved event wheel scheduler in HW too, HW simulation becomes possible for HW that might be "hard" or "soft", but then HW in FPGAs are not strictly "hardware" either (see old thread). So if HW & SW can be somewhat interchanged, it becomes easier to migrate large C seq problems gradually into C-Occam par/seq then into more HDL par all from inside one (maybe ugly)language. It would be even nicer to start over with a new leaner language that can cover HDL & SW but its more practical to fuse together the languages people actually use. Who is the potential customer for this, any SW-HW person interested in speeding up SW like the original poster or any embedded engineer that wants to customize cpu with own HW addons using Occam style channels to link them. I could go on, but much work to do. John johnjaksonATusaDOTcomArticle: 62763
antti@case2000.com (Antti Lukats) wrote in message news:<80a3aea5.0311060129.38e3476a@posting.google.com>... > "Andras Tantos" <andras_tantos@tantos.yahoo.com> wrote in message news:<3fa942a5@news.microsoft.com>... > > > I will write a open source arm vhdl model from > > > this month on. I hope to have it ready in > > > approximately 2 months using LeonSoc as a framework > > > and implementing a arm1 integerunit. Anyone that wants > > > to participate is wellcome. > > > Konrad Eisele > > > > Many tried, all got kicked in the back by ARM. If you can create something > > useful, get ready for a contact from one of their lawyers, > > > > Andras Tantos > > why write it from scratch? the nnARM source codes can be found with google > with no problems. the synthesis result is unfortunatly quite big fits > barely into XC2S600E > > would be nice to have smaller core though ;) > > antti > PS the ARMlayers tried to take nnARM off from public internet, but its > still downloadable, so the layers are not doing very good job. Doesn't really matter, good enough in this case, lets any potential commercial user get the message loud & clear. If its a 600 target, thats one very expensive Arm compared to real thing. For an opensource cpu to be useable, it must be competitive in size, speed, power with commercial cpus. johnjaksonATusaDOTcomArticle: 62764
I'm working on a cpu core and intend to embed it into ASIC circuits, with the aim to do some network processing. Now the FPGA prototype is running and a 66M speed is achieved( xilinx virtexII-4 ). Wondering how fast it can run in ASIC, we had our ASIC guys to synthesize the codes and the result was shocking, it reached 400M! Far beyond our expectation of 150M. The library we used was of 0.13u, from TI, fairly fast, in which a NAND gate is around 0.03ns. Now my question is: Is the ASIC speed result reliable? Since we didn't do P&R( we don't have tools and experiences ), I really doubt the timing report may be over optimistically estimated and not reliable. I was told something about "wire load model" and ours is automatically selected by the compiler. Anybody can give me some hints or direct me to some documents will be very appreciated! Thank you very much. yu jun yujun@huawei.comArticle: 62765
Austin Lesea wrote:
>
> With the FROM:TO constraints I have always found them applying to things that
> I did not want them to. To really get the constraint "correct" (so that it
> didn't want to apply it to something else), I had to use FROM:THROUGH:TO
> (specify the path in question).
>
> After mucking about with this for a long time, and failing to get a
> reasonable result, I just pulled the constraints, and used the period
> constraint all alone. The multicycle through paths now did not meet timing
> (failed), but at least I could go and manually check each one, and "sign off"
> that these paths were OK none the less.
>
> The area was also massively affected by the FROM:THOUGH:TO constraints, with
> very poor timing results (worse than the period constraint alone) resulting
> on the paths that I really cared about and larger area.....
>
> I suppose that if I had a single clock things would have worked better, but
> with multiple clock domains, resynchonization circuits, and the rest of the
> stuff, the FROM:TO constraints just seemed to be causing me nothing but
> headaches (as the synthesizer just seemed to want to apply relaxed
> constraints to too many paths).
>
> Austin
Howdy Austin,
A number of us at my office have run into situations where we'd like
to use relaxed timing for one thing or another, but rarely do so for the
exact reasons you outline above. If an experienced FAE can't get it to
work correctly, is the customer expected to?
Honestly, this seems like something that parallels floorplanning. Or
the modular design flow. Sure, Xilinx provides a way to do these
things, but it is painful enough that most people can't afford the time
it takes to get it working properly - so neither the customers nor
Xilinx benefits. If only Xilinx would give their customers the tools to
do these kinds of things easily, they'd carve out an even bigger chunk
of the FPGA market for themselves. Quite honestly, with the devices
growing so large, I don't see how this can be pushed aside for much longer.
Have fun,
Marc
Article: 62766
David,
>
>When we do that the external clock is now leading the internal
>clock by 1 ns. I didn't understand why what clock feeds both DCM's
>would change the timing and since our timing is tight I need them
>to be closely aligned.
>
The precessing clock offset is most likely due to the default
intentional delay inserted into the internal DCM feedback path
to give zero hold time at the IOB inputs; this advances the clock
as seen directly at the DCM outputs.
Try setting the DESKEW_ADJUST attribute on the DCM to
SOURCE_SYNCHRONOUS, which disables the internal delay element.
( but be wary of I/O timing changes if that DCM drives anything
other than the forwarded clock )
See pages 4-5 of XAPP259 for a good description of the delay logic.
>
> For the DCM is is ok to feed the locked from one into the reset of the next
> or do we need to hold the reset for at least 3 clocks?
>
This is one of those "DANGER WILL ROBINSON!!!" subjects :
- use a reset delay circuit, and make sure it's clocked by something
other than the output clock of the DCM you're attempting to reset :)
- if you're using external feedback into a DCM to do board deskew,
the deskew DCM requires an even longer reset delay because the
feedback clock IOB is disabled until config completes, so the
master DCM can't startup properly
- be sure to monitor the LOCKED, CLK_IN, CLK_FX status bits
to decide when to reset the master ( and it may not hurt to
independently check that the pre-DCM input clock is present
and accounted for with some sort of watchdog logic )
- any slave DCMs need their own startup logic that fires once
the master has locked, and make sure you check the status
of ALL slave DCMs to decide when it's time to punt and reset
the whole shooting match.
- once you think you have it working, disconnect and reconnect
the input clock a few times and fix anything that fails to
recover properly.
Possibly Helpful Answer Records:
14743 What is the DESKEW_ADJUST attribute?
15350 What does the DESKEW_ADJUST constraint do?
10972 DCM - What do the various status pins represent?
14425 Resetting after configuration is strongly recommended
for a DCM that is configured with external feedback
11067 ModelSim Simulations: Input and Output clocks of the DCM and CLKDLL
models do not appear to be de-skewed
13024 How are Tdllino and Tdcmino calculated for a DLL/DCM?
have fun,
Brian
djg@pdp8.net (David Gesswein) wrote in message news:<T%9qb.10489$9M3.2691@newsread2.news.atl.earthlink.net>...
> I tried the Xilinx support line Case # 503586 and haven't gotten a good
> answer so though I would try here.
>
> I am trying to interface to a ZBT SRAM from a Virtex II and was trying to
> do like in xapp 136 which used 2 DCM's to generate a internal FPGA and an
> external board clock using external DCM feedback that are aligned. That
> configuration in simulation (5.2i sp3) shows the external clock is .5ns
> delayed from the internal clock. We actually need to use a third DCM FX
> output to generate the clock for the SRAM. When we do that the external
> clock is now leading the internal clock by 1 ns. I didn't understand why
> what clock feeds both DCM's would change the timing and since our timing
> is tight I need them to be closely aligned.
>
> The external clock is output using a DDR FF and I used the DCM wizard which
> should of put in all the problem bufg/ibufg etc which the V2 users guide
> says are needed if it is going to compensate for the pad to DCM delay.
>
> I also think only 2 DCM's are needed, 1 to generate the internal clock using
> FX and a second to generate the deskewed external clock. That configuration
> seems to generate the same timing as the 3 DCM version.
>
> Anybody know the correct solution?
>
> Also does anybody know an easy way on the board to measure the alignment
> between an internal and external clock? Bringing the internal clock out to
> a pin would require knowing the actual loaded buffer delay which I
> wouldn't think I could get very accurate. If I can accurately measure it
> and its not a simulation artifact I should be able to tweak the phase shift
> to make it align. I would think that should then be stable across boards.
>
> Couple other questions, has anybody seen the hold time of the V2 IOB
> flip flops documented?
>
> For the DCM is is ok to feed the locked from one into the reset of the next
> or do we need to hold the reset for at least 3 clocks? Different
> documentation shows different ways and the direct connection didn't work
> under 6.1 simulation.
>
> Thanks,
> David Gesswein
Article: 62767"Kevin Becker" <starbugs@gmx.net> wrote in message news:bbc55e92.0311061129.28af9d44@posting.google.com... > I'm designing a processor for one specific application and in my > software I have need a counter. I have a problem figuring out how to > make Add-with-carry work for this. > > I want to do v := v + i. > v and i are both 32 bit values, my ALU is 16 bits wide. > Everything is 2-complement. > > I would add the lower 16 bits, then add the higher 16 bits with carry. > My problem: "i" may be positive or negative, so there are 3 things > that can occur: > - overflow > - underflow > - none of those When after you add the low halfwords, you either get a carry or you don't. That is used as carry in for the high halfword add. > If I have only one carry bit, those 3 possibilities cannot be > represented. Am I right that in such an architecture it is impossible > to achieve what I want? How do I have to change my ALU in order to do > that? And how do I handle the sign bits in the "middle" of the 32 bit > values? If possible, I would like to avoid an additional comparison > and use only flags. After the high halfword add, you compare the carry out to the carry out of the sign bit to the carry in of the sign bit. If they are different then it is overflow or underflow. The value of such bit tells you which one. -- glenArticle: 62768
Dear all: I 've a .jed file of ispLSI-2064 for an old project, but the source .ldf file is lost. Now we have to modify the inside logic of the chip, how to decompile the jedec file back into a ldf file? TIA (Replace "nospam" with "obase" to send me email)Article: 62769
Martin Euredjian wrote: > > "Austin Lesea" wrote: > > > A real customer doesn't care what it costs right now, because 'right now' > is > > not when they are going to sell anything. They want to know what it will > cost > > when they go into production (along with all of their competitors). > > Nitpicking, but, companies like mine are "real customers" yet we only need a > few hundred or thousand devices for production ... not hundreds of > thousands. > > I've always thought that semiconductor pricing was unfairly skewed to favor > the big guys. I understand discount structures, etc., but there's a huge > difference between $200 and $12. And, it's weird, 'cause you'd think that > you'd sell a ton more chips if the little guys could buy them at a more > affordable price point. > > I've been dealing with a semiconductor manufacturer that's been downright > rude about discounts because they were the only game in town. Now, with > Virtex 2 Pro's high speed serial I/O capabilities I have a chance to drop > them like a hot potato in my next design. The likelyhood of that happening > is extremely high at this point. I'm sure they bend over backwards for > those who move more chips, but, what they don't realize (even though I've > explained it), is that I'm ramping up. They are literally handing Xilinx > business to the tune of thousands of V2P's per year. Very unwise. > > So, the high cost of chips for the sub 1K/year crowd might very well make > them look elsewhere and, as you can imagine, once you adopt and get > comfortable with another vendor the chances of getting a different chip onto > that a board are pretty low. Well, that is all in how much you push your distributors. Right now they are hungry and they all want to lock in design wins on the new parts. I have gotten a very agressive price on the XC3S400 and I am asking about the XC3S1000 since I may need a few more LUTs to support modular configuration. I expect I will be getting close to that 10x figure Peter mentioned. My XC3S400 price was within a factor of 3 of that. Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAXArticle: 62770
"David Gesswein" wrote: > >Use FPGA Editor to bring the internal clock out to a pin as close to the > >external clock as you can (to reduce board/layout/measurement errors). FPGA > >Editor will give you routing delay information. I think it's accurate to > >the pin. > > > I have only found how to get max delay from the tool and wasn't sure how > much the actual will differ. We will see. When you define a probe it gives you a routing delay. ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ Martin Euredjian To send private email: 0_0_0_0_@pacbell.net where "0_0_0_0_" = "martineu"Article: 62771
Austin Lesea wrote: > > John, > > Nope. 1st law says that energy is conserved. Can not lose it. > > Austin > > John Smith wrote: > > > > Aggghhhh.... I'm gonna be on 2ndlaw.com, and its sister, I may be a while... > > > > Thanks for the answers guys. 'Lost' energy (non-recoverable energy) is my > > summary. Correct? > > > > Thanks again > > JS John, Don't let this confuse you. In reality "lost" energy is still energy. But it is lost in the sense that you can't do anything useful with it. It becomes spread out evenly as heat otherwise known as "disorder". Only "orderly" forms of energy can be used. Heat is only useful (orderly) if there is more of it here than there, then you can get some useful work from it by tapping it as it flows from here to there. But then both here and there are at the same temperature and you can do no more work with that energy. In that sense, it is "lost". -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAXArticle: 62772
Just remember that support people get graded on how quickly they close cases, not how "well" they close them (as least as far as I can tell). And this is not limited to Altera. Speed is clearly the primary evaluation of support at most companies. Joe Thompson wrote: > > I'm in the middle of a similar situation. I just reported a fatal, > reproducible error on "My Support." Once the tech was able to > reproduce the error, his response was that the bug would be "fixed in > a future version..." Case closed. > > He also said that he successfully tested the design using the > integrated FPGA Compiler II tool (I'm using Precision) and recommended > that approach as a workaround. I tried it and found that my > utilization jumped from ~75% with Precision to 116% with the > integrated synthesis. > > Needless to say, I am not impressed. > > Joe > ------------------------------------------------------------ > Joe G. Thompson Phone: (603) 512-9003 > joe@advancedprinciples.com Fax: (208) 730-5713 > > On 3 Nov 2003 01:05:37 -0800, rotemg@mysticom.com (Rotem Gazit) wrote: > > >Recently we decided to use Altera Cyclone part in a new design. When > >we ran into problems I opened a web case using "Altera's my support". > >After two days of silence I added an update explaining why the problem > >is urgent. > >After 10 days !!! I got the first response asking for the name of the > >local FAE and providing no more information. > >I answered the question and in exchange I got email saying "your > >service request will be closed" . -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAXArticle: 62773
Hi Stefano, I got the same problem as you.. (Foolishly upgraded to 5.2.03i) Is there some way to get an answer from the Xilinx guys? Thanks a bunch. ========================================================================= Low Level Synthesis * ========================================================================= Library "C:/Xilinx/data/librtl.xst" Consulted WARNING:Xst:528 - Multi-source in Unit <sha2> on signal <h_rnm0_0> not replaced by logic Signal is stuck at GND WARNING:Xst:528 - Multi-source in Unit <sha2> on signal <g_rnm0_0> not replaced by logic Signal is stuck at GND WARNING:Xst:528 - Multi-source in Unit <sha2> on signal <f_rnm0_0> not replaced by logic Signal is stuck at GND WARNING:Xst:528 - Multi-source in Unit <sha2> on signal <e_rnm0_0> not replaced by logic Signal is stuck at GND WARNING:Xst:528 - Multi-source in Unit <sha2> on signal <d_rnm0_0> not replaced by logic Signal is stuck at GND WARNING:Xst:528 - Multi-source in Unit <sha2> on signal <c_rnm0_0> not replaced by logic Signal is stuck at GND WARNING:Xst:528 - Multi-source in Unit <sha2> on signal <a_rnm0_31> not replaced by logic Sources are: b_rnm0_0:Q, a_rnm0_31:Q ERROR:Xst:415 - Synthesis failed CPU : 3.89 / 4.38 s | Elapsed : 4.00 / 4.00 sArticle: 62774
(below french version) Hello all, I'd like to ask you if anyone used JBits and XHWIF with admxrc2 boards. I'm trying to do this but I don't want to spend time if anyone did already this. Is anyone who managed to port the XHWIF (and JBits) to an admxrc2 board? Thanks very much for your help Barthélémy von Haller PS : if you have an example of porting a board to xhwif could you send me the sources ? **** french version **** Bonjour tout le monde, J'aimerais utiliser JBits et XHWIF avec la carte admxrc2 de alpha data. Malheureusement je n'ai pas trouver qqn qui aurait déjà porté xhwif sur cette carte et je suis donc obligé de m'y atteler. Avant de m'y mettre et de passer beaucoup de temps là-dessus, j'aurais aimé savoir si qqn a édjà fait ce portage et si cette personne serait prête à partager son travail ! D'avance un grand merc Barthélémy von Haller PS : même si vous n'avez pas porté xhwif sur admxrc2, mais sur une autre carte, je suis intéressé par les sources qui je l'espère me donneront de l'inspiration !
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