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Symon, None. We have no possibility of Single Event Latch-up (already tested every famility in the neutron beam). No hard failures whatsoever. The device FIT rate is probably somewhere around 20 FITs (estimate from high temperature operating life testsing). Austin Symon wrote: > Hi Austin, > Out of interest, how many of the 300 parts in your experiment broke > permanently? Any at all? If there were any 'hard' failures, did altitude > affect this statistic, or were these failures due to other mechanisms? > Syms. > > "Austin Lesea" <Austin.Lesea@xilinx.com> wrote in message > news:3FA0113E.BDD340C1@xilinx.com... > > Hello from the SEU Desk: > > > > Peter defended us rather well, but how can one seriously question real > > data vs. babble and drivel? > > > > Well, after 919 equivalent device years of experiment at sea level, > > Albuquerque (~5100 feet), and White Mountain Research Center (12,500 > > feet) the Rosetta Experiment* on the 3 groups of 100 2V6000s has logged > > a grand total of 45 single soft error events, for a grand total of 20.4 > > years MTBF (or 5335 FITs -- FITs and MTBF are related by a simple > > formula -- mean time between failures vs failures per billion hours or > > FITs). > > > >Article: 62626
Hi Rotem, absolutly not, my experience isn't so bad. I get answers from mySupport within the same working day (as far it is possible over the Atlantic ocean ;-)) Marc rotemg@mysticom.com (Rotem Gazit) wrote in message news:<86b060d0.0311030105.2488bb09@posting.google.com>... > We have been working with Xilinx parts for the past 4 years. > Whenever I had problem the local FAE couldn't solve I used the Xilinx > WEB case system. > I always got very fast and professional response, usually within the > same working day. > > Recently we decided to use Altera Cyclone part in a new design. When > we ran into problems I opened a web case using "Altera's my support". > After two days of silence I added an update explaining why the problem > is urgent. > After 10 days !!! I got the first response asking for the name of the > local FAE and providing no more information. > I answered the question and in exchange I got email saying "your > service request will be closed" . > > Did anyone else had this kind , maybe better ?, experience with Altera > web support ? > I think that as FPGAs become more and more complicated, and design > cycles shorter, the support level is becoming one of the key factors > when selecting an FPGA. > > Cheers, > RotemArticle: 62627
Rotem Gazit wrote: > After 10 days !!! I got the first response asking for the name of the > local FAE and providing no more information. > I answered the question and in exchange I got email saying "your > service request will be closed". For Altera technical problems, I call the FAE. He calls back the same day, and sometimes knows the answer. He has a direct line to support if he doesn't. The Altera web site has good docs and FAQs, but I only enter a web case if I have a well-defined reproducable bug. > I think that as FPGAs become more and more complicated, and design > cycles shorter, the support level is becoming one of the key factors > when selecting an FPGA. I agree. FPGAs are just a big bag of gates and flops. Design decisions are now mostly based on service. -- Mike TreselerArticle: 62628
> I had to debug somebody else's hardware that implemented a FINO > > He had invented the wonderful new memory type... 2K by 8 WOM > > Write-Only Memory :-) > > Ian Hi Ian. Sorry but my WOM has 1Mbitx16, it´s implemented on strained silicon, has a life expectancy of almost 10 write cycles and I think it doesn't loose it contents when power is turned off (for obvious reasons I couldn't test this) :) I'm looking for funds to maintain this important research. Anyone? Luiz CarlosArticle: 62629
Hi All,
I also use bits of Perl script to produce a text file which lists 'nets
connected to the device' next to 'device pin names'. The Perl get the data
from the CAD tool netlist output and Xilinx's pinlists. (I used to cut and
paste pinlists from the PDF but I think Xilinx provide these files
nowadays). This makes it easier to go through the design and look for
typos/errors. The Perl also lists unused pins, which catches mistakes too.
Also, the script makes the pin LOC bit of the UCF file, the net names on
the schematic must match the top level Entity port names, of course.
cheers, Syms.
>
> My suggestion would be to just do it by hand and carefully
> check things. Then get a couple of friends to help you check
> it again. It would be worth bribing with beer/pizza and/or
> offering to trade roles when their design needs checking.
>
> What I've done on many occasions is to collect paper copies of
> all the data sheets and net lists (both by net and by part/pin)
> and all the other info you think might be interesting, and take
> over a conference room with a big table and do a check-everything
> level design review just before the board goes out. And gerber
> plots and ... Get somebody to check everything you can think
> of to check. They don't have to know much about your design,
> just have enough experience and common sense to read the data
> sheets and schematics and see if the connections make sense.
> (Double-double check the bubbles/inversions.)
>
>
> There is a lot of regularity in the footprint. Assuming your
> board level CAD system has some sort of scripting, you can
> probably write a program/script to generate a script that
> will make the part.
>
Article: 62630John, Falling apart. What everything does (eventually). What you and I are doing right now (getting older, and falling apart). Austin John Smith wrote: > "Kevin Neilson" <kevin_neilson@removethiscomcast.net> wrote in message > news:ZzCob.71991$Fm2.57178@attbi_s04... > > I read an article in "Scientific American" about how much information can > be > > compressed into a certain volume, and apparently all objects have a > Shannon > > entropy in addition to the thermodynamic entropy. Also, black holes have > a > > Shannon entropy that is based on the surface area of the event horizon. I > > was totally lost. Can anybody else explain how Shannon's information > > theory applies to black holes? > > -Kevin > > > > > > For the ignorant (me): what it Entropy? > > RichArticle: 62632
"Austin Lesea" <Austin.Lesea@xilinx.com> wrote in message news:3FA3000A.45C10F96@xilinx.com... > Kevin, > > Really quite easy. > > Just read http://www.mdpi.org/entropy/papers/e3010012.pdf > > Now after you have read it, go get a stiff drink ....and then fall into a > troubled sleep. > > As you toss and turn having nightmares about information horizons, and gravity > strings, remember what the White Rabbit said: "feed your hair." > I thought it was "feed your head."Article: 62633
Tehe address mapping is only of concern when you use different aspect ratios ( depth x width) for the two ports. You may want to read XAPP463 which, for Spartan3, describes the same BlockRAM as in Virtex-II and Virtex-IIPro. But this description is younger and better. For each port, you can chose between 16K x 1 (deep and narrow),all the way to 512 x 36 (shallow and wide ). The table shows you the mapping. Don"t ask for 32-bit address operation! Peter Alfke ======================== Vazquez wrote: > > Hello, > > there is an application note from Xilinx: XAPP130 (v1.4) > http://www.xilinx.com/bvdocs/appnotes/xapp130.pdf > > On page 4 there is table 3: Port Address Mapping. > > There are some formulas given for Start and End. > > My question: What do Start and End mean? > What is the meaning of ADDRport(Read or Write?)? > What is the meaning of Widthport(Read or Write?)? > > Maybe someone can it explain on some example: > > write port data width[0..0] > write address [14..0] > > read port data width [9..0] > read address [31 ..0] > > How can the formulas be applied to this example? > > Thank you for your help. > > Kind regards > > Andres Vazquez > G&D System DevelopmentArticle: 62634
"Ben Twijnstra" <bentw@SPAM.ME.NOT.chello.nl> writes: > > I think it's wrong to check for the distribution. One should check for > > the functionality required by the tool. If you require a certain > > thread library, check for that and report that installation fails > > since the specific thread library is not present. > > The trouble is that you can check for version numbers and such, but not on > actual capabilities when you get a distribution shoved in your face. Red Hat > 9.0 reports a certain version number for their Posix threads library that is > basically the same as the version number reported by the 8.x versions. > However, this 9.0 version uses significantly different kernel calls than the > 8.x series. How to determine what a library does under the hood... If you've > got a good idea that does not involve compiling code and see whether it > coredumps, I'll take it. Hi Ben, Unfortunately I don't have a lot of Posix threads experience so I can't comment on the version number checking. However, I think one should check for the functionality provided by the different versions rather than trying to extract their version numbers. It might be possible to fork out two pre-compiled code segments which assume the functionality of the two thread libraries. One will crash (I guess you'll have to catch that sigv) and not return the correct result. The other will run and return the correct result. This way you should be able to tell which part of the installer has to use. Of course testing for a known kernel bug which will lock up the machine this way is not advisable :-) OTOH I don't see why compiling a small program and see if it compiles, links, and run is that bad. This is what's taking place in the GNU autoconf script which many Linux users are quite familiar with. > IMHO, Quartus under Linux is pretty flexible when it comes to > distributions. Yes. But unfortunately it does not run on the x86-64 under SuSe 8.2 as I mentioned in an earlier message. I think it will run if the LD_LIBRARY_PATH etc. is set up correctly. This is a minor issue which I think would be simple to fix. I don't think Altera should officially support all (or a large number of) Linux distributions. I think it's better to make sure it runs well under the officially supported version. However, I hate to see software which checks if /etc/redhat-release matches a given string and bails out if it doesn't (it could give you a warning that you're running under a non-supported release). Again, they should check for the functionality required by the tool so that it could run under multiple distributions which provide the same libraries as the officially supported version. I think this will only get better over time as Linux becomes even more mainstream in the EDA world. Petter -- A: Because it messes up the order in which people normally read text. Q: Why is top-posting such a bad thing? A: Top-posting. Q: What is the most annoying thing on usenet and in e-mail?Article: 62635
John Smith wrote:
> "Kevin Neilson" <kevin_neilson@removethiscomcast.net> wrote in message
> news:ZzCob.71991$Fm2.57178@attbi_s04...
>
>>I read an article in "Scientific American" about how much information can
>
> be
>
>>compressed into a certain volume, and apparently all objects have a
>
> Shannon
>
>>entropy in addition to the thermodynamic entropy. Also, black holes have
>
> a
>
>>Shannon entropy that is based on the surface area of the event horizon. I
>>was totally lost. Can anybody else explain how Shannon's information
>>theory applies to black holes?
>>-Kevin
>>
>>
>
>
> For the ignorant (me): what it Entropy?
>
> Rich
>
http://www.2ndlaw.com/ will be a good start. Note that if S is entropy, q
the amount of heat -- BTU, Calories -- and T absolute temperature,
S = Integral(dQ/T).
Simplifying: heat, like water, runs downhill, and unless something like a
waterwheel or a heat engine extracts energy when it does, some of what
had been available energy is permanently lost. The water or heat is all
still there, and so is the energy -- just not available. Lost available
energy shows up as increased entropy.
Two Laws of Thermodynamics have been stated thus:
You can't get something for nothing. Water had to be pumped up before it
ran down to turn the wheel.
You can't even break even. (The second law is about entropy.) Because of
inevitable inefficiencies -- friction or moving heat across a temperature
gradient, entropy will increase, and you won't get all of the energy out.
Let's leave the Third Law for some other time.
Jerry
--
Engineering is the art of making what you want from things you can get.
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Article: 62636that's enough guys..., black hole normaly holds 1, or 2,...but sometimes up to 5 boys and girls (please check guiness book), noting to do with the surface except for its decoration attractivenessArticle: 62637
"Steve" <email_me@via_my_website.com> wrote in message news:<diupb.361$Hn6.398701@newsfep1-win.server.ntli.net>... > The best advice from this thread was from Matt North when he said: > > "This is because languages like VHDL are HARDWARE description languages, you > code should be > written is such a way that a synthesis tool can recognise it as a counter, > memory, mux etc." Thanks a bunch for your comments and the book suggestions. What you describe certainly makes sense, and it sounds like a pitfall that I would have gone into head first. Now, having been warned, maybe I can get by with just a scraped knee or so! MikeArticle: 62638
santosh nath wrote: > > I am really curious to know how thermodynamic entropy differs from > Shannon's There is some controversy about this. The two ideas are fundamentally distinct and it is unfortunate that they have the same name. They are related, of course, but the relationship is something that has to be spelled out carefully. In my opinion the best work on this is a paper Ed Jaynes wrote for the Am. J. Phys. You'll find it here: http://bayes.wustl.edu/etj/node1.html "Gibbs vs. Boltzmann Entropies", article 21. I believe Anton Garrett wrote a lengthy paper spelling it out further based on Jaynes's argument; I think it was in *Foundations of Physics* several years ago. This isn't trivial stuff; good luck studying it! -Tom -- To respond by email, replace "somewhere" with "astro" in the return address.Article: 62639
Hi Hal, Hal Murray wrote: > My suggestion would be to just do it by hand and carefully > check things. Then get a couple of friends to help you check > it again. It would be worth bribing with beer/pizza and/or > offering to trade roles when their design needs checking. It didn't end up taking very long, maybe 5 hours I suppose. In my youth (!) I entered pages and pages of hex by hand from computer magazines - those old skills came flooding back to me yesterday as I trolled one line at a time through the pinout sheet, checking off each pin and so on... > There is a lot of regularity in the footprint. Assuming your > board level CAD system has some sort of scripting, you can > probably write a program/script to generate a script that > will make the part. I should look into this - I'm using Mentor's DesignView and ExpeditionPCB, presumably they have some scripting capabilties. Thanks for your reply. JohnArticle: 62640
Hi Mike, mikegw wrote: > a) Will a FPGA co-processor board(s) offer a speed improvement in running > our simulation jobs over using a 'traditional' cluster (mosix/Bewoulf)? > Bearing in mind that ours will be the only job on the machine so can we > reconfigure our FPGA boards to speed calculation? To parallel what Jon said earlier - the biggest gotcha that seems to bite people is IO bandwidth. It's not necessarily hard to develop highly pipelined FPGA designs that will crunch your numbers at 100M sample/sec, but can you keep it busy? I read of an interesting approach a while ago - do a search for Pilchard, it's an FPGA coprocessor board developed at a Hong Kong university. Basically it fits in the standard PC memory module form factor, with custom Linux drivers to access it. The bandwidth on the memory bus is much greater than on PCI. Regards, JohnArticle: 62641
> > Kevin Neilson wrote:
> > > Can anybody else explain how Shannon's information
> > > theory applies to black holes?
> >
> > Sounds like just the place for a
> > First In Never Out (FINO) transmit buffer.
> >
> > -- Mike Treseler
>
> I had to debug somebody else's hardware that implemented a FINO
>
> He had invented the wonderful new memory type... 2K by 8 WOM
>
> Write-Only Memory :-)
>
> Ian
Ian,
Signetics invented this 30 years ago!
try :- http://www.ariplex.com/tina/tsignet1.htm
Syms.
Article: 62642OH yea, this sounds like the support I get when using the web site. My FAE is very good so I have switched over to calling him first. Good luck, I think you are going to need it. "Rotem Gazit" <rotemg@mysticom.com> wrote in message news:86b060d0.0311030105.2488bb09@posting.google.com... > We have been working with Xilinx parts for the past 4 years. > Whenever I had problem the local FAE couldn't solve I used the Xilinx > WEB case system. > I always got very fast and professional response, usually within the > same working day. > > Recently we decided to use Altera Cyclone part in a new design. When > we ran into problems I opened a web case using "Altera's my support". > After two days of silence I added an update explaining why the problem > is urgent. > After 10 days !!! I got the first response asking for the name of the > local FAE and providing no more information. > I answered the question and in exchange I got email saying "your > service request will be closed" . > > Did anyone else had this kind , maybe better ?, experience with Altera > web support ? > I think that as FPGAs become more and more complicated, and design > cycles shorter, the support level is becoming one of the key factors > when selecting an FPGA. > > Cheers, > RotemArticle: 62643
Hello Lockie, I donot know your previous implementation was on XC95288 or the XC95288XL family, the thing here is the XL devices have 5V tolerant i/o, and you can interface them straight to the FPGA i/o. Pull up is required in case of 5V CMOS only. But in the case of Spartan2E, the i/o's are not 5V tolerant, and thus you cannot directly interface it to a 5V device. You need to have a series resistor or a buffer in between. In your case as you want to interface the fpga to the cpu, which in your case I presume to be 5V CMOS you can only use a level translator or bidirectional buffer for e.g. from IDT, www.idt.com. If you don't want to use external buffer and use the pull up resistor arrangement, you will need to use the Spartan2 family instead, which has 5V tolerant I/o. Regards Sandeep "Lockie" <biglockie@hotmail.com> wrote in message news:3fa5fdfc@dnews.tpgi.com.au... > Hey All, > > Im using a XC2S300E and a 5V CPU. The XC2S300E implements a simple memory > interface to the CPU. > > My question is related to using the 5V CPU with the 3.3V XC2S I/O Pins. In > a past design i've used a XC95288 (CPLD), and had to use strong pull up > resistors (<1K to 5V) to meet the timing requirements of the bus, along with > floating the Xilinx I/O Pins to implement a bi-directional interface. > > In this new design its not suitable to use such a "dodgey" method of > interfacing. > > Can anyone suggest any possible solutions I could try? > > Thanks in advance. > Lockie. > >Article: 62644
Hello Nick, Pls find the Quality and Reliability report for Xilinx at; http://www.xilinx.com/products/qa_data/index.htm This will give you details on the various tests being carried out for fault tolerance. Regards Sandeep "Nick" <nc300@ic.ac.uk> wrote in message news:867470.0311030641.72b9e096@posting.google.com... > Hi all, > > I have recently started to look into FPGA defect and fault tolerance, > I was wondering if anyone could suggest a book or paper I could read > reflecting what has been done in the field. > > Thanks, > > NickArticle: 62645
Hi all, As there are number of point tools available in the industry for FPGA based design and implementation, it is becoming more difficult to stick to one flow. Does anybody have some sort of tools tree (2-3 tools against each node in the design flow diagram) available in the industry? This should be independent of any tool vendor but include widely used tools. I mean, I want something like this 1. Design entry Tool1: Tool2: 2. Synthesis Tool1: Leo Spec Tool2: Synplify Pro Tool3:... 3. Code Coverage / Automatic test bench gen. Tool1: ... Tool2: ... 4. Physical synthesis Tool1: ... 5. Place and Route Tool1: ... Tool2:... 6. STA etc..... Thanx in advance, NagarajArticle: 62646
presently we are working on 802.11a/g implementation in fpga. whazz up, david ? cheers, buzz # -----Original Message----- # From: David [mailto:dbeberman@earthlink.net] # Posted At: Wednesday, October 29, 2003 4:01 AM # Posted To: fpga # Conversation: Searching for 802.11a/g implementations # Subject: Re: Searching for 802.11a/g implementations #=20 #=20 # Thanks for the response, Robert. I hadn't found what I was looking # for with a google search, but will take a look at ittiam. #=20 # In answer to another response, what I'm looking for is the DSP # baseband processing part of the 802.11 phy. The RF frontend and the # ADC/DAC are not my main focus right now. Not looking at the MAC # either. # Thanks #=20 # "Robert Sefton" <rsefton@abc.net> wrote in message=20 # news:<%xfnb.71886$th6.68580@twister.socal.rr.com>... # > I googled on "802.11" phy core and got several hits. Here's=20 # one that has # > been targeted to an FPGA. # >=20 # > http://www.ittiam.com/pages/products/wlan-aphy.htm # >=20 # > Robert # >=20 # > "David" <dbeberman@earthlink.net> wrote in message # > news:366a0905.0310250649.7e4883f@posting.google.com... # > > Hi, # > > # > > I've been reading the archives of this list, and the FAQ.=20 # I haven't # > > seen much about 802.11a and g phy implementations. Does=20 # anybody know # > > where I might find 802.11a/g VHDL, Verilog or other=20 # implementations. # > > This does not need to be open source, however, I am looking for # > > something that I will be able to add my own modifications to. # > > # > > Thanks, # > > # > > David #=20Article: 62648
"mikegw" <mikegw20@hotmail.spammers.must.die.com> wrote in message news:<bo4na0$5qk$1@tomahawk.unsw.edu.au>... > Hello all, > > Firstly I would like to say that other than knowing what a FPGA is on a most > basic level my knowledge about the subject is nil. I am looking at this > from an application that needs a solution. I have seen about the place add > on boards for PC's that act as co-processors. This is the interesting bit > to me. Our research group is looking into building a computer (cluster > perhaps) for calculation of particle dynamics, similar to CFD in > application. Our programs are in C/C++ running on Linux ( any flavour will > do). in München, Germany there is a research group that uses Xilinx a lot they do some 'particle' search I think FPGAs are mostly used to filter out the data coming from then experiment. as you are also in heavy research area maybe good idea to contact them - I have no addresses but there are not so many nuclear labs so the one I mentioned should be easy to find for you anttiArticle: 62649
John Williams <jwilliams@itee.uq.edu.au> writes: > Hi Hal, > > Hal Murray wrote: > > > My suggestion would be to just do it by hand and carefully > > check things. Then get a couple of friends to help you check > > it again. It would be worth bribing with beer/pizza and/or > > offering to trade roles when their design needs checking. > > It didn't end up taking very long, maybe 5 hours I suppose. In my > youth (!) I entered pages and pages of hex by hand from computer > magazines - > those old skills came flooding back to me yesterday as I trolled one > line at a time through the pinout sheet, checking off each pin and so > on... > > > There is a lot of regularity in the footprint. Assuming your > > board level CAD system has some sort of scripting, you can > > probably write a program/script to generate a script that > > will make the part. > > I should look into this - I'm using Mentor's DesignView and > ExpeditionPCB, presumably they have some scripting capabilties. > Lots of luck - the Expedition flow has zero scripting capability :-) We use the same flow, and I ended up writing some perl which read the Altera .pin file, created a symbol (using acmaker), then created a PDB entry in hkp, then HKP2partsdb it into the local parts database. Not pleasant, but it meant that changing the pinout of our 2x356 BGAs (it was a while ago - I thought they were scary then :-) was a whole lot less hassle. If you're using that flow, I'd look into Boardlink (which you have included with your DesignView license - or maybe Boardlink Pro, which costs money. Cheers, Martin -- martin.j.thompson@trw.com TRW Conekt, Solihull, UK http://www.trw.com/conekt
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