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"Roberto Gallo" <robertogallofilho@hotmail.com> wrote in message news:b16n2d$ive$1@aracaju.ic.unicamp.br... > > Does anyone have any ideia about how to create a *real* Random Number > Generator using an APEX20K FPGA? If no, is there any IC that can do that? > I would be very pleased if someone could give me at least some ideas. > http://www.intel.com/design/security/rng/rngppr.htm Give some references on hardware random number generators that are not pseudo random number generators. I doubt this could be done with an FPGA, though. I believe it uses some special analog electronics to do it. It might be that you could do it with a small amount of external analog circuitry and the digital part in the FPGA. Otherwise very long LFSR's could generate numbers with periods longer than the age of the universe. A lot longer. (I won't say how long, as we had a long discussion on this before.) There are also tricks that some PC OS's use to initialize the RNG, like measure the time between keypresses or mouse clicks. -- glen -- glenArticle: 52026
hi, go for other family like virtex which can operate at higher clock rate best of luck praveenArticle: 52027
I have two versions installed on Win98 and it works fine... just got to change the XILINX variable (either in your registry, or easier still in your autoexec.bat) to point to the right path. adrian > Hello, > Can any conflict occurs if i install 2 versions of the xilinx tool in > the same machine. > thanksArticle: 52028
Thanks for all answer. Manual encoding is a solution but enumerate type is very useful in simulation where you see clearly your state and not an numeric valuer without sense (we use an high level description language !). Moreover when you have an existing design (and even several) with enumerate type in many and many FSM is very costly to modify a "correct" code because of a lack of the synthetiser. I discover recently that Mentor Graphic as this safe mode too (see http://www.iec.org/online/tutorials/safe_state/) I hope that Xilinx engineers will offer soon this important feature (and hope they hear me !). chopra_vikram@excite.com (Vikram) wrote in message news:<b6a2818d.0301281156.5eda1be2@posting.google.com>... > Mike Treseler <mike.treseler@flukenetworks.com> wrote in message news:<3E357B74.2090208@flukenetworks.com>... > > Alain wrote: > > > How specify with XST synthetiser (Xilinx) to encode FSM in "safest > > > way", . . . > > > I previously use FpgaExpress and it had this option... > > > > > > If XST has no "safe" setting for one-hot, consider using > > binary encoding as it is inherently safe. > > > > -- Mike Treseler > > A google search on - XST one-hot comes up with the foll. links - > > http://toolbox.xilinx.com/docsan/xilinx4/data/docs/cgd/f6.html > > http://www.xilinx.com/xlnx/xil_ans_display.jsp?BV_SessionID=@@@@0361207789.1043783564@@@@&BV_EngineID=ccccadchggigjemcflgcefldfgldgji.0&getPagePath=15708 > > Hope this helps, > Vikram.Article: 52029
Dear Ken, I used a serial adder for my first design. Sadly there is little chance to avoid the 1024 clock cycle penalty, as there is a comparison on the next step of the algorithm: Interleaved Modular Multiplication (compute: P=X*Y mod M) P:=0 for i=1024 downto 1 do P:=2P+X(i)*Y if P>M then P:=P-M if P>M then P:=P-M end for There can be done some improvements on that, but the main problem remains. As far as i can see, there is nearly no pipelining possible. Thank you very much for your answer. I really would enjoy the course, as there are a lot of very interesting points. Unfortunately I have neither the time nor the money yet. Yours sincerly, Lars. -- GnuPG public key: http://www.ida.ing.tu-bs.de/~larsu/larsu_ida_ing_tu-bs_de.keyArticle: 52030
On Tue, 28 Jan 2003, Ray Andraka wrote: > There are several ways to skin this cat. > > You can mix carry techniques. Use the fast carry chain for reasonable sized > sub-adders (say 32 bits), then use one of the fast carry techniques such as carry > look-ahead, carry-skip or carry select to combine the results. Depending on your > performance target, you probably will still need to do some pipelining. Up to now i only use sub-adders with the carry-select techniques, because my first attempts with carry-look-ahead logic were without success. I got a long delay with the PG-generators. Beside of that they use a large amount of LUTs. But i think it is worth to give it another try. Thank you for your notion on that. > Another option is to use 1024 serial adders (assuming you need a result every clock > cycle), then arrange the adds so that each one is started on clock after the > previous. These will run very fast, as there is no carry chain to worry about, and > the adder itself only occupies one slice. You will need a shift register for each > one however, so it will get to be quite large if you need to do an add per clock. > The high clock capability may let you do several clocks per sample, which will > greatly reduce the number of instances you will need. Sorry, i'm not able to follow you in this point. I still have a delay of 1024 clock cycles for the completion of the first add ? If its so, i have to make a comparison on the result after the addition and therefore it is hard to use pipelining (please see answer to Ken). > In your case, I think the best bet may be to just use pipelining and accept the > latency. My next approach is to use a 512 or 256 bit adder and therefore split the computing into 2 resp. 4 clock cycles. -- GnuPG public key: http://www.ida.ing.tu-bs.de/~larsu/larsu_ida_ing_tu-bs_de.keyArticle: 52031
On Tue, 28 Jan 2003, glen herrmannsfeldt wrote: > I would say that a pipelining approach should help. I am > interested to know what kind of problem would use a 1024 bit adder. Glen, I try to implement an algorithm of modular multiplication, which is needed for many cryptographic applications. Typically this multiplication is solved with a Montgomery multiplier. However i work on another approach. -- GnuPG public key: http://www.ida.ing.tu-bs.de/~larsu/larsu_ida_ing_tu-bs_de.keyArticle: 52032
Hi Pete Tyder might have what you are looking for www.tyder.com We got help from them before using fpga boards for DSP work. Bob "Pete Dudley" <pete.dudley@comcast.net> wrote in message news:<nKqcnYJF6v_dyqqjXTWc3A@comcast.com>... > Does anyone know of a analog-in analog-out DSP development for a Xilinx > fpga? > > I don't need much fpga logic. I just want something into which I can burn my > iir filter design so the customer can see what it does before we build it > into his system. > > The frequencies are in the audio range so 20Ksps is fast enough.Article: 52033
Depends on when you need that number, If you need it only now and then, and not on regulary times, just read out a counter that never stops. This can be usefull if you have a CPU on board, and you must for example generate a random nr for a TCP-packet sequence nr. Reading out a 32 bit counter can save you much processing time. "Roberto Gallo" <robertogallofilho@hotmail.com> wrote in message news:b16n2d$ive$1@aracaju.ic.unicamp.br... > > > Hello gurus! > > Does anyone have any ideia about how to create a *real* Random Number > Generator using an APEX20K FPGA? If no, is there any IC that can do that? > I would be very pleased if someone could give me at least some ideas. > > > Thank you > > Roberto Gallo > > >Article: 52034
Hello Mr.Kevin, I have all documents of PLX 9050. Its little difficult to start about. Which one to implement????.....this type of question keeps buging me. It will good if i can get was reference PCI core detail(internal design details), do u have any idea where i can get?????. I tried opencore.com but he doesnot explain properly. If anyone have any details regarding it . Please do tell waiting for reply praveenArticle: 52035
praveenkumar1979@rediffmail.com (praveen) wrote in message news:<ff8a3afb.0301282235.6d57954@posting.google.com>... > hello, > i am praveen kumar , a student doing the vhdl code of PCI bridge. can > u please give the internal design detial(design document) of the PCI > bridge which you have implemented. you can mail it to my email id > praveenkumar1979@rediffmail.com).i will be greatful to you. > > waiting for ur reply > thanks in advance > praveen Praveen, it is not a PCI bridge what I am designing. I sent you an email. Mauricio LangeArticle: 52036
svhb <svhb@pandora.be> wrote: : Depends on when you need that number, : If you need it only now and then, and not on regulary times, just read out a : counter that never stops. : This can be usefull if you have a CPU on board, and you must for example : generate a random nr for a TCP-packet sequence nr. Reading out a 32 bit : counter can save you much processing time. Implementing ringoscillators to clock those counters could add some more stochastics to the numbers read... -- Uwe Bonnes bon@elektron.ikp.physik.tu-darmstadt.de Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt --------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------Article: 52037
Hello all,
I'm having a problem reading some test data into my quartus ii design.
The .txt file has a simple format of integers in a column :eg.
234
-3421
21
etc .. .
I created a new block in quartus for vhdl :
LIBRARY ieee ;
USE ieee.std_logic_1164.all;
USE ieee.numeric_std.all;
LIBRARY std ;
USE std.textio.all;
ENTITY Read_Vectors IS
generic(
Input_File : string := "c:\test_read_vectors_integer.txt"
);
PORT(
clk : IN std_logic;
Ena : IN std_logic;
Xout_Value : OUT signed (15 DOWNTO 0);
);
END Read_Vectors ;
ARCHITECTURE Version_1 OF Read_Vectors IS
begin
Read_in_Integer : process(clk, Ena)
file X : TEXT open READ_MODE is input_file;
variable L : line;-- line of file
variable Xin_file_integer_value : Integer;
begin
if Ena = '0' then
Xout_Value <=(others => '0');
elsif rising_edge(clk) and not endfile(X) then
readline (X, L);--read input file
read (L, Xin_file_integer_value); --read value from file
Xout_Value <= to_signed(Xin_file_integer_value,16);
end if;
end process read_in_integer;
end Version_1;
My plan is to use Xout_Value as the input to my design. The problem is
that I can't get this code to output the values under the quartus
environment. Is there another way to achieve this ?
Article: 52038I think Altera uses GNU-C for NIOS. "Marc Van Riet" <marcvanriet@yahoo.com> wrote in message news:3e35c83e$0$27955$ba620e4c@news.skynet.be... > Hi, > > I'm writing a small processor core as a hobby. It is a small 16-bit core > with about 20 instructions, including simple ALU functions, memory read and > writes, stack operations, ... All instructions can be conditional > (depending on the value of my 'working register'). Up to three operations > can be combined in a single opcode, although not all combinations are > possible. > > I was wondering if it would be do-able for me to port the GNU C-compiler to > my own core. I guess it is possible, since the ARM has conditional > instructions too, and it has multiple instructions in one opcode too. > > But how long would that take me ? Anybody any experience in porting GNU-C to > a similar core as mine ? > > Are there any alternatives ? The LCC compiler isn't an option I think, > because their original target core doesn't have multiple-instructions or > conditional code. > > Any comments are appreciated, > Marc > > > > > >Article: 52039
Never had any luck getting STAPL to work with Xilinx. Altera STAPL works fine. "Ryan Gammon" <rggammon@alumni.uwaterloo.ca> wrote in message news:4vCZ9.2292$fO5.272948@ursa-nb00s0.nbnet.nb.ca... > Hello folks, > > I'm trying to sort out how to use jtag for things other than programming a > chip. I'm using the Xilinx webpack 5.1, including iMPACT. > > My goal is to shift an arbitrary bit pattern onto the outputs of a cpld. > > I've tried two ways of doing this: > > Method 1: > - Write a script of JTAG commands in SVF or STAPL > - Somehow run this script (I can create .svf/.stapl's in impact, but I > don't think I can run them) > > Method 2: > - Add test vectors to the jedec output. I've found instructions on how to do > this with ABEL, but nothing on adding them in a VHDL project. > - Run "functional test". > > My questions are: > - Can I run SVF's/STAPL's from iMPACT? > - Can I add test vectors to a .jed when the project is a VHDL project? > - Where do BSDL files come into this? > > Thanks for your help! > > Ryan. > >Article: 52040
In article <3e35c83e$0$27955$ba620e4c@news.skynet.be>,
"Marc Van Riet" <marcvanriet@yahoo.com> wrote:
| Hi,
|
| I'm writing a small processor core as a hobby. It is a small 16-bit core
| with about 20 instructions, including simple ALU functions, memory read and
| writes, stack operations, ... All instructions can be conditional
| (depending on the value of my 'working register'). Up to three operations
| can be combined in a single opcode, although not all combinations are
| possible.
|
| I was wondering if it would be do-able for me to port the GNU C-compiler to
| my own core. I guess it is possible, since the ARM has conditional
| instructions too, and it has multiple instructions in one opcode too.
A couple of years ago I ported GCC to an architecture similar to yours.
At that time, there wasn't any explicit support in GCC for conditional
operation or VLIW packing; I implemented conditional operation through
"if-conversion" in the peephole optimizer, and the VLIW packing was done
in a separate scheduling/packing phase in the assembler.
Now that GCC has IA-64 support, it may be a better target for your
architecture.
| But how long would that take me ? Anybody any experience in porting GNU-C to
| a similar core as mine ?
A simple basic port (without working out all the subtle bugs) can be
done in a man-month or so. It depends upon how far you want to take it.
Basic code generation can be done fairly quickly, but getting really
good code generation out requires more work (and is why many of the
existing .md files are so non-intuitive).
|
| Are there any alternatives ? The LCC compiler isn't an option I think,
| because their original target core doesn't have multiple-instructions or
| conditional code.
You might want to look at the Trimaran toolsuite:
http://www.trimaran.org/
It was done to research instruction-level parallelism for IA-64 / HP
Play-Doh architectures, which have similar features to your architecture.
Intel just announced the Open Research Compiler project on SourceForge:
http://ipf-orc.sourceforge.net
--
-- Tim Olson
Article: 52041Praveen, Is this a respin? A new product? Integration of some sort? What are your resources? Requirements? Based on your posts so far, your going to need help (at work). Here is what I can tell you: 1) Reinventing a PLX9050 is a bad idea. The device has read/write FIFO's, scatter gather DMA and other features that make it a product. To replicate this in a development effort to target a specific application would be (grossly) inefficient. Get your particular set of requirements - they would be a subset of what the 9050 is doing now(?)- and read on. 2) A PCI to local bus interface can be done with an off the shelf core droped into a programable logic device. The PCI/Local interfaces to the two sides of logic with (read/write) asyncronous FIFO's. You write the local "glue logic" to interface to the local bus with the FIFO's. The size of these FIFO's affects bursting and bus requirements - sizing them properly greatly affects performance and throughput. The local interface logic will need bus master and DMA capabilities. I'm not sure what your using for a local bus. There are also DMA control cores out there as well. This approach can get you off the ground quickly. I know the guys at www.opencores.org had something on this - you might want to check with them. "praveen" <praveenkumar1979@rediffmail.com> wrote in message news:ff8a3afb.0301290446.1e43aa45@posting.google.com... > Hello Mr.Kevin, > I have all documents of PLX 9050. Its little difficult to start about. > Which one to implement????.....this type of question keeps buging me. > It will good if i can get was reference PCI core detail(internal > design details), do u have any idea where i can get?????. I tried > opencore.com but he doesnot explain properly. > If anyone have any details regarding it . Please do tell > > waiting for reply > > praveenArticle: 52042
Hello, Generaly the simulator that comes with the vendor tools is not well suited for such things. You'd better consider using something more advanced like ModelSim. "Dave Wilson" <da_wils@hotmail.com> wrote in message news:6895fdb2.0301290641.fe11dd6@posting.google.com... > Hello all, > > I'm having a problem reading some test data into my quartus ii design. > > The .txt file has a simple format of integers in a column :eg. > > 234 > -3421 > 21 > etc .. . > > I created a new block in quartus for vhdl : > > LIBRARY ieee ; > USE ieee.std_logic_1164.all; > USE ieee.numeric_std.all; > LIBRARY std ; > USE std.textio.all; > > ENTITY Read_Vectors IS > generic( > Input_File : string := "c:\test_read_vectors_integer.txt" > ); > PORT( > clk : IN std_logic; > Ena : IN std_logic; > Xout_Value : OUT signed (15 DOWNTO 0); > ); > END Read_Vectors ; > ARCHITECTURE Version_1 OF Read_Vectors IS > begin > Read_in_Integer : process(clk, Ena) > file X : TEXT open READ_MODE is input_file; > variable L : line;-- line of file > variable Xin_file_integer_value : Integer; > begin > if Ena = '0' then > Xout_Value <=(others => '0'); > elsif rising_edge(clk) and not endfile(X) then > readline (X, L);--read input file > read (L, Xin_file_integer_value); --read value from file > Xout_Value <= to_signed(Xin_file_integer_value,16); > end if; > end process read_in_integer; > end Version_1; > > My plan is to use Xout_Value as the input to my design. The problem is > that I can't get this code to output the values under the quartus > environment. Is there another way to achieve this ?Article: 52043
Is there a formula for predicting how many Xilinx Slices a RAM will take? ie, suppose I have a 32 x 1k RAM. Without synthesizing it, what will be the area? Now if I add one bit of parity per word? One bit per byte? Surely there must be a way of telling how many slices an M x N RAM takes before the design is done???Article: 52044
If you use Virtex or later families, then the block RAM is
usually more suitable for a memory of this size.
Nevertheless, there is occasionally a need for a large memory
in the fabric. Each LUT is a 16x1 memory, so a 32x1K needs an
array of 32x64 LUTs. Additionally, you will need to have
muxing to get the data out to a common bus. In 4K/spartanI
devices, you can use the tristate buffers in each CLB to get
the mux for free. In virtex, there are fewer tristate buffers
per CLB than there are LUTs, plus any particular tristate
buffer can only connect to two of every four columns. For
Virtex, you pretty much have to build up multiplexers out of
additional LUTs. The number of LUTs per bit is 2^n-1 (it is a
tree structure) so the muxes (ignoring the F5 adn F6 muxes for
the moment) occupy an additional 31 LUTs per bit for your 1K
memory. You can take advantage of the F5 and F6 muxes to
rduce the size of the multiplexer tree at the expense of a
harder layout problem. In any case, unless you pipeline the
mux tree, you may not get the performance you need with such a
large memory implemented in the fabric.
A better alternative, if you can live with the sequential
rather than random access, is to use SRL16's to make a deep
shift register type memory. That way, you eliminate the
muxes, and can do the routing as nearest neighbor rather than
a tree structure for faster performance.
RM wrote:
> Is there a formula for predicting how many Xilinx Slices a
> RAM will take?
>
> ie, suppose I have a 32 x 1k RAM. Without synthesizing it,
> what will be the area? Now if I add one bit of parity per
> word? One bit per byte? Surely there must be a way of
> telling how many slices an M x N RAM takes before the
> design is done???
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin,
1759
Article: 52045First: A 32-bit wide and 1K deep RAM is best implemented in two BlockRAMs ( each 16 bits x 1K addresses.) The dual-ported nature is an additional bonus. Second: If you really want to use slices for smaller RAMs, remember that each slice has two LUTs, each of which is a 1-bit wide-16 addresses deep RAM. So at best, a slice = 32 bits. But you may need some address decoders and/or output multiplexers on top of that. Peter Alfke, Xilinx Applications ======== RM wrote: > Is there a formula for predicting how many Xilinx Slices a > RAM will take? > > ie, suppose I have a 32 x 1k RAM. Without synthesizing it, > what will be the area? Now if I add one bit of parity per > word? One bit per byte? Surely there must be a way of > telling how many slices an M x N RAM takes before the > design is done???Article: 52046
On a related topic, in lieu of a complete board/dev environment, is there IP available for the converter interfacing that will let one get converter data to/from a MCU or DSP properly (FIFO etc.; I think this is called an ADC bridge or something like that). Something free or open source would be especially nice. 8-) Thanks, TomArticle: 52047
Wayne <bigwayne@techie.com> wrote:
: Never had any luck getting STAPL to work with Xilinx.
: Altera STAPL works fine.
Did you try with alteras jamplayer? I had to apply appended patch to get it
to work with Xilinx generated STAPL files.
Bye
--- jamexec.c~ 2000-11-13 18:58:26.000000000 +0100
+++ jamexec.c 2002-12-03 22:05:25.000000000 +0100
@@ -816,6 +816,23 @@
long *long_ptr = NULL;
JAM_RETURN_TYPE status = JAMC_SUCCESS;
+ /* remove all white space */
+ while (statement_buffer[in_index] != JAMC_NULL_CHAR)
+ {
+ if ((!jam_isspace(statement_buffer[in_index])) &&
+ (statement_buffer[in_index] != JAMC_TAB_CHAR) &&
+ (statement_buffer[in_index] != JAMC_RETURN_CHAR) &&
+ (statement_buffer[in_index] != JAMC_NEWLINE_CHAR))
+ {
+ statement_buffer[out_index] = statement_buffer[in_index];
+ ++out_index;
+ }
+ ++in_index;
+ }
+ statement_buffer[out_index] = JAMC_NULL_CHAR;
+ in_index = 0;
+ out_index = 0;
+
while ((status == JAMC_SUCCESS) &&
((ch = statement_buffer[in_index]) != '\0'))
{
--
Uwe Bonnes bon@elektron.ikp.physik.tu-darmstadt.de
Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt
--------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------
Article: 52048
Hello again;
I am developing one project that has many cores inside, but one of these
cores depends on dynamic parameters. At this point I have two possibilities:
1st, program each parameter-dependent core inside my APEX20K200 and swicht
between as I need them. 2nd, option, the best, would be to reprogram only
*part* of my FPGA (kid of dynamic reconfiguration) depending on the
parameter.
Is there a good way to do that? or will I need to reprogram de entire
FPGA?
Letīs say that my static cores would use 70% of the FPGA and the
parameter-dependent ones would use each 20% while I could have as many as 10
of these.
Any clue will be appreciated.
Thank you.
Roberto Gallo
Article: 52049Hello All, I am using virtex connected to SDRAM and xilinx serial PROM. I am using Logic Analyzer to test the outputs. My design has clock dll,Block rams,and GSR. The data is transfered from block ram and written on the SDRAM, then it is read from SDRAM and written on another block ram. The problem is the following: when i download the program and run it using power on, i find(in the logic analyzer) that the read data which transfere from SDRAM to the second block ram is correct(or from the second time of the power on ). when i try to use power on again, i find that the data has been changed. if i try the third time, i find half of the data is correct or all of it, if i try many times, i get sometimes very strange results and sometimes correct data and so on...... Is the problem from the refresh? but of course my controller sends refresh commands in the desired time. and it does the SDRAM initilization in the beginning (nop for 100us, Precharge, 2 refresh cycles, mode register) . any one has solution? Thanks Talal
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