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"Markus Meng" <meng.engineering@bluewin.ch> wrote in message news:<3e3a2949$1_4@corp.newsgroups.com>...
> hi all,
>
> for my particular design I need 7 clocks. Four of them are fixed for those I
> use the
> four global clock inputs. I would like to use three additional clocks for
> decoding
> three serial synchronous lines. Each line has a clock and a serial data
> line. Now
> the question:
>
> Is it possible to feed this three pairs in the chip and to use their clock
> signals very
> locally in the design to drive internal serial to parallel converters? For
> that purpose I would
> need to clock some CLB's from other than the four global clock lines. I'am
> using
> VHDL. How do I constraint the design that this will work, if it is possible?
>
> best regards
>
> markus meng
>
> --
> Mit freundlichen Grüssen
> Markus Meng
>
> P.S. Achtung wir haben eine neue FAX-Nummer
> ********************************************************************
> ** Meng Engineering Telefon 056 222 44 10 **
> ** Markus Meng Natel 079 230 93 86 **
> ** Bruggerstr. 21 Telefax 056 222 44 34 <-- NEU !! **
> ** CH-5400 Baden Email meng.engineering@bluewin.ch **
> ** Web www.meng-engineering.ch **
> ********************************************************************
> ** You cannot create experience. You must undergo it. Albert Camus**
>
>
>
>
>
>
>
> -----= Posted via Newsfeeds.Com, Uncensored Usenet News =-----
> http://www.newsfeeds.com - The #1 Newsgroup Service in the World!
> -----== Over 80,000 Newsgroups - 16 Different Servers! =-----
Marcus -
I ran into similar issues trying to use more than 4 clocks and
posted some info on this a couple of weeks ago. I am using
Verilog, but I'm sure you can apply similar techniques to VHDL.
Here's what I found...
1) to route a general purpose pin onto a global clock line:
// a) tell Xilinx to bring the signal in with a normal buffer
// synthesis attribute clock_buffer clk_on_gp_pin ibuf;
input clk_on_gp_pin;
wire clk_as_global_clock
// b) use a magic XIlinx buffer to get the signal onto a global
// clock line.
BUFG u2BUFG (
.I(clk_on_gp_pin),
.O(clk_as_global_clock)
);
2) to route a general purpose pin as a non-critical clock:
// a) tell Xilinx to bring the signal in with a normal buffer
// synthesis attribute clock_buffer clk_on_gp_pin ibuf;
input clk_on_gp_pin;
3) to route a general purpose pin as a low skew clock:
// a) tell Xilinx to bring the signal in with a normal buffer
// synthesis attribute clock_buffer clk_on_gp_pin ibuf;
// b) tell Xilinx to use low skew clock resources
// synthesis attribute uselowskewlines clk_on_gp_pin yes;
input clk_on_gp_pin;
4) to convert a signal coming in on a global clock pin into
a general purpose signal:
input signal_on_gclk_pad;
wire signal_for_gp_use;
// Xilinx magic buffers for the data signals that come in
// on GCLK signals
IBUFG u1IBUFG (
.I(signal_on_gclk_pad),
.O(signal_for_gp_use)
);
OR TRY
// synthesis attribute clock_buffer signal_on_gclk_pad ibufg;
input signal_on_gclk_pad;
Wouldn't you think that Xilinx would have a nice App note that
**clearly** describes this?
John Providenza
Article: 52101Nial Stewart wrote: > > > I have wondered why Altera bother developing a synthesis tool in house. I > would have > thought they'd have been better concentrating on P+R tool development unless > Exemplar are charging an arm and a leg to include Leonardo. > > Nial. > Nial, To make a minor correction to what you said, the Quartus II 2.2's HDL synthesis is not really an Altera in-house product. I heard that Altera bought the source code of the synthesis tool from a start-up called Verific Design Automation. http://www.verific.com/ No, Verific Design Automation's website doesn't mention that Altera licensed their product, but if you read the licensing agreement of Quartus II 2.2 carefully when installing Quartus II 2.2, it mentions that you are installing software designed by Verific Design Automation. http://www.verific.com/customers.html By the way, Verific Design Automation's founder was also developed LeonardoSpectrum at Exemplar Logic. Kevin Brace (If someone wants to respond to what I wrote, I prefer if you will do so within the newsgroup.)Article: 52102
An addition to the low skew clocks for VirtexE and SpartanII you want the clock pins to be located on the top or the bottom of the chip and use the USELOWSKEWINES attribute on that net. In these two architectures, the backbone routes for low skew lines run along the top and bottom of the chip. For VirtexII architectures, it doesn't matter where the clock I/O is located since the routing is more flexible and you don't need the USELOWSKEWLINES attribute. Kate John Providenza wrote: > "Markus Meng" <meng.engineering@bluewin.ch> wrote in message news:<3e3a2949$1_4@corp.newsgroups.com>... > > hi all, > > > > for my particular design I need 7 clocks. Four of them are fixed for those I > > use the > > four global clock inputs. I would like to use three additional clocks for > > decoding > > three serial synchronous lines. Each line has a clock and a serial data > > line. Now > > the question: > > > > Is it possible to feed this three pairs in the chip and to use their clock > > signals very > > locally in the design to drive internal serial to parallel converters? For > > that purpose I would > > need to clock some CLB's from other than the four global clock lines. I'am > > using > > VHDL. How do I constraint the design that this will work, if it is possible? > > > > best regards > > > > markus meng > > > > -- > > Mit freundlichen Grüssen > > Markus Meng > > > > P.S. Achtung wir haben eine neue FAX-Nummer > > ******************************************************************** > > ** Meng Engineering Telefon 056 222 44 10 ** > > ** Markus Meng Natel 079 230 93 86 ** > > ** Bruggerstr. 21 Telefax 056 222 44 34 <-- NEU !! ** > > ** CH-5400 Baden Email meng.engineering@bluewin.ch ** > > ** Web www.meng-engineering.ch ** > > ******************************************************************** > > ** You cannot create experience. You must undergo it. Albert Camus** > > > > > > > > > > > > > > > > -----= Posted via Newsfeeds.Com, Uncensored Usenet News =----- > > http://www.newsfeeds.com - The #1 Newsgroup Service in the World! > > -----== Over 80,000 Newsgroups - 16 Different Servers! =----- > > Marcus - > > I ran into similar issues trying to use more than 4 clocks and > posted some info on this a couple of weeks ago. I am using > Verilog, but I'm sure you can apply similar techniques to VHDL. > > Here's what I found... > > 1) to route a general purpose pin onto a global clock line: > > // a) tell Xilinx to bring the signal in with a normal buffer > // synthesis attribute clock_buffer clk_on_gp_pin ibuf; > input clk_on_gp_pin; > wire clk_as_global_clock > > // b) use a magic XIlinx buffer to get the signal onto a global > // clock line. > BUFG u2BUFG ( > .I(clk_on_gp_pin), > .O(clk_as_global_clock) > ); > > 2) to route a general purpose pin as a non-critical clock: > > // a) tell Xilinx to bring the signal in with a normal buffer > // synthesis attribute clock_buffer clk_on_gp_pin ibuf; > input clk_on_gp_pin; > > 3) to route a general purpose pin as a low skew clock: > > // a) tell Xilinx to bring the signal in with a normal buffer > // synthesis attribute clock_buffer clk_on_gp_pin ibuf; > // b) tell Xilinx to use low skew clock resources > // synthesis attribute uselowskewlines clk_on_gp_pin yes; > input clk_on_gp_pin; > > 4) to convert a signal coming in on a global clock pin into > a general purpose signal: > > input signal_on_gclk_pad; > wire signal_for_gp_use; > // Xilinx magic buffers for the data signals that come in > // on GCLK signals > IBUFG u1IBUFG ( > .I(signal_on_gclk_pad), > .O(signal_for_gp_use) > ); > > OR TRY > // synthesis attribute clock_buffer signal_on_gclk_pad ibufg; > input signal_on_gclk_pad; > > Wouldn't you think that Xilinx would have a nice App note that > **clearly** describes this? > > John ProvidenzaArticle: 52103
Hey, I am basically implementing IEEE488.2 specs . I have coded in VHDL and downloaded the bitstream onto FPGA(Xilinx-Spartan2 ). What i have found is that sometimes the FPGA behaves very erratically after several rounds of downloading and that after a proper shutdown of the PC some RESET signal is resetting the FPGA which then configures properly. But now what is happening is that ----lets say i have some logic to pass when going from State A to State B. the logic involves some say- C or D. Basically two OR's. Now i downloaded the bitstream with this logic. Then i removed the logic D. And now my logic is simply C . But i find that the state B is reached even when the logic C is simply false .How can it be that way. is it the FPGA has some mem element which stores the prev logic and once that path has traced it follows that. though rationally it is not so i kno that as after reseting the FPGA should only configure to the new bitstream and not acc to the old one. But i am stuck as the states are wrongly being entered . Can someone suggest something................and help me ..................Article: 52104
"freny" <wacky_me@rediffmail.com> schrieb im Newsbeitrag news:446b88f2.0301311124.740ced95@posting.google.com... > is it the FPGA has some mem element which stores the prev logic If you mean that the FPGA keeps some "ghost image" of its configuration inside, then the answer id definitely NO. But many other things can go wrong. If you download a bitstream via JTAG directly into the FPGA, you MUST pull PROGRAM low before to reset the FPGA. The Xilinx software cantdo this. Another problem could be your state machine. Make sure that all input signals are synchronized (2 FlipFlop synchronizer), otherwise the state machine WILL get messed up. Its just a matter of time and encoding style, one-hot is very sensitive here (which is good for findig such synchronization problems) -- MfG FalkArticle: 52105
freny wrote:
> But i am stuck as the states are wrongly being entered .
>
>
> Can someone suggest something
Synchronize your inputs to the system clock.
-- Mike Treseler
Article: 52106Muthu, Xilinx Foundation Series software has not been sold to new customers since Q4 of 2001. ISE replaced it. There are many differences between the Foundation Series and ISE. The main one is that Foundation Series uses the Aldec schematic editor and Aldec Project Manager. ISE uses the Xilinx ECS schematic editor and Project Navigator. Let me know if you have any specific questions. Steve Muthu wrote: > Hi, > > What is the difference between the Xilinx Foundation Series and the Xilinx ISE. > > Regards, > MuthuArticle: 52107
Hi people, I went through some hard moments with the LogiBLOX utility that comes with Foundation 2.1i, trying to instantiate RPM constrained RAMs . The problem was, as I discovered later, that when LogiBLOX uses RPM to create the RAM macro, it uses a strange placement. I've read in the XAPP057 that the preferred way to place CLB rams is in vertical groups, to use the longlines or quadlines. Well, LogiBlox places the CLBs horizontal in a single row! So, as the device I am programming has only 20 columns of CLBs, when I try to implement a 32 bit wide RAM, the mapping tool tells me that I am ran out of space and should get a bigger device!!! I did not find another solution except using smaller LogiBlox created macros or generate my own memory (what I am doing now). Strange things happen in this life. Mauricio LangeArticle: 52108
David Collier wrote: > > I'm used to doing similar stuff on the Altera s/w which gives me a sort of > "edit the input waveforms and we'll simulate it and show you the output > waveforms" simulator ( I prefer test vectors, but beggars can't be > choosers ) > > I'm having real trouble ... most of the ISE versions around do not have a simulator embededd, unless you explicitly got or purchesed ModelSim. -- Tullio Grassi ====================================== Univ. of Maryland - Dept. of Physics College Park, MD 20742 - US Tel +1 301 405 5970 Fax +1 301 699 9195 ======================================Article: 52109
Thanks a lot, it works like a charm. David "Subroto Datta" <sdatta@altera.com> wrote in message news:BLw_9.238$wm5.20124716@newssvr15.news.prodigy.com... > David, > > This article should help answer your question. Basically the EDA tool > needs to be available in your search path. > > http://www.altera.com/support/kdb/rd05082002_6624.html > > - Subroto Datta > Altera Corp. > > "david lamb" <david.lamb@videotron.ca> wrote in message > news:YYf_9.27663$LR3.999729@charlie.risq.qc.ca... > > Hi, > > How do you tell Quartus where to find the leonardo executable file so that > > it is able to launch it automatically? In the project settings, I assigned > > Leonardo as the synthesis tool but when I start the compiler, it cannot > find > > Leonardo executable file. > > Thanks > > David > > > > > >Article: 52110
or the results of a septic system backup. I can't even blame it on the finger I
injured last month...wrong finger to miss the 'f'.
Tom Curtis wrote:
>
> "linear feedback shit registers" - sounds like the result of over-clocking a
> systolic processor!! :-)
>
> Tom C.
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 52111
thanks Mike, I already told freny that earlier today as a
result of a private
email sent to me before posting here. I'm reproducing here
what I wrote
for the benefit of others. This seems to come up far more
often than it
should. Perhaps too many software folks are buying into
thought that they
can design hardware with these newfangled tools. Here's what
I replied:
>The FPGA does not store a previous configuration. I t sounds
like you
>may have an input to your state machine that is not
synchronous to the
>state machine clock. This can cause a state machine to
misbehave if
>the input arrives close to the clock edge so that it is seen
on one clock
>by part of the state machine, and on the next clock by the
rest of the state
>machine. Asynchronous inputs have to be synchronized to make
sure
>they are seen by all destination flip-flops on the same clock
cycle.
followed by this more detailed response after a note asking
what the clock
has to do with the arrival of the input...
>If the input signal affects more than one flip-flop in the
state machine and
>the signal is not synchronous to the clock, you can get a
false transition.
>For example, consider a very simple state machine that
transitions from
>state ab= '00' to state ab='11' if input A is high, or is
supposed to stay in
>state '00' otherwise. If input A happens close enough to the
clock edge
>that the differential circuit delay permits that clock edge
to catch input A
>at flip-flop a but not at flip flop b, the state machine
advances from
>ab='00' to ab='10' instead of the intended "11' state. The
delays to the two
>flip flops will never be exactly the same. In order to avoid
this problem,
>the input must go to one and only one flip flop so that it
gets synchronized to
>the state machine. This is usually handled by adding a
synchronizing
>flip-flop on the input signals to the state machine.
At 12:39 AM 2/1/03 +0530, you wrote:
Mike Treseler wrote:
> freny wrote:
>
> > But i am stuck as the states are wrongly being entered .
> >
> >
> > Can someone suggest something
>
> Synchronize your inputs to the system clock.
>
> -- Mike Treseler
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin,
1759
Article: 52112Hi I'm currently working on a PCI card and am using the PCI64 core from Xilinx targetting Virtex2. I want to make the card universal (i.e. 5V and 3.3V PCI). I've implemented the Xilinx AppNote 646v1.2, regarding this. I have some concerns, shared by others in my area, regarding placing anything in the PCI signal path, while running at 66MHz. To save having to look it up: AppNote 646 suggests using IDT QuickSwitch devices to provide what amounts to a fast diode clamp with 0-3.3V swing, hence protecting the Virtex2, incurring a max of 250ps delay and 5pF capacitance. (Don't have doc in front of me so these figures are from memory) The card is for multiple test scenarios, and hence we want it to be usable in 32/33 PCI (in nice cheap PCs) for some applications, while also 64/66 compatible when data transfer rates are a priority and the additioanl cost of a server board is justified. Does anyone out there have any experience of implementing this AppNote or of using another method to provide the voltage conversion/protection ? Many Thanks GordonArticle: 52113
Mike, This is a known issue that will be fixed in the next major software release. A solution record is coming soon to our website (support.xilinx.com). The work aroud is to use the FPGA Editor locations in the UCF file. You can't use the Floorplanner to see it but it is there. You can verify it in FPGA Editor. Kate M Schreiber wrote: > All, > I have noticed a difference between the xilinx floor planner tool > and FPGA editor. In FPGA Editor the DCM's seem to be labeled (in a > xc2v1000 part) DCM_X0Y0, DCM_X1Y0, DCM_X2Y0, DCM_X3Y0 (from left to > right) and then on the top as DCM_X0Y1, DCM_X1Y1, DCM_X2Y1, DCM_X3Y1. > I think that this is the correct notation, but when I open up the > floor planner they are labeled as DCM_X0YO, DCM_X2Y0, DCM_X4Y0, > DCM_X6Y0.......then on the top as DCM_X0Y1, DCM_X2Y1, DCM_X4Y1, > DCM_X6Y1. This becomes a problem because I lock my DCM's to specific > quadrants, and when i map one of them to DCM_X3Y0 it does not show up > as being placed in the floor planner. Can anyone explain why this is? > I am using Xilinx ISE version 5.1.02i. Also I am using engineering > silicon, with the engineering silicon system variable set > (XIL_BITGEN_VIRTEX2ES). > Thanks in Advance, > MikeArticle: 52114
> Then, the host decides what address to assign to my device looking for > the weight of the lowest bit set, so, if when BAR0 gives back > 0xfffff000, the lowest bit is the 11th, or a decoding space of 2k, > right? 0xFFFF_F000 is 12 bits (bits 11-0), or a 4k space. > Then, my card should end with an address multiple of 2k, 4k. in any > location of the memory space, that is what I understood. After the configuration WRITES all 1's to the BAR, and reads back 0xFFFF_F000 it then WRITES a new address to the board that will be the start address of your 4k memory. > So, is the base address assignment a multipass cycle? I mean, the host > first writes 0xffffffff to my BAR0, the it reads the data back, then > it writes the assigned base address to my BAR0? Correct. > I did the following: preset my BAR0 register to 0x00000005 (the > BAR0(0) bit indicates the space, memory or i/o) and get, as result, > the following address assigned: 0x02000001, what could that possibly > mean? You get a 4k space starting at 0x0200_0xxx. BUT, why are you setting bit 0 to 1 for? You are asking for 4k of I/O space...and you probably really want memory space. Why are you setting bit 2? Setting bit 2 and 1 to 10b asks the system to locate you in 64 bit address space... I'd suggest presetting bit 0 to 0 and bit 2 to 0 as well. These should not be presets, but hard bits...that can't be written. No need to implement them as a register, just use an enablable buffers and tie the inputs to ground for the lower 12 bits of the BAR. AustinArticle: 52115
Hi, Can Anyone tell me why static timing analysis is done after synthesis and implementation ? Regards, SkillieArticle: 52116
Steve Lass <lass@xilinx.com> wrote in message news:<3E3AEB96.4ECB7359@xilinx.com>... > Muthu, > > Xilinx Foundation Series software has not been sold to new customers since > Q4 of 2001. ISE replaced it. > > There are many differences between the Foundation Series and ISE. The > main one is that Foundation Series uses the Aldec schematic editor and > Aldec Project Manager. ISE uses the Xilinx ECS schematic editor and > Project Navigator. > > Let me know if you have any specific questions. > > Steve > > Muthu wrote: > > > Hi, > > > > What is the difference between the Xilinx Foundation Series and the Xilinx ISE. > > > > Regards, > > Muthu Here we have installed both Xilinx Foundation 4 and Xilinx ISE 4. Will there be any differences in the performance wise? ie., If i run a same .edf for place and Route will there be any difference? Regards, MuthuArticle: 52117
Hi, After a place and route is done, the first thing that one looks for is that whether timings are being met or not.. Well there is no point of having a design is that is placed and routed but does not meet the speeds that it is aimed for. A static timing analysis allows the designer with the information of timings on various nets, which could be form from flops to flops, or pads to flops, blockrams etc.. Also with the time as the company introduces new fpga's pieces into the market, the timings of the fabric might not be same as the previous lot of components. Then it gives speeds update that are used by the static timing analyser to give the user the information about a previously PAR-ed design, whether it will work with new speeds or not. Perhaps that answers your query Amit "Skillwood" <skillwoodNOSPAM@hotmail.com> wrote in message news:<b1fj7l$12qoi7$1@ID-159866.news.dfncis.de>... > Hi, > Can Anyone tell me why static timing analysis is done after synthesis and > implementation ? > > Regards, > SkillieArticle: 52118
Hi all, In many designs I experienced some problems (i.e. the FPGA didn't work as expected) when I connected a Spartan2E FPGA output pin to the input lines of a PC parallel port (Ack, Busy...). When I used output lines only (D0, D1...) I didn't get any kind of problem. Why this happends? What's the right way to connect a parallel port to the Spartan2? Thanks in advance. SteveArticle: 52119
Hi, I'm trying to find the detailed achitecture of the interconnect in Virtex device, but in the datasheet I only find a general decription of it. Especially about the GRM(General Routing Matrix) used in Virtex. I'd like to know what is the detailed structure of GRM, like which switch can connect to which switch. I was unable to find this information on your datasheets. I also want to know the detailed interconnect structure of VirtexII, in perticular the structure of the switch matrix that connects the vertical routing channels and the horizontal routing channels.Article: 52120
Does anyone know where I can find the documentation for XDL(Xilinx Description Language)? It should be a utility that comes with ISE, but I can't find anything about XDL on the ISE software documentation on www.xilinx.com. Thanks a lot.Article: 52121
"Steve" <NOSPAM@tin.it> schrieb im Newsbeitrag news:JCS_9.72638$ZE.1957613@twister2.libero.it... > Hi all, > In many designs I experienced some problems (i.e. the FPGA didn't work as > expected) when I connected a Spartan2E FPGA output pin to the input lines of > a PC > parallel port (Ack, Busy...). > When I used output lines only (D0, D1...) I didn't get any kind of problem. > Why this happends? > What's the right way to connect a parallel port to the Spartan2? Be carefull, the data lines are active push-pull outputs (mostly), where control outputs are mostly open drain outputs with 4.7 K pull-ups. The signal quality from the parallel port is often not really good, so using STROBE as a clock for a FPGA is a big NO-NO, the slow edges, ringing and reflections will cause doule clocking -> mess up of state machines. Do a oversampling of the control lines, this is IMHO a clean solution. -- MfG FalkArticle: 52122
"Sean" <creon100@yahoo.com> wrote in message = news:b97bab2f.0301300723.6c18c86c@posting.google.com... > I've looked through every datasheet I can think of and still can't > come up with a clear answer to this. >=20 > I've got a system that has a TI DSP processor, an EPC16, and an > EPF50kE on board. On power-up the EPC16 programs the Flex10ke, but > when the whole system is reset I want the flex to be reprogrammed.=20 > I'm actually taking the reset switch through the Flex10ke so that I > can have some control over that signal at power-up, so what I'd like > is some way to just use an output from the flex to initiate its own > reconfiguration. However, I've been unable to glean if that is > possible or not. I can't tell if this would be something I'd trigger > via the flex or the EPC16 (I believe on Xilinx parts the programming > device triggers the programming sequence), but I think it's something > I trigger via the flex10ke. Is this possible, the datasheets seem to > imply it is, but I can't really figure out how to do it. Thanks guys. Hi Sean, A couple of questions about your design: - Is the EPC16 only used as serial configuration device for the FLEX, or = does it also function as a parallel Flash PROM to store the software = application for the TI DSP? In others words: are the "parallel Flash" = I/O pins of EPC16 left unconnected or not?=20 - What do you exactly mean by: "On power-up the EPC16 programs the = Flex10ke, but when the whole system is reset I want the flex to be = reprogrammed."? Do you want to reprogram the FLEX during system reset, = or after the system is reset (e.g. the reset is deactivated?) - Do you want to reprogram the FLEX itself, or do you want to reprogram = the EPC16 holding the configuration bitstream for the FLEX? - Taking a reset switch through a (volatile SRAM-based) FLEX device to = have "some control" of things during power-up doesn't sound like such a wise thing to do, since during power-up the FLEX device itself is = not operational (yet), and thus it is hard to have control of it. To summarize, my question is: what do you really want? Does the = reprogramming have to be dynamically (e.g. online), or is it allowed to = do a power-up sequence (e.g. offline). What (re)programming = infrastructure do you use (passive serial,JTAG, etc.) Best regards, JaapArticle: 52123
"Florian" <flo78de@yahoo.de> wrote in message news:<3e362717$0$3025$9b622d9e@news.freenet.de>... > Hello, > i'm designing a board with a VirtexII that takes masses of data from several > inputs and stores it in 2 DDR-RAM channels. For the ram-controller i'm > orientating on xapp200. It says to feed the ddr_clk and possibly ddr_clkb > back into the fpga. My question is how to route this feedback on the pcb? I > see several possibilities: > - shortest way from pad to pad > - from the series termination resitor > - from the ram-socket > - from the parallel termination resitor > And how do i terminate this feedback? (DCI is not an option) > > Any help welcome > > Thank You in advance > Florian Your objective should be to make the DDR socket get as close as possible to the same (phase) clock as the controller. That usually means matching trace lengths from the point of clock distribution to the SDRAM with the length to the controller, which is either a feedback clock or an input clock, depending on your distribution scheme. Where you pick it up is a signal integrity issue, which somewhat separate from the trace length matching issue. Note that the clock inputs to the DDR SDRAM are not (single-ended) SSTL-2, but are differential. You need both parts of the differential signal. -BorisArticle: 52124
Hi, I have a digital signal representing a sinewave of amplitude 0.5. The signal has 32 bits with 16 bits before the decimal point and 16 bits after. Obviously, modelsim doesn't care about the decimal point so when I choose 'Analog' for the signal's format in the waveform, the sine wave doesn't fit on my monitor since modelsim thinks it has a very large amplitude...but all the 1's are in fact after the decimal point...Is there a way to go around this problem? Thanks David
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