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From: "Dennis Maasbommel" <aabbccdd00@hotmail.com> Subject: Modelsim generating (Sigsegv BadPointer Access)-error on winXP Date: zondag 18 mei 2003 22:59 Hello again, you all ! The advice on my previous post (see below) was to upgrade to Modelsim version 5.7. So I did, but unfortunately, the program running on my winXP system, still collapses when I try to add signals to the wave window. And here I have no solution or workaround yet. It occured to me, that perhaps the system collapses if I'd try to add signals to the wavetable, if they haven't been forced a particular value at all. So I forces the signals a value and simulated the model for some time, and THEN added the signals to the wave table. Unfortunately, still no success. Is somebody able to help this student out here? Thanks in advance. Best regards, Dennis Maasbommel ----- Original Message ----- From: "Dennis Maasbommel" <aabbccdd00@hotmail.com> Newsgroups: comp.arch.fpga Sent: Thursday, May 08, 2003 3:01 AM Subject: Modelsim generating (Sigsegv BadPointer Access)-error on winXP > Hi Folks, > > Using FPGA Advantage V5.4 on my WinXP SP1 system, > I am having some problems with the integrated modelsim (v5.6d) > component. > > After a succesful compilation, I try to simulate the model, > But with many models I get this error > > ** Fatal: (SIGSEGV) Bad pointer access. > > > I searched using Google and it took me to the GNU C Library, > where this error was explained; From this point my guess is > that maybe Modelsim is not suitable for WinXP yet. > > I have tried all the compatibilty modes > (i.e. win95, win98/winME, winNT4 SP5, win2k) > but neither of these modes prevented modelsim from > generating this error. > > I have also tested a very simple model, which COULD be simulated, > but unfortunately Modelsim collapsed (program exits without further notice) > when I wanted to add signals to the wave-table. I guess maybe this has > someway the same cause as the 'Bad Pointer Access'-error. > > Beside this behavior, I have no other clue that my installation > version is corrupted > > Does any of you have experienced likewise problems with this tool, > and/or know how to solve these problems? I would be glad to hear it! > > Best Regards, > Dennis Maasbommel > >Article: 55801
"lc" <cupido@kkk.mail.ua.pt> wrote in message news:1053038695.922327@newsfront2... > Hello, > > What would be the simplest and smallest CPU core for an FPGA ? > I saw a lot of cores that mimic existing controllers > but I would not mind to have something simpler. > Low LE count is my goal. > > Anybody had similar objectives? Any ideas ? > Would somebody point me in the right direction ? Microcore looks interesting: http://www.microcore.org/ I first looked at a long time ago but it hadn't progressed very far. It now looks as if it is quite viable. I'll see if I can put it into a Spartan-II. Leon -- Leon Heller, G1HSM leon_heller@hotmail.com http://www.geocities.com/leon_hellerArticle: 55802
hi all, can anyone tell me why should we use DCMs in FPGA rather that going for simple counter for clock division What are other uses of DCMs? regdsArticle: 55803
All true. The problem with two single processor machines is the doggone
dongles and moving the files to the right machines can be awkward. Of course
network licensing fixes some of that...at a cost.
"Nicholas C. Weaver" wrote:
> In article <vcj50bhle8hrff@corp.supernews.com>,
> Hal Murray <hmurray@suespammers.org> wrote:
> >>A dual processor isn't going to buy any improvement in synthesis, place
> >and route
> >>times, but if you are using the machine for other things too, it wil
> >let you stay
> >>productive while these tasks complete.
> >
> >Only if you have enough memory for both the CAD tools and whatever
> >else you want to do.
>
> But if you are swapping, things are going to be miserably slow,
> period.
>
> --
> Nicholas C. Weaver nweaver@cs.berkeley.edu
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 55804
Counters can only divide clocks by an integer amount. DCMs can multiply the
clock by a fraction or integer so that your internal clock is not as dependent
on your external clock frequency. they also let you adjust the phase of the
clock, and for high speed clocks permit control of the skew between the clock
and the external I/O.
LIJO wrote:
> hi all,
> can anyone tell me why should we use DCMs in FPGA rather that going for
> simple counter for clock division
> What are other uses of DCMs?
>
> regds
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 55805Hi all, I took over an project with 9054 PLX chip. Old software uses generic windriver to access hardware via simple memory reading/writing. Now I wan't to use PLX API, but... how can I acces memory cell with API functions?? I can acces the chip through API, reading PLX registers an so on. but no chance to access hardware behind plx (with old software everything works fine...) Any hints? Thx for help, ChristianArticle: 55806
Hello, While writing the testbench which all test cases should i include in my testbench to fully test my PCI core. waiting for reply praveenArticle: 55807
In article <m34r3qruws.fsf@scimul.dolphinics.no>, Petter Gustad <newsmailcomp5@gustad.com> wrote: >> Dual processor has a big advantage: you can get other work done on the >> same system without (mostly) bogging down your CAD flow. It's a tough >> call. The other option is a KVM switch and a "dinky system" so you >> can do web browsing or something while waiting for the tools to run. > >Personally I think uniprocessor systems gives you best price/ >performance. If you run UNIX/Linux you can simply submit your >synthesis and par job into a cluster and free your desktop for >interactive work. > >If your tool takes advantage of multiple CPU then it's a different >story. Also, Ray Andraka points out the headaches/costs of software. If the work you want to do is some more editing on another project or something, 2 machines -> 2 CAD tool copies. And if they are annoying and heavily copy protected, congratulations, you MORE than compensated for the cost of a dual processor setup. -- Nicholas C. Weaver nweaver@cs.berkeley.eduArticle: 55808
Vlsi Champ wrote: > Hello, Can anybody please tell me the difference between the Xilinx ISE > (Foundation) tool & Xilinx Webpack tool? The GUI appears to be the > same... Also if possible, please mention the costwise difference too. > Thanks in advance, Regards, Rajesh.... Read the Xilinx website a bit more careful! ... and find out that the Webpack is a free version of the complete ISE, but it supports only the lower-end devices. Regards, Mario PS: You should not make HTML-postings.Article: 55809
"Peter C. Wallace" <pcw@freeby.mesanet.com> wrote in message news:<pan.2003.05.15.23.24.22.967566.16848@freeby.mesanet.com>... > On Thu, 15 May 2003 15:52:51 -0700, lc wrote: > > > Hello, > > > > What would be the simplest and smallest CPU core for an FPGA ? I saw a > > lot of cores that mimic existing controllers but I would not mind to > > have something simpler. Low LE count is my goal. We have a 16-bit microprocessor that was designed to have very simple VHDL code so that our students can play around with it. It also has a particulary nice assembler language. It's not the smallest an simplest but it is small and simple ;-) The web page is in german, but the documentation on the bottom of the page is in english. http://www.fpga.de/tiki/tiki-index.php?page=IpK16 Kolja SulimmaArticle: 55810
nweaver@ribbit.CS.Berkeley.EDU (Nicholas C. Weaver) writes: > In article <m34r3qruws.fsf@scimul.dolphinics.no>, > Petter Gustad <newsmailcomp5@gustad.com> wrote: > >> Dual processor has a big advantage: you can get other work done on the > >> same system without (mostly) bogging down your CAD flow. It's a tough > >> call. The other option is a KVM switch and a "dinky system" so you > >> can do web browsing or something while waiting for the tools to run. > > > >Personally I think uniprocessor systems gives you best price/ > >performance. If you run UNIX/Linux you can simply submit your > >synthesis and par job into a cluster and free your desktop for > >interactive work. > > > >If your tool takes advantage of multiple CPU then it's a different > >story. > > Also, Ray Andraka points out the headaches/costs of software. If the > work you want to do is some more editing on another project or > something, 2 machines -> 2 CAD tool copies. And if they are annoying > and heavily copy protected, congratulations, you MORE than compensated > for the cost of a dual processor setup. I have to admit that I've never dealt with dongles. All the sofware I use is based upon flexlm, (Synopsys, Cadence, Avant!, etc) except Xilinx ISE (where I manually have to make sure that I don't run more instances of the SW than I have licenses). I have only one copy of the sofware residing on the NFS/Samba server. Petter -- ________________________________________________________________________ Petter Gustad 8'h2B | ~8'h2B http://www.gustad.com/petterArticle: 55812
lc, Well, another first for X: a uMouse with a soft uC. Austin http://members.aol.com/ucimicromouse/index.htm lc wrote: > > Hello, > > What would be the simplest and smallest CPU core for an FPGA ? > I saw a lot of cores that mimic existing controllers > but I would not mind to have something simpler. > Low LE count is my goal. > > Anybody had similar objectives? Any ideas ? > Would somebody point me in the right direction ? > > Thanks. > > Luis Cupido. > > P.S. - The application is logic intensive (a very large correlator) > however the system output happens only once every second. > Using logic for the output processing become tremendously big, > a total waist of resources for something that happens only once > every second.Article: 55813
On 19 May 2003 02:01:50 -0700, tsvika.hirst@minicom.com (Tsvika Hirst) wrote: >I need to specify a workstation that will use for FPGA development >(around 300K gates) i.e. simulate, synth, place and route flow (e.g. >Foundation ISE + ModelSim XE). I plan to use RedHat Linux, as I was >told it improves stability and 30% performance relative to >Windows2000. I use a dual-processor setup myself, with Windows 2000 O/S. Nothing against Linux, but using an O/S that a lot of other users run makes it (slightly) more likely that any problems I encounter have already been tripped over by someone else. For those of you with dual-processor systems, a question: which motherboard are you using? I'm running an old Asus CUV4X-D with two 1GHz Pentium IIIs and 1.5GB of memory--kind of ancient, but it works very well. What are today's best choices for dual-processor boards? Bob Perlman Cambrian Design WorksArticle: 55814
Has anyone experience of BGA balls separating from the PCB pads when cycling the boards at thermal extremes e.g. -40degC to +85degC. I understand that there are cases where outer balls/pads have been seen to separate on physically large BGA devices but need to understand what physical size this is i.e. 35mm, 40mm?? This should be reduced by going for well matched Tce of BGA substrate to PCB material but are there other issues worth considering. GerArticle: 55815
Martin, Altera has encrypted HSPICE files available for Stratix and Cyclone (and other) devices. Please contact your FAE for access to these files. FPGA vendor (Altera and others) HSPICE files are encrypted to protect the intellectual property of our design and of our fab partner. Sincerely, Greg Steinke gregs@altera.com "Martin Schoeberl" <martin.schoeberl@chello.at> wrote in message news:<T0txa.65849$_b1.689078@news.chello.at>... > Greg, > > thanks for your explanation and the link. I was only looking for literature > of the devices I'm actually using. But there is a lot more info on a little > bit older devices than Cyclone. I expect the output buffer of the Cyclone > are simmilar with the of Stratix. > > About simulation: I would like to simulate my load, but I've only SPICE and > no tool for ISIS modles. But I think there are no SPICE models available > (for both A and X), right? > > Martin > -- > -------------------------------------------------------- > JOP - a Java Processor core for FPGAs now > on Cyclone: http://www.jopdesign.com/cyclone/Article: 55816
Hello, The EPM7032QI44-15 is an original MAX 7000 family device. As such it does not have JTAG support for either BST or ISP. The newer MAX 7000S devices (and all subsequent CPLDs) support JTAG for ISP, and many of these support BST as well. The details are found in table 4 of the MAX 7000 datasheet, found at this link: http://www.altera.com/literature/ds/m7000.pdf Another point: The details of the ordering code break down like this: EPM7032 = 32 macrocell MAX 7000 device (not MAX 7000S, MAX 7000AE, etc) QI44 = 44 pin QFP, Industrial temp -15 = 15 ns tpd speed grade. The details for this and other device ordering codes are shown in the Ordering Information document: http://www.altera.com/literature/gn/ordinfo.pdf On newer devices this information is also included in the device datasheet for easier reference. Sincerely, Greg Steinke gregs@altera.com "Selenium" <uranium2003@libero.it> wrote in message news:<YMNxa.11912$Ny5.354869@twister2.libero.it>... > On some telecom devices boards I have found some CPLDs EPM7032QI44-15, > unfortunately on the site of the Altera it is not it traces of it. > > Are these CPLDs compatible JTAG? > > Byez.Article: 55817
Jan Panteltje wrote: > ERROR:Place:1993 - Components udc0_uf10_N324 and udc0_N1466 are using the > F5/F6MUX resources. The component udc0_uf10_N324 is part of a carry chain > macro. Please RLOC components udc0_uf10_N324 and udc0_N1466 together. I haven't seen this particular error before but I believe I can explain it. The component "udc0_uf10_N324" contains a portion of two different multi-slice shapes, a carry chain structure and an F5/F6MUX structure. Apparently the placer is having problems reconciling the placement requirements of both shapes and is asking for help via the use of RLOC constraints that would guide the relative placement of the logic involved. There are other possible solutions depending on the root cause of the problem. If the two shapes ended up sharing the same slice due to an unrelated pack then anything that blocked that unrelated pack would avoid the problem. Using a larger device would work (and would also be a good test of the unrelated pack theory) but another way would be to assign one of the shapes to an area group and then set a "compression" attribute of zero which will block unrelated packs for that logic. There is no need to actually define a range to the area group. Example UCF syntax: INST "some/hierarchy" AREA_GROUP = AG1 ; AREA_GROUP "AG1" COMPRESSION = 0 ; This trick can also be used to guard critical logic from unrelated packs which can lead to conflicting placement needs WRT timing. BretArticle: 55818
"Dennis Maasbommel" <aabbccdd00@hotmail.com> wrote in message news:S7lya.1857672$sj7.80152275@Flipper... > From: "Dennis Maasbommel" <aabbccdd00@hotmail.com> > Subject: Modelsim generating (Sigsegv BadPointer Access)-error on winXP > Date: zondag 18 mei 2003 22:59 > > Hello again, you all ! > > The advice on my previous post (see below) was to upgrade to Modelsim > version 5.7. > So I did, but unfortunately, the program running on my winXP system, still > collapses when > I try to add signals to the wave window. And here I have no solution or > workaround yet. > > It occured to me, that perhaps the system collapses if I'd try to add > signals to the wavetable, > if they haven't been forced a particular value at all. So I forces the > signals a value and simulated > the model for some time, and THEN added the signals to the wave table. > Unfortunately, still no success. > > Is somebody able to help this student out here? Sure. It sounds like you're running a badly cracked version. If not, contact ModelTech for proper technical support. Cheers, JonBArticle: 55819
Hello,
I tried to implement fir using DA. I studied examples from book
Uwe Meyer-Baese titled "Digital Signal Processing with FIeld
Programmable Gate Arrays".
I wrote fir in Matlab with coefficients h[] = {2 3 1} and for input
x={1, 3, 7} i received y={2, 9, 24, 24, 7, 0, ...}.
And my question is:
Why is for DA_fir on output value y=18 (temporary acc p = {0, 24, 28,
18}) ? (Example 3.6 on pagee 98). Why is this different from "direct"
response?
How can i use da_fir instead of "direct" fir? And how i can receive
the same output values like for "direc" fir?
I would like to compare techiques such like CSD, RAG algorithm and
distributed arithmetic, and i stopped on DA :(
Regards,
PawelT.
Pozdrawiam,
PawelT
Article: 55820
Bob,
I've got two systems running here. One is a dual PIII-800 NT machine with
an ASUS MB, don't recall which one with 1GB memory. The other is a dual
K7-1.8 GHz running win2K on an ASUS A7M266-D board with 2GB memory. The
K7 machine throws many more BTUs into the room and is also much harder on
the ears, so I use the older NT machine except when I need the extra
horsepower. I've been happy with the ASUS boards over the years, so my
next system will also be ASUS.
I agree with your sentiments regarding Linux. It is also worth noting
that you can run just about anything under the windoze with a fairly
simple install. Many apps need a considerable amount of set up to get to
run under Lixux. FWIW, I have not had any stability problems with the NT
machine once I get it all set up correctly. Win2K did give me some
heartburn with Xilinx4.2 that never did get resolved.
Bob Perlman wrote:
> On 19 May 2003 02:01:50 -0700, tsvika.hirst@minicom.com (Tsvika Hirst)
> wrote:
>
> >I need to specify a workstation that will use for FPGA development
> >(around 300K gates) i.e. simulate, synth, place and route flow (e.g.
> >Foundation ISE + ModelSim XE). I plan to use RedHat Linux, as I was
> >told it improves stability and 30% performance relative to
> >Windows2000.
>
> I use a dual-processor setup myself, with Windows 2000 O/S. Nothing
> against Linux, but using an O/S that a lot of other users run makes it
> (slightly) more likely that any problems I encounter have already been
> tripped over by someone else.
>
> For those of you with dual-processor systems, a question: which
> motherboard are you using? I'm running an old Asus CUV4X-D with two
> 1GHz Pentium IIIs and 1.5GB of memory--kind of ancient, but it works
> very well. What are today's best choices for dual-processor boards?
>
> Bob Perlman
> Cambrian Design Works
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 55821I agree that the use of the ECS tool is not purely fun, simply because of some of its quirks and foibles (e.g. not fixing connection changes until after the schematic is saved, hence, reporting "errors" that are no longer there) but if you look at the 14 pages of HDL that are produced buy a rather small and simple schematic, you begin to see why one might do that. What's more, with no "LINT" utility for the VHDL, as is included with most other freeware packages, it's not very convenient to hand-enter a 14-page file to represent what amounts to four or five TTL components. Now, if one could do, completely, some of these "small" tasks using ABEL, without having to tiptoe around the "XILINX-isms" it might work out OK. Most of the trouble I've had with this task has been with the XILINX-isms, i.e. how to specify what I want from the characteristics of the individual device, and how to get the software to understand what it, itself, has done. There are features, e.g. the default "KEEPER" state of device pins that isn't automatically overridden by the UCF, and the fact that pin definitions asserted in ECS or the UCF, are not necessarily heeded by the software, that have been at the heart of my difficulties. BTW, inasmuch as there's no LINUX version of this software, (I'm told release 6 will be LINUX-compatible) this is probably not the place to advocate the use of LINUX. Richard Erlacher "Uwe Bonnes" <bon@elektron.ikp.physik.tu-darmstadt.de> wrote in message news:ba12po$k7k$1@news.tu-darmstadt.de... > Richard Erlacher <richard_no_junk_mail_4_me at idcomm.com> wrote: > : Once I have time to upgrade my current box from '98 (which I trust) to XP or > : 2K (neither of which I trust), which change is planned for a week or two > : from now, I'll undoubtedly switch to whatever the current freeware > : (WEBPACK?) is. I'm probably done with buying software from XILINX, though. > > I run Webpack with Linux/Wine. No need for XP beside wine emulating XP :-) > *) > > : What my problem here has been is an unwillingness of the software to > : implement constraints clearly spelled out in the User Constraint File (UCF), > : which I'd have thought would have precedence over defaults that are hidden > : where you can't see 'em. > > Constaints work for me ( pin placement, setting slew rate). With the relativ > fixed timing model, however timing constraints probably won't help > much. Either the logic can be implemented with the speed you need and the > way you write it, or not, but timing constraints won't help for a CPLD. > > : It's taken me almost two weeks to get this EVB (and it's not the board's > : fault!) to produce output. Not even a simple buffer which puts out a clock > : coming in on a global clock pin was trivial to make appear, and it still > : doesn't routinely work. Multiple compiles (RERUN ALL) of the same source > : seemingly produces arbitrarily different output, though it just as > : frequently produces the same, but erroneous, output. What I used to test > : the entry system was a set of equations that I wanted to ABEL from PALASM, > : easily accomplished via the @alternate directive, but that quickly fell > : apart as I (not an ABEL expert) couldn't figure out how to port the case > : statements that represent a couple of muxes. Subsequently I simply used ECS > : to enter the little test circuit in schematic form. Doing this in PALASM > : for a 24-pin PAL took less than half a day including the time to build a > : board and assemble it. I've gotten the thing to work on the EVB, though all > : bets are off if I have to reprogram the board again. > > I can't imagine that any schematic entry for pure logic is mostly fun. When > I tried to implement some module in ECS for better documentation, I nearly > got crazy. Take the time to learn HDL, keeping the structure of the target > hardware in mind. It probably will pay off. > > : I've been frustrated somewhat by the software's unwillingness to implement > : constraints such as PULLUP ( which apparently conflicts with the hidden > : "KEEPER" attribute) and my own inability to distinguish between FAST slew on > : the output and SLOW slew rate, which appears to differ only by a nanosecond > : or two, but that's probably because of the absence of a realistic load. The > : 1.2 volts of overshoot/undershoot and half volt of ringing (3.3-volt I/O) > : are probably because of the long traces leading to the connector pins. > > Keep in mind that you can use either KEEPER or PULLUP on one chip, but not > together. I've learnd the hard way too. > > How do you measure overshoot/undershoot? Remember to ground the probe as > short as possible to a good ground, or otherwise you get a false > indication. Try with the SLOW attribute if ringing really bugs that > design. For me, the .tim Timing report reports 4 ns more delay for a -7 > device. > > : Since we've talked I guess we agree that there really isn't a good ground > : reference on the board to which one can attach probes, etc. That and the > : lead lengths to the connectors are probably the only problems with the board > : itself, and, aside from, maybe, providing a good ground reference, I doubt > : the EVB could have been done much better. > > A multilayer board with a dedicated ground layer and probe attach points > would help. > > : I appreciate the help offerred by the several folks who've contacted me via > : email. It's been enlightening. I'm sure some of you have been amused with > : the 'scope display pic's I sent. > > : Nevertheless, I'm still frustrated about the state of the software. If any > : of our software guys offerred to release something that behaved as > : peculiarly as this, my boss would probably take 'em out back and shoot 'em. > : That's just a culture thing, though. > > At least the webpack people are responsive to error reports. I've seen other > behaviour in other cases... > > Bye > > *) Webpack/Linux/Wine is not for the faint hearted... > -- > Uwe Bonnes bon@elektron.ikp.physik.tu-darmstadt.de > > Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt > --------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------Article: 55822
Hi, Does anyone have hands-on (!) experience integrating the Altera Ethernet MAC IP-core into a Nios-based design (Stratix) ? This MAC IP-core has an MII interface to an external PHY device, and a AHB interface which can be connected to the Nios Avalon bus using a AHB to Avalon bridge (included in SOPC Builder). Does anyone have an indication of the real-life (!) achievable performance/bandwidth when a 100 Mbit PHY is used, and a Avalon DMA controller is attached to lessen the burden for the Nios CPU? Experience with this MAC IP-core in combination with ARM (Altera Excalibur) is also valuable to us. We have evaluated Nios in combination with uLinux (www.microtronix), which worked out quiet fine, but for ethernet this designkit makes use of external chipsets which have both the MAC and PHY integrated (CS8900 for 10 Mbit, LAN91C111 for 100 Mbit), and which have an ISA bus. For two real projects, we now are discussing to integrate the MAC as an IP-core inside the FPGA, mainly for obsolecense reasons (e.g. MII being a industry standard, and ISA being virtually dead?). On a communication protocol level, we intend to use TCP/IP and/or UDP. Any experience or feedback is highly welcome, Best regards, JaapArticle: 55823
I woud like to make wirelles link with PPM, DPPM and DPIM modulators and demodulators. I use altera max++ . I woud appreciate any help.Article: 55824
Hello all. We are using Altera NIOS CPU with non-Altera PCI card with Altera FPGA (Gidel PROC20K board without flash memory). We are trying to use GERMS monitor, but it doesn't work - the "nios-run" script doesn't find a target (no responce from the GERMS). All the "hardware" was checked over and over - it's OK for sure. We looked at the GERMS source code, and it looks like it requires flash memory to exist and the program that GERMS receives is uploaded to flash, so this maybe the explanation why in our case (no flash on board) it doesn't work. The question is, can the GERMS monitor be somehow "reconfigured"? In other words, can we make it work somehow without flash, by uploading the program to the RAM on the FPGA itself? Has anybody tried something like this? Thanks in advance
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