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Found the right button. Can produce Postscript now. Thanx for helping -Manfred KrausArticle: 56676
On Tue, 10 Jun 2003 14:11:29 -0700, Hal Murray wrote: >>This 5V trouble is also true of PCI cards. There are still _many_ 5V PCI >>cards around. All you need is one 5V card in a backplane and your 3.3V >>limited FPGA card is in trouble... > > Does anybody make PCs with 3V PCI slots? Can I get a motherboard at > Fry's? > > Seems like a chicken/egg problem. All the PCI cards I've seen only have > the 5V slot cutout so they wouldn't fit into a 3V only system. So why > would anybody make a PC with 3V slots if there aren't any cards to go > into them? > > Best clean idea I know about is to use a PCI-PCI bridge chip and put > your FPGA on the isolated bus with nothing else on it. The bridge adds > other problems, obviously, but they might be worth it to use the new/big > FPGAs. > > Several years ago, I put a scope on a 5V PCI system. Nothing went over > 3V. We were considering cheating for a research project. Yes, I doubt there are many or even _any_ motherboards that have 5V drivers on the PCI bus, The problem is add-on cards.... PCWArticle: 56677
I can't find the website!? -- Posted via Mailgate.ORG Server - http://www.Mailgate.ORGArticle: 56678
Hi all, I tried without any settings (I create a new project and I only specified the target device and the libraries) and it didn't fit because it was not able to route all the nets. I checked all the global nets as Giuseppe Giachella suggested, but they are the same that I had in the MaxPlusII poject. I even tried to let QuartusII to do the synthesys but I did not obtain anything good. In my project I am using a PCI core by PLDA (master-slave v5.12), is it a clue for someone? Any other ideas? Regards, Andrea SabatiniArticle: 56679
On Tue, 10 Jun 2003 12:57:16 -0700, Peter Alfke <peter@xilinx.com> wrote: >As a hardware-oriented guy, I have been watching this thread in amazement. >The difference between calling something LSB or MSB, or bit number >whatever is just in your mind. The circuitry does not give a damn, it >just shifts the content of one latch or flip-flop into the neighbor that >it is connected to. Whether you call that left-shift or right-shift is >entirely up to you, ditto for the bit numbering. Unless if you're doing serial arithmetic, when you do want to process the LSB first, so you can add the "carry" from any bit to its next-highest neighbour. This would be an architectural limitation, but a limitation of the design, not of the underlying FPGA. - BrianArticle: 56680
On 10 Jun 2003 07:45:31 -0700, petersommerfeld@hotmail.com (Peter Sommerfeld) wrote: >Has anyone figured out (or tried to) the format of the bitstream used >to configure an FPGA. Obviously each vendor's, and maybe each part's, >bitstream format is different. >I'm asking because I wonder how difficult it would be to write one's >own synthesizer and router, if only to see if it can be done without >years of man-hours invested. If this is what you want to do, understanding the bitstream is actually redundant. Look into XDL, which has all the internal details of a design (placement, routing etc) in text format, with converters to/from the internal format used by Xilinx's placement and routing tools. (for synthesis, you don't need to go so far, just use EDIF) This way you could (in theory) replace parts of the Xilinx design flow - e.g. write your own placement tool which took the mapper's output (map.ncd, translated into XDL) - and maybe some other knowledge of the design, e.g. the VHDL source code - and placed logic elements according to the structure inferred from the design, thus eliminating the routing speed problems caused by "random placement". Translate the result back from XDL back into .ncd and run routing passes on it. Inspecting the XDL format of various stages of a design will give some idea of the complexity of the task ... note I'm not suggesting it's easy! - BrianArticle: 56681
On Tue, 10 Jun 2003 20:11:29 -0000, hmurray@suespammers.org (Hal Murray) wrote: >>This 5V trouble is also true of PCI cards. There are still _many_ 5V PCI cards >>around. All you need is one 5V card in a backplane and your 3.3V limited >>FPGA card is in trouble... > >Does anybody make PCs with 3V PCI slots? Can I get a motherboard >at Fry's? Tyan Trinity GCSL? http://www.tyan.com/products/html/trinitygcsl.html - BrianArticle: 56682
Nick Young wrote: > Hi, > > I want to get into FPGA's but havnt the first clue about how to go > about it. I would like to learn, hands on projects, about how to use > and program FPGA's. I have a very small budget so the less I can > spend the better. Can anyone suggest where to start Xilinx have masses of tutorials, application notes, data sheets etc on their website. I've recently started learning about them as well. Here's some things I'd do: Register here for the Xilinx University Programme: http://www.xilinx.com/univ/ and download tutorials from there and here http://www.xilinx.com/support/techsup/tutorials/index.htm. Download the Xilinx Webpack and Modelsim from here: http://www.xilinx.com/xlnx/xil_prodcat_landingpage.jsp?title=ISE+WebPack Find a good VHDL tutorial. I bought a book, but there'll be a few tutorials on the web. Download application notes from here: http://www.xilinx.com/apps/appsweb.htm Take a few years off and read everything. ;) -- Steve http://www.digitalradiotech.co.uk/ Subscribe for free to the Digital Radio Listeners' Group NewsletterArticle: 56683
Nothing would keep you from producing DVI signals out of a V2 other than the maximum channel frequency you can achieve. The range of 0 to about 200MHz is attainable. Beyond that I don't have enough experience to tell you. 200MHz would equate to a DVI link producing a 640x480 image at 60 frames per second with about 10% H and V blanking. Get up to 1024x768 and you need to output about 600MHz per channel. I don't think V2 can do that. I think that's where V2Pro comes into play. -- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ Martin Euredjian To send private email: 0_0_0_0_@pacbell.net where "0_0_0_0_" = "martineu" "Martin Thompson" <martin.j.thompson@trw.com> wrote in message news:ullw911gk.fsf@trw.com... > > Right, in summary, it looks like (as we had thought) V-II is not > capable of doing the PHY of DVI :-( > > Thanks all! > > Martin > > -- > martin.j.thompson@trw.com > TRW Conekt, Solihull, UK > http://www.trw.com/conektArticle: 56684
Hi, Problem Definition: FPGA 1 on board 1 will be driving its output through a Mictor connector (male) to board 2's Mictor connector (female) and then to FPGA 2 on board 2. Do FPGAs have the drive capability for such a connection OR will I need to find a way to buffer this ? How about APEX20K1500E specifically ? Thanks, PrashantArticle: 56685
So just build eight different-length LFSRs, all of which can fit into three or four Virtex-II CLBs (using SRL16s), and stop worrying about randomness. The parallel output IS random... Peter Alfke =========================== Rene Tschaggelar wrote: > > Allan Herriman wrote: > > > > Connecting the (Fibonacci) LFSR internal state to a DAC in parallel > > can be modeled as a 1 bit LFSR followed by an FIR filter. The FIR > > filter taps are just the DAC bit weights. > > > > If you are shifting LSB to MSB, the impulse response is: > > > > 1/128, 1/64, ... 1/2, 1. > > > > If you are shifting MSB to LSB, the impulse response is: > > > > 1, 1/2, ... 1/64, 1/128, which is the time reversal of the other > > impulse response (which means that the magnitude response is the same, > > but the phase has been reversed). > > > > This response is equivalent to a single pole low pass filter. (If > > that's what you actually wanted, it's much cheaper just to use a > > single bit output of the LFSR and an RC LP filter.) > > > > > > As the other posters said, this isn't the way to make a random voltage > > generator. What are you actually trying to achieve? > > Thanks for all replies this far. > > A random voltage generator. With a variable clock, such as the LT6900, > which can generate from 1kHz to 30MHz, and the property of the LFSR > to have a spectrum between the clock and the clock divided by the > number of bits, a system can be tested without a sweeper. > Since there appears not to be a paper about parallel output of a LFSR, > I'll run a PC simulation when time permits. > > Rene > -- > Ing.Buero R.Tschaggelar - http://www.ibrtses.com > & commercial newsgroups - http://www.talkto.netArticle: 56686
Prashant, This is what IBIS and spice simulators are used for. One can open a case with the hotline to do a "what if" signal integrity case. We need the connector spice models (or equivalent models for IBIS), and the intended load, pcb trace geometries, connecting cable parameters (if any), etc. etc. etc. Austin Prashant wrote: > Hi, > > Problem Definition: > FPGA 1 on board 1 will be driving its output through a Mictor > connector (male) to board 2's Mictor connector (female) and then to > FPGA 2 on board 2. > > Do FPGAs have the drive capability for such a connection OR will I > need to find a way to buffer this ? How about APEX20K1500E > specifically ? > > Thanks, > PrashantArticle: 56687
I do not understand the subtleties of DVI, but I understand the multi-gigabit serializer in VirtexIIPro. Ignoring and bypassing the 8B10B encoder, each MGT output will act as a parallel-to serial converter, converting 20 bits parallel into 1-bit serial. All you need to supply is a reference clock that is 20 times slower than the outgoing bitstream. The lower limit for the reference clock frequency is 50 MHz, which generates a 1 gigabit/sec output stream. If you want to have a lower output rate, "stutter" the bits, i.e. duplicate adjacent bits on the parallel side. That way, you can achieve any output bit rate you want, from dc to 3 Gbps. And driven from an internally terminated differential driver with programmable output swing and programmable preemphasis. Neat stuff, all self-contained. Peter Alfke, Xilinx Applications ===================== Martin Euredjian wrote: > > Nothing would keep you from producing DVI signals out of a V2 other than the > maximum channel frequency you can achieve. The range of 0 to about 200MHz > is attainable. Beyond that I don't have enough experience to tell you. > 200MHz would equate to a DVI link producing a 640x480 image at 60 frames per > second with about 10% H and V blanking. Get up to 1024x768 and you need to > output about 600MHz per channel. I don't think V2 can do that. I think > that's where V2Pro comes into play. > > -- > ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ > Martin Euredjian > > To send private email: > 0_0_0_0_@pacbell.net > where > "0_0_0_0_" = "martineu" > > "Martin Thompson" <martin.j.thompson@trw.com> wrote in message > news:ullw911gk.fsf@trw.com... > > > > Right, in summary, it looks like (as we had thought) V-II is not > > capable of doing the PHY of DVI :-( > > > > Thanks all! > > > > Martin > > > > -- > > martin.j.thompson@trw.com > > TRW Conekt, Solihull, UK > > http://www.trw.com/conektArticle: 56688
In a CMOS to CMOS world, any output can drive any (number of) input(s), since the input load current is effectively zero, and the output impedance in the strongest flavor is < 10 Ohms. It's never a question of static drive, it's a question of edge rates, reflections, terminations, signal integrity etc. Peter Alfke, Xilinx Applications ========================== Prashant wrote: > > Hi, > > Problem Definition: > FPGA 1 on board 1 will be driving its output through a Mictor > connector (male) to board 2's Mictor connector (female) and then to > FPGA 2 on board 2. > > Do FPGAs have the drive capability for such a connection OR will I > need to find a way to buffer this ? How about APEX20K1500E > specifically ? > > Thanks, > PrashantArticle: 56689
Andrea Sabatini wrote: > In my project I am using a PCI core by PLDA (master-slave v5.12), is it a > clue for someone? Is Synplify giving you any warnings? Check the core source code for tool dependent attributes. If you don't have source, check with PLDA for their Synplify flow. -- Mike TreselerArticle: 56690
Brian - If you came up with a pill that cured cancer, someone in this group would complain that you didn't make it cherry-flavored. Bob Perlman Cambrian Design Works On Tue, 10 Jun 2003 23:40:34 GMT, Brian Dipert <bdipert@NOSPAM.pacbell.net> wrote: >> Hmmm, I'd rate it OK, but a little thin on the CPLD end of the scale, >>and >>suspect it did not take a lot of time. > >Yeah, if I just didn't require those blasted two minimum hours of >sleep every night.....or if the scientists would just quit fooling >arond and perfect human cloning.... > >...biting his tongue... > >NOTE NEW ADDRESS AND FAX NUMBER >Brian Dipert >Technical Editor: Mass Storage, Memory, Multimedia, PC Core Logic and Peripherals, and Programmable Logic >EDN Magazine: http://www.edn.com >Contributing Editor, CommVerge Magazine: http://www.commvergemag.com >5000 V Street >Sacramento, CA 95817 >(916) 454-5242 (voice), (617) 558-4470 (fax) >***REMOVE 'NOSPAM.' FROM EMAIL ADDRESS TO REPLY*** >mailto:bdipert@NOSPAM.edn.com >Visit me at http://www.bdipert.comArticle: 56691
Hi Martin, I have personally never done this, but I think it might be possible. Basically you need the following functionality: | TMDS Encoder (8b:10b lookup-table)|--->|10 bit->1bit serializer|--->|LVDS transmitter| I think the lvds transmitter and the serializer are available in v2, the tmds encoding can be implemented in the programmable logic, using the lookup table described in the DVI standard. As I have not tried it, I am not sure this would work, but I think it quite possibly would. Note that if you are trying to implement HDMI instead of DVI, you would need to add the capability for TERC4 coding into your design. Ljubisa Bajic ATI Technologies ---- My opinion does not represent that of my employer ---- Martin Thompson <martin.j.thompson@trw.com> wrote in message news:<u4r2youcy.fsf@trw.com>... > Hi all, > > Has anyone out there successfully implemented a DVI (Digital Video > Interface) in a Virtex-II (or any other FPGA for that matter)? The > tricky bit seems to be the physical layer which is > sort-of-differential-but-not-really (it's called TMDS - transition > minimised digital signalling). I'm sure there's a nifty way of doing > it though... > > Thanks in advance! > MartinArticle: 56692
Part of my next toybox, for sure! :-) -Martin "Peter Alfke" <peter@xilinx.com> wrote in message news:3EE76542.A3827501@xilinx.com... > I do not understand the subtleties of DVI, but I understand the > multi-gigabit serializer in VirtexIIPro. > Ignoring and bypassing the 8B10B encoder, each MGT output will act as a > parallel-to serial converter, converting 20 bits parallel into 1-bit > serial. All you need to supply is a reference clock that is 20 times > slower than the outgoing bitstream. > The lower limit for the reference clock frequency is 50 MHz, which > generates a 1 gigabit/sec output stream. If you want to have a lower > output rate, "stutter" the bits, i.e. duplicate adjacent bits on the > parallel side. That way, you can achieve any output bit rate you want, > from dc to 3 Gbps. > And driven from an internally terminated differential driver with > programmable output swing and programmable preemphasis. Neat stuff, all self-contained. > > Peter Alfke, Xilinx Applications > ===================== > Martin Euredjian wrote: > > > > Nothing would keep you from producing DVI signals out of a V2 other than the > > maximum channel frequency you can achieve. The range of 0 to about 200MHz > > is attainable. Beyond that I don't have enough experience to tell you. > > 200MHz would equate to a DVI link producing a 640x480 image at 60 frames per > > second with about 10% H and V blanking. Get up to 1024x768 and you need to > > output about 600MHz per channel. I don't think V2 can do that. I think > > that's where V2Pro comes into play. > > > > -- > > ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ > > Martin Euredjian > > > > To send private email: > > 0_0_0_0_@pacbell.net > > where > > "0_0_0_0_" = "martineu" > > > > "Martin Thompson" <martin.j.thompson@trw.com> wrote in message > > news:ullw911gk.fsf@trw.com... > > > > > > Right, in summary, it looks like (as we had thought) V-II is not > > > capable of doing the PHY of DVI :-( > > > > > > Thanks all! > > > > > > Martin > > > > > > -- > > > martin.j.thompson@trw.com > > > TRW Conekt, Solihull, UK > > > http://www.trw.com/conektArticle: 56693
The parallel-data-in to serial-10bit-coded-data-out and LVDS is, shall we say, trivial. The issue is output bitstream clock rate. If you need DVI beyond the lowest resolutions you just can't do it on V2 because you are in GHz territory or very close to. I'm not sure how fast you an get a V2 LVDS output to go (I only have about a year and a half worth of experience with FPGA's and the fastest I've gone is 165MHz) but I know it ain't in the GHz region. Maybe 200 to 300MHz, max? The datasheet shows samples of (simple) internal functions running upwards of 400MHz. Peter? -- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ Martin Euredjian To send private email: 0_0_0_0_@pacbell.net where "0_0_0_0_" = "martineu" "Ljubisa Bajic" <eternal_nan@yahoo.com> wrote in message news:9b0afb2c.0306111045.344cd548@posting.google.com... > Hi Martin, > > I have personally never done this, but I think it might be possible. > Basically you need the following functionality: > > | TMDS Encoder (8b:10b lookup-table)|--->|10 bit->1bit > serializer|--->|LVDS transmitter| > > I think the lvds transmitter and the serializer are available in v2, > the > tmds encoding can be implemented in the programmable logic, using the > lookup > table described in the DVI standard. > > As I have not tried it, I am not sure this would work, but I think it > quite possibly would. > Note that if you are trying to implement HDMI instead of DVI, you > would need > to add the capability for TERC4 coding into your design. > > Ljubisa Bajic > ATI Technologies > ---- My opinion does not represent that of my employer ---- > Martin Thompson <martin.j.thompson@trw.com> wrote in message news:<u4r2youcy.fsf@trw.com>... > > Hi all, > > > > Has anyone out there successfully implemented a DVI (Digital Video > > Interface) in a Virtex-II (or any other FPGA for that matter)? The > > tricky bit seems to be the physical layer which is > > sort-of-differential-but-not-really (it's called TMDS - transition > > minimised digital signalling). I'm sure there's a nifty way of doing > > it though... > > > > Thanks in advance! > > MartinArticle: 56694
Hello Bram, I have seen some evaluation boards on the Xilinx website with VirtexII PRO and DDR memory. About the LVDS link, do you need a physical connection of a specific minimum length (for instance including cable?), or is a "loopback" from transmitter to receiver (RX) also sufficient for the evaluation you want to do? Using a "loopback" will of course prevent you from having to buy 2 evaluation boards, just to see if you can get the LVDS link running.... For instance, have a look at the Virtex-II XC2V4000 XP Development Kit, it has got both LVDS and DDR. I guess you already consulted Kees van Egmond at Avnet/Silica? Best regards, Jaap P.S. Please do my greetings to Stefan van Beek, you probably know him.. "Bram van de Kerkhof" <bvdknospam@oce.nl> wrote in message news:1054561920.762580@news-ext.oce.nl... > Hello, > > I'm looking for an evaluation board of the Virtex 2 (actually for the > Spartan 3 but as there are none available i will have to verify on the > Virtex 2) > I want to verify a ddr-sdram and 300 Mb's lvds link design. Two avaluation > boards is also ok (one for ddr and one for lvds). > > Who has some idea's ? > > Yours Bram > > -- > ================================================== > Bram van de Kerkhof > > OCE-Technologies BV > Building 3N38 > > St. Urbanusweg 43, > Venlo, The Netherlands > P.O. Box 101, 5900 MA Venlo > ================================================== > Direct dial : +31-77-359 2148 > Fax : +31-77-359 5473 > ================================================== > e-mail : mailto:bvdk@oce.nl > ================================================== > www : http://www.oce.nl/ > ================================================== > >Article: 56695
"Cooley" <305liuzg@163.net> wrote in message news:baqqri$1ql4$1@mail.cn99.com... > I want to implement uclinux in Nios. > > Is there any free uclinux version for nios. > > Would anyone help me? > > Thanks and Regards. > > > > If you have plenty of time to spend writing and debugging linux device drivers, etc., continue looking or waiting for a free uclinux distri for nios. If this is not the case however, look at http://www.microtronix.com. We have evaluated this recently, and plan to use in a recently starting design (Nios in Stratix EP1S80). Best regards, JaapArticle: 56696
On Wed, 11 Jun 2003 10:20:10 -0400, Niko Zhang wrote: > I can't find the website!? It's at, http://www.polybus.com/hdlmaker/users_guide/Article: 56697
Peter Alfke <peter@xilinx.com> writes: > I do not understand the subtleties of DVI, but I understand the > multi-gigabit serializer in VirtexIIPro. > Ignoring and bypassing the 8B10B encoder, each MGT output will act as a > parallel-to serial converter, converting 20 bits parallel into 1-bit > serial. All you need to supply is a reference clock that is 20 times > slower than the outgoing bitstream. > The lower limit for the reference clock frequency is 50 MHz, which > generates a 1 gigabit/sec output stream. If you want to have a lower > output rate, "stutter" the bits, i.e. duplicate adjacent bits on the > parallel side. That way, you can achieve any output bit rate you want, > from dc to 3 Gbps. I should probably read the data sheet, but... Is there also a serial-to-parallel converter which works at this clock-rate? And is this also in the spartan III? ThomasArticle: 56698
Hi Jean Philippe, I am not familiar with XST (yet), but it probably optimizes to "area" default, unless you have set specific timing- or other synthesis constraints. Optimizing to area will probably reduce the number of slices of LUTS, by using the embedded multiplier for your constant multiplication. Read the manual (if any?) and check out possible synthesis constraints. If nothing seems to help but you are still desperate to solve issue, take a deep breath and either: - in case you want to keep using XST: change your VHDL coding style in such a way that you get want you want (yuk!) - in all other cases: pull out your wallet and buy yourselve a (good) third party synthesis tool What is this INT16 type? Is this similar to SIGNED(15 DOWNTO 0), conform the IEEE numeric_std package, or has Xilinx "reinvented the wheel" by defining its own datatypes again, similar like we had in the early '90s? By the way, I believe the 16-bit register can also be removed by enabling a pipeline register inside the embedded multiplier block. Finally, you may also want to use the Xilinx Coregen tool, and generate a constant multipliers using LUTS for you, and instantiate this as a blackbox in you VHDL design. Enough possibilities to choose from, but perhaps that is exactly the problem??? ;-) Best regards, Jaap "delahaye" <jean-philippe.delahaye@iuplo.univ-ubs.fr> wrote in message news:290d1261.0305230656.5faa6b8a@posting.google.com... > Hi everybody, > Please help, > > I design the behvioral below wich contains a simple multiplication > between a signal and a constant; > > My behavioral is : > entity mult is > Port (a : in INT16; clk : std_logic; s : out INT16 ); > end mult; > > > architecture Behavioral of mult is > constant alpha INT16 := 123; > begin > mul: process(clk) > begin > if clk'event AND clk='1' then > s<=a*alpha; > end if; > end process mul; > end Behavioral; > > I use xilinx ISE 5.2 with XST to synthesis it and Modelsim to simulate > it. > The behavioral simulation is good, but the post-map simulation is > totally wrong. > A part of my HDL Synthesis Report is:: > Macro Statistics > # Registers : 1 > 16-bit register : 1 > # Multipliers : 1 > 16x8-bit multiplier : 1 > > > I think that after the synthesis my positive constant 123=(1111011)b > is sign extended on 16 bits to use 16*16 bits multiplier and the > value 1 is extended on MSB rather than 0. > > Note that I want to use lut or block multiplier of the Virtex. I give > this simple design to light up the synthesis problem of constant > mapping on signed multiplier. > > WHAT KIND OF SOLUTION IN VHDL EXIST TO REALLY FIX THE BIT WIDTH OF A > CONSTANT TO AVOID THE PROBLEM OF SIGN EXTENTION?? > > I wich I expose my problem clearly > Regards, > > Jean Philippe,Article: 56699
I have a question for all you Modelsim experts out there. I want to set up a test bench which ultimately will use a long test vector (something on the order of tens of millions samples long.) The way that I've always done this in the past is to generate and store the vector in a text file, and then read them in in a VHDL testbench, one line at a time. A second option is that the test vector can be stored as a constant vector table in VHDL, which would get compiled--the idea being that this would cut out the overhead associated with file accesses. However, I think that this way wouldn't work for the long test vectors I'm thinking of.... I also read that I can use a tcl testbench that provides the stimulus. This I have absolutely no experience in. What is the relative advantage/disadvantage of using a tcl vs. VHDL, if I'm sure that I will be using Modelsim forever? Any other advice about how to best manage the test vectors? Thanks!
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