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OK, here's the difinitive answer, I hope. Upgrade to 7.2.2, and it does compile without an error, but still divides the clock by the default of 2. To solve this add: attribute xc_props : string; attribute xc_props of U_DCM : label is "CLKDV_DIVIDE=16"; below the other attributes. Then it should work fine. I presume this may well be the case for the other attributes as well. Ken McElvain <ken@synplicity.com> wrote in message news:<3EEB5BFF.7080405@synplicity.com>... > As long as you are upgrading I suggest that you go to 7.3 . > You should also be able to use generics directly instead of > generics and attributes. > > Suhaib Fahmy wrote: > > > Okay, think I worked it out. it seems that Synplify 7.1 doesn't support > > real attributes. Is there a workaround? Or must I use v.7.22 to be able > > to compile this? > > > > Thanks. > > > > > > On Sat, 14 Jun 2003, Suhaib Fahmy wrote: > > > > > >>Hi, > >> > >>I have instantiated two Virtex II DCMs using the language templates in > >>ISE4.1. When I try to compile the design, Synplify complains about not > >>being able to map the type "Real", and quits. So I put a pair of > >>--synopsis translate_off/on terms around the attribute declaration and > >>it compiles fine, but I note in the report that it has used a divisor of > >>2, not 16 as I requested, but that's to be expected. > >> > >>If I use modelsim to simulate the original VHDL code, it works > >>correctly, dividing by 16. But the post-map and post-p&r models divide > >>by two. > >> > >>What am I doing wrong? Why does Synplify not understand the attributes? > >> > >>Thanks. > >> > >>Article: 56851
Perhaps:
always @(posedge CLK or posedge RST)
if(RST) mst <= 0;
else if(crrst) mst <= 0;
else if(en1) mst <= 1;
A side note - many people don't like to see code without begin/end
constructs even though they aren't always necessary. A begin/end block is
used to substitute several commands where one command would normally be
used. If there's only one command in a block, the begin/end is superfluous.
Another possibility would be:
always @(posedge CLK or posedge RST)
if(RST) mst <= 0;
else mst <= ~crrst & (en1 | mst);
"nospam" <nospam@nospam.invalid> wrote in message
news:581uev026jm0r96pt2duth2pdbv7jbalk7@4ax.com...
> Given this construct
>
> always @(posedge CLK or posedge RST) begin
> if(RST || crrst) begin
> mst <= 0;
> end else if(en1) begin
> mst <= 1;
> end
> end
>
> the current XST barfs about not matching "known FF".
> XST is happy with this equivalent construct
>
> always @(posedge CLK or posedge RST) begin
> if(RST) begin
> mst <= 0;
> end else if(en1 || crrst) begin
> mst <= !crrst;
> end
> end
>
>
> Is this the least ugly alternative?
>
>
Article: 56852
Mark Sandford wrote:
> The app note details all of this on with good file format suggestions
> on pages 8-9 (reading the manual ussually helps).
> http://www.xilinx.com/xapp/xapp098.pdf
That document says:
Because of the difficulty in identifying and removing the title
declaration, the binary (.bit) file created by BitGen is not
recommended for use. Instead, one should use BitGen to
create a hex file, which, in turn, is converted to binary as
described in the preceding section.
I humbly disagree, and have successfully used bit files for my work,
using the documentation posted by Alan Nishioka <alann@accom.com>
in this group (comp.arch.fpga) on 29 Aug 2001. Google for
"Larry Doolittle JTAG" and you can find my source code.
The bitfile processor is buried in virtex.c.
- Larry
Article: 56853In article <YbtHa.3279$ca4.296525@news20.bellglobal.com>, Jason Berringer <jberringer@trace-logic.com.delete> wrote: > >I was wondering if anyone has ever attempted a phase lock loop in digital >before (specifically VHDL). I'm looking for some examples or pointers on For an all-software example look at NTP (network time protocol). Looks like you can start at ntp.org. I know there is also at least one open source GPS firmware out there (no idea what the name is, try sourceforge) which may implement a PLL in software. -- Ben Jackson <ben@ben.com> http://www.ben.com/Article: 56854
Gilad Cohen wrote:
> Every time I ran an exceptionally long VHDL simulation, my computer
> crashed.
> I'm using quite a strong server, so I don't think the problem is in
> the computer.
> I'm assuming that the long VHDL simulation simply "ate up" all of my
> system's memory.
Unless your testbench is using pointers or access types,
it can not "eat up" memory.
> The only solution I can see, is to implement the input generation and
> output examination in software, and call the VHDL simulator on each
> test at a time.
>
> Does anyone know a better solution to the long VHDL simulation
> problem?
Consider trying the testbench on a different computer
and/or a different simulator.
-- Mike Treseler
Article: 56855sri_valli_design@hotmail.com (Valli) wrote in message news:<d9acfecb.0306162148.4f985d64@posting.google.com>... > > I want to implement Mux-DFF only.(without using the LUT resources..) It probably doeesn't help you in this case, but if one of the inputs to the mux is a constant, I've seen the synthesis tools automagicly use the reset input of the flop to implement a simple mux without a LUT. This assumes, of course, you don't have a async reset on the flop. Although it's a bit of a stretch, *IF* there are certain relationships between the two mux'ed inputs, it seems like creative use of the clock enable and/or reset may produce a mux-like structure, but it would be very dependant on the data patterns of the two signals. Multiple DFF's may also be needed. Or it may just not be possible. Can you not use the TBUF lines for your mux? MarcArticle: 56856
Hello. Can anyone recommend a simple Forward Error Correction algorithm to implement in a Xilinx Virtex? I'm not talking about buying a Reed Solomon (or equivalent) core from Xilinx. I need something much simpler. Thanks, Gilad.Article: 56857
On Tue, 17 Jun 2003 15:42:24 +0000 (UTC), Larry Doolittle <ldoolitt@recycle.lbl.gov> wrote: >Mark Sandford wrote: >> The app note details all of this on with good file format suggestions >> on pages 8-9 (reading the manual ussually helps). >> http://www.xilinx.com/xapp/xapp098.pdf > >That document says: > Because of the difficulty in identifying and removing the title > declaration, the binary (.bit) file created by BitGen is not > recommended for use. Instead, one should use BitGen to > create a hex file, which, in turn, is converted to binary as > described in the preceding section. > >I humbly disagree, and have successfully used bit files for my work, >using the documentation posted by Alan Nishioka <alann@accom.com> >in this group (comp.arch.fpga) on 29 Aug 2001. You can find this at: http://www.fpga-faq.com/FAQ_Pages/0026_Tell_me_about_bit_files.htm >Google for >"Larry Doolittle JTAG" and you can find my source code. >The bitfile processor is buried in virtex.c. > > - Larry Philip Freidin FliptronicsArticle: 56858
My SDRAM controller has ports used to set CAS Latency (CASL) and Burst
Length (BL). These ports will be driven by a register interface to an
external microprocessor. The interface module is not written yet.
If I simply hard-wire the CASL and BL ports
...
.CAS (2'd3),
.BL (8'd32),
...
for a test, XST will very joyfully remove all sorts of logic I do not wish
it to remove. This seems to cause a chain reaction whereby I loose logic
that is actually needed.
My workaround at the moment was to define a dummy module with a super-slow
counter. Since the counter is gated by one of my reset lines, it really
never counts very far. I then use the MSB of the counter within and if/else
block to assign values to outgoing CASL and BL ports. XST is happy with
this because it thinks that this counter could change values (even though it
never will).
I'm sure there's a more elegant way around this? Can someone tell me how?
Thanks,
--
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Martin Euredjian
To send private email:
0_0_0_0_@pacbell.net
where
"0_0_0_0_" = "martineu"
Article: 56859Steve Lass wrote: > The 3S50, 3S200 and 3S400 will be included in the 6.1i WebPACK (coming > this Fall). > > John wrote: > >> Hello, >> Does anyone know when Spartan3 devices other than the 50K will be >> supported by ISE WebPack. Also, does anybody know what the largest >> Spartan3 supported by the WebPack tools will be? >> >> Thanks >> >> > Nice feedback ------------ And now a word from our sponsor ------------------ Do your users want the best web-email gateway? Don't let your customers drift off to free webmail services install your own web gateway! -- See http://netwinsite.com/sponsor/sponsor_webmail.htm ----Article: 56860
"Martin Euredjian" <0_0_0_0_@pacbell.net> wrote in message news:scJHa.68$z73.5025817@newssvr15.news.prodigy.com... > My SDRAM controller has ports used to set CAS Latency (CASL) and Burst > Length (BL). These ports will be driven by a register interface to an > external microprocessor. The interface module is not written yet. > > If I simply hard-wire the CASL and BL ports > > ... > .CAS (2'd3), > .BL (8'd32), > ... > > for a test, XST will very joyfully remove all sorts of logic I do not wish > it to remove. This seems to cause a chain reaction whereby I loose logic > that is actually needed. > > My workaround at the moment was to define a dummy module with a super-slow > counter. Since the counter is gated by one of my reset lines, it really > never counts very far. I then use the MSB of the counter within and if/else > block to assign values to outgoing CASL and BL ports. XST is happy with > this because it thinks that this counter could change values (even though it > never will). > > I'm sure there's a more elegant way around this? Can someone tell me how? How about just gating CASL and BL with the reset signal? (or negated reset) Otherwise, it seems usual to latch data like this at reset off lines that are otherwise only after reset. -- glenArticle: 56861
gilad_coh@walla.co.il (Gilad Cohen) writes: > Can anyone recommend a simple Forward Error Correction algorithm to > implement in a Xilinx Virtex? > I'm not talking about buying a Reed Solomon (or equivalent) core from > Xilinx. I need something much simpler. Hamming codes?Article: 56862
for about 25 years, I've been using a fairly simple all-digital PLL design that will synchronize in quadrature with a reference occurring at 1/16 the clock rate. I've adapted this design to operate at 1/32 and as low as 1/8 the center frequency, and have found that it works remarkably well, provided you can tolerate the occasional phase noise at 1/16 the center frequency that occurs when the stepwise correction in phase is made. The phase noise is directly proportional to the ratio of the center frequency to oscillator frequency, the latter being a precise harmonic of the center frequency. Acquisition time is typically three cycles. Email me if you're interested, and I'll send you a schematic in XILINX's ECS format. It uses simple components, hence can easily be translated into whatever you need. Note that it requires asynchronous clear if you use it as-is, which is the form in which I swiped it 25 years ago, though it is quite straightforward to adapt it to synchronous form, which I've done in order to conserve registers for purposes of implementing it in SPLD's. regards, Richard Erlacher Principal Engineer id Communications (303) 790-4343 "Jason Berringer" <jberringer@trace-logic.com.delete> wrote in message news:YbtHa.3279$ca4.296525@news20.bellglobal.com... > Hello guru's > > I was wondering if anyone has ever attempted a phase lock loop in digital > before (specifically VHDL). I'm looking for some examples or pointers on > trying to build one for a low frequency range of 200 Hz to 200 kHz. I would > appreciate any comments or suggestions. Google didn't get me very far, so if > you know of any app notes, etc. please let me know. > > Thanks, > > Jason > >Article: 56863
Hello, I have seen some FPGA implementations of old 80's arcade games like pacman Could a Board like the (B5-X300 FPGA) Board http://www.burched.biz/b5x300.html To create a graphics processor (GPU Only) for a homebrew console on par with like a 16 Bit SuperNintendo (SNES) or some of the lower cost boards even more capable then this. Or is this just wishful thinking? Thanks, M. BazaillionArticle: 56864
I forgot to add "With exteral Ram for the Video."Article: 56865
Hi,
I am a student working on my final year thesis. I'm looking into ways
of compressing Virtex bitstream by partial reconfiguration. In the
process, I have to generate my own bitstreams to be loaded onto the
FPGA. Much as I have tried following the algorithm provided in
XAPP151, I am stuck at the part where CRC checks are performed, not
being able to produce code that precalculate the correct CRC value to
be written onto the CRC register for internal checks. In the partial
configuration bitstream, 2 CRC checks are performed, one prior to
loading the last frame and one after. My code correctly produces the
CRC value for the second check, but not for the first, where there is
a constant CRC error value for all bitstreams I have tested with. What
could be a possible reason for this? I've have
tried many ways of tackling it to no avail.Please help!!!
Article: 56866Thanks to all that have responded and given me a great place to start. Jason "Jason Berringer" <jberringer@trace-logic.com.delete> wrote in message news:YbtHa.3279$ca4.296525@news20.bellglobal.com... > Hello guru's > > I was wondering if anyone has ever attempted a phase lock loop in digital > before (specifically VHDL). I'm looking for some examples or pointers on > trying to build one for a low frequency range of 200 Hz to 200 kHz. I would > appreciate any comments or suggestions. Google didn't get me very far, so if > you know of any app notes, etc. please let me know. > > Thanks, > > Jason > >Article: 56867
Hi, I have been unable to find a data sheet for the XCV6000 device. Have I got the number wrong ? Does such a device exist ? If so, where can I find a data sheet for this device. Thanks, PrashantArticle: 56868
Maybe XC2V6000? "Prashant" <prashantj@usa.net> 写入消息新闻 :ea62e09.0306171712.6665c9e7@posting.google.com... > Hi, > > I have been unable to find a data sheet for the XCV6000 device. Have I > got the number wrong ? Does such a device exist ? If so, where can I > find a data sheet for this device. > > Thanks, > PrashantArticle: 56869
Hi,
I am a student working on my final year thesis. I'm looking into ways
of compressing Virtex bitstream by partial reconfiguration. In the
process, I have to generate my own bitstreams to be loaded onto the
FPGA. Much as I have tried following the algorithm provided in
XAPP151, I am stuck at the part where CRC checks are performed, not
being able to produce code that precalculate the correct CRC value to
be written onto the CRC register for internal checks. In the partial
configuration bitstream, 2 CRC checks are performed, one prior to
loading the last frame and one after. My code correctly produces the
CRC value for the second check, but not for the first, where there is
a constant CRC error value for all bitstreams I have tested with. What
could be a possible reason for this? I've have
tried many ways of tackling it to no avail.Please help!!! Thank you so
much!
Article: 56870Can we actually do that, and how? Will a larger time be incurred in configuring with rbt, since each bit is represented by 1 byte in ascii? Can we convert *.rbt back to *.bit? Thanks!Article: 56871
RS codes over a smaller field could be implemented fairly easily. The
code itself isn't all that complicated, so the decoding that you care
to implement could be complicated (soft decoding via Sudan's
algorithm?) or simpler. If you built an RS code over a very small
field (F_{16}), the decoder could even be exhaustive and therefore
better than the minimum distance ones.
Hamming codes can be done with just a couple LUTs.
Convolutional codes have an enormous amount of flexibility in the
decoder. Short, psuedo-Viterbi algorithms can be implemented quite
easily.
What's the application? If it is a learning lab, I'd start with
Hamming codes. You could then move to a more complicated matrix-based
decoder. Algebraic decoding is pretty simple in logic, but requires a
bit more of a leap between the hardware understanding and theoretical
understanding. Many folks can follow one or the other, but not nearly
as many can join the two.
Jake
gilad_coh@walla.co.il (Gilad Cohen) wrote in message news:<8f9a8978.0306170907.f75d345@posting.google.com>...
> Hello.
> Can anyone recommend a simple Forward Error Correction algorithm to
> implement in a Xilinx Virtex?
> I'm not talking about buying a Reed Solomon (or equivalent) core from
> Xilinx. I need something much simpler.
>
> Thanks,
> Gilad.
Article: 56872On Tue, 17 Jun 2003 18:12:38 -0700, Prashant wrote: > Hi, > > I have been unable to find a data sheet for the XCV6000 device. Have I got > the number wrong ? Does such a device exist ? If so, where can I find a > data sheet for this device. > > Thanks, > Prashant You want the Virtex2 datasheet. The device is the XC2V6000Article: 56873
I think a BCH code is somewhat simpler to implement than an RS code. You wouldn't have the burst protection inherent in RS. A small Hamming code, like a (7,3) code, could be done with just a small lookup table, but would give you little protection, especially from burst errors. Something with small codewords you could implement entirely in a single blockRAM. Maybe a combination of a Hamming code and an interleaver would be a good compromise. Knowlege of your BER and the nature of the errors is very important. -Kevin "Gilad Cohen" <gilad_coh@walla.co.il> wrote in message news:8f9a8978.0306170907.f75d345@posting.google.com... > Hello. > Can anyone recommend a simple Forward Error Correction algorithm to > implement in a Xilinx Virtex? > I'm not talking about buying a Reed Solomon (or equivalent) core from > Xilinx. I need something much simpler. > > Thanks, > Gilad.Article: 56874
Martin Euredjian wrote: > > My SDRAM controller has ports used to set CAS Latency (CASL) and Burst > Length (BL). These ports will be driven by a register interface to an > external microprocessor. The interface module is not written yet. > > If I simply hard-wire the CASL and BL ports > > ... > .CAS (2'd3), > .BL (8'd32), > ... > > for a test, XST will very joyfully remove all sorts of logic I do not wish > it to remove. This seems to cause a chain reaction whereby I loose logic > that is actually needed. > > My workaround at the moment was to define a dummy module with a super-slow > counter. Since the counter is gated by one of my reset lines, it really > never counts very far. I then use the MSB of the counter within and if/else > block to assign values to outgoing CASL and BL ports. XST is happy with > this because it thinks that this counter could change values (even though it > never will). > > I'm sure there's a more elegant way around this? Can someone tell me how? There are all sorts of ways to work around this. It only requires that you use one external pin as an input. But the optimizer should not be removing any logic that will change your outputs given that your "unimplemented" circuit is fixed. With a fixed input, the optimizer will allow that to propogate through and remove any logic that is then disabled. No other logic should be removed. For example, an AND gate with one of the inputs wired to a zero will be removed and the zero propagated to the output since no matter what value is on the other inputs the output will not change. I understand that in your case the input will be replaced with a register and so you want that logic to remain. But the tool sees the gates as unneeded logic. I would recommend that you use a "dummy" module that uses a single input pin to the D input of as many FFs as you need to generate the outputs from that module. I suppose the optimizer may see them as equivalent and change them to a single FF, so you might want to use a "keep" directive on the FF output nets. The dummy module can serve as a placeholder until you make the real one. We always start projects by defining all the modules from the top down. We start with just the IOs so that the structure is there and dummy up the modules that we have not implemented. I hope this is useful. But then you may already know this and be looking for something simple like a switch. I belive there is one, but it likely works at a global level. -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAX
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