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"Jesse Kempa" <kempaj@yahoo.com> wrote > The device Mr(s). Panic refers to [...] Hehe. I might be a bit on the feminine side, but I'm not a full blown woman. Yet anyway :-P > Anyways, even though I work here [...] Hmmm. You wouldn't happen to know of some documents that would answer my question (OP)? Working "over there" and all...? -PanicArticle: 62076
Use FPGA Editor to look at the diagram of a single slice. You'll see what
logic and interconnection possibilities you have within the confines of a
slice. In fact, you can even switch to editing mode and make connections
manually. See if you can figure out how to pack your logic in there this
way.
--
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Martin Euredjian
To send private email:
0_0_0_0_@pacbell.net
where
"0_0_0_0_" = "martineu"
"ric" <ric_ma@attansic.com.tw> wrote in message
news:e56276c6.0310170151.da838dd@posting.google.com...
> Hi,guys!
> I have maybe a silly question,but it confused me all the day,the
> question is:
> I have a function with 5-inputs and one output,and thus XST maps to
> 2 LUTs in the Xilinx FPGA,but I think its a bit too wasteful--there is
> about 5000 such functions in my design.So I want to use a 4-input LUT
> and a D-LATCH with async clear instead(one of the 5-inputs is used to
> clear the output).But,the question is,I do use the LUT and latch in
> the same slice,but the other LUT in the same slice can not be used by
> other logic!
> Why my method could not work?Is there any resource conflict?
> Appreciate for your help!Thanks!
>
> ps.
> My verilog code is like this:
> always @ (zero_flag or a or b )
> if (zero_flag)
> o_tmp_data <= 14'h0 ;
> else if (b[1:0] == 2'b00)
> o_tmp_data <= a[13:0] ;
> else if (b[1:0] == 2'b01)
> o_tmp_data <= {a[12:0],1'b0} ;
> else if (b[1:0] == 2'b11)
> o_tmp_data <= ~a[13:0] ;
> else
> o_tmp_data <= {~a[12:0],1'b1} ;
> or I use two blocks and the other block is exactly like what Xilinx
> suggests in its template,but the XST could not recognize it as a LUT
> and a latch,and still 2 LUTs.I wonder if I miss something?
Article: 62077I've had similar problems. A few here have mentioned the problem you have. I have a problem with timing not being met (was met on 5.2i) even though I have several timing constraints and placement constraints that should help. I'd agree with your final statement, but it really isn't a 'nice GUI'. It's more like a slopped-together GUI to get the task done, but pays little attention to the technical details that FPGA engineers desire or the good GUI design that can provide such nice results. As GUIs go, it's most comparable to the crap that Matlab added to their 6.0 stuff. And don't even get me started on ECS. I've seen schematic capture programs done as an assembly-language programming course final project that are better than that. JakeArticle: 62078
On Thu, 16 Oct 2003 10:03:02 -0700, John Larkin <jjlarkin@highSNIPlandTHIStechPLEASEnology.com> wrote: >OK, a simple system: a Motorola MC68332 uP is trying to configure a >Spartan2 chip, an XC2S15-VQ100. We've done this sort of thing tons of >times without incident. There are two short traces from the a uP >parallel port to the CCLK and DIN pins on the FPGA; PROGRAM- is wired >to the uP RESET- line, so we can config the chip after powerup. We're >using code that has always worked; the bits from the RBT file are >built into the uP rom image, and the processor just bangs the bits >out. Timing is legal and conservative; setup/hold times exceed a >microsecond. CCLK and DIN are 5 volt, fairly slow HCMOS levels, but >that should be OK here. Powerup sequence is legal. > >But this one won't configure. INIT just stays high after reset, even >if I load deliberately bad data frames. This for three days! CCLK and >DIN look OK, in fact very clean, on their test points, but finally I >decide to look at CCLK and DIN *at the fpga pins*. So, when I touch a >scope probe on the CCLK pin and run the code, the green LED (on DONE) >lights! It works! It also works if the CCLK pin is touched with a >small insulated screwdriver, 330 ohms to ground, or an x-acto knife, >but not a toothpick (so it's not mechanical). The scope waveform looks >fine, no serious ringing or whatever, but the probe capacitance is >doing something. > >Anybody seen anything like this? > >John Sure. (Although you don't say, I am assuming you are using Serial Slave configuration mode) The clue is that loading the CCLK fixes things. As I was reading your description I was thinking mechanical, so great that you did a test with an insulator. Unfortunately you can't trust the scope picture, because as you have said, probing the CCLK pin fixes it. Often people are using passive probes (7 to 15 pf load) and scopes with bandwidth of 200 MHz or lower. You don't say what you are using. When I look for this stuff, I use at least 500 MHz bandwidth scope+probe system, with an active FET probe with 1 pf load. This has shown stuff that passive probes miss. My best guess is that you have a signal integrity problem (termination, stubs, reflections, ...) and the problem is on the falling edge of CCLK, which you are probably not looking at. What I have seen is that during the falling edge, a SI problem leads to a little U turn in the clock during either the rising OR falling edge. Murphy often causes the U turn to occur at about the mid point of the falling edge, at about the trip point of the receiver. This looks to the receiver (CCLK in, in your case) as if there is a rising edge at the falling edge. The result is sub-optimal. I last wrote about this in 12/13/2001 http://www.fpga-faq.com/archives/37500.html#37520 The reason that even INIT is not going low is that even the header is not being received correctly, and so it is not even starting the configuration process. One of the best ways to diagnose the start of configuration problems is to look at the DOUT pin. You should see a complete copy of the initial header come out the DOUT pin a cycle or 2 after it goes in on DIN . If you don't see this, then neither did the FPGA. Please let us know how things go on this. All the best, Philip Philip Freidin FliptronicsArticle: 62079
If you use Xilinx IP Core A - 6 bit B - 6 bit B- 12 bit is enough "Anil Khanna" <anil_khanna@mentor.com> 写入消息新闻 :3f906a1c$1@solnews.wv.mentorg.com... > I am trying to construct a 6x6 signed multiplier using the Virtex II block > multipliers. I know that the V-II multipliers are inherently a 2's > complement signed multiplier. However, my question is - by how much should I > sign-extend the inputs? > > Example: > Input A - 6 bit > Input B - 6 bit > Output B- 12 bit > > Should I connect the remaining ports of the multiplier input (A(7:18)) to > A(6) or just A(7:12) to A(6)? The handbook suggests that the sign-extension > of the inputs is done till the width of the output. Is this enough or should > I do it till the physical width of the multiplier? > > Thanks > > Anil > >Article: 62081
Hi D :-), What about a TV ping-pong game? I just checked the one on my website and it seems to fit in a XCS10. You need just 3 resistors to drive a VGA monitor and I believe your boards 25MHz crystal will be OK to generate the V/HSync signals (use a good multi-sync monitor). http://www.ht-lab.com/freecores/pingpong/pingpong.htm Good luck, Hans. www.ht-lab.com "DGW" <chippa11@hotmail.com> wrote in message news:3f8cb95a$0$21654$afc38c87@news.optusnet.com.au... > I am urgently in search of a simple project that will demonstrate on the old > Xilinx Spartan XCS10. Any intro to medium sized project that can perform > functions on the demo board Digilab XLA5 at > http://www.digilentinc.com/Catalog/digilab_xla.html with the LEDs and 7 SEG > displays being utilized would be desirable. Examples may include simple > timers, counters, traffic light controller, etc etc. I know this is a long > shot, but I am desperate!! The files would need to be able to run on Xilinx > Foundation 4.2i or equiv if possible. Schematic design entry would be > preferrable over VHDL but not essential. Apologies to the experts in this NG > and if I am looking in the wrong places can anyone suggest where else to > look/ask/beg? A negotiated fee can be arranged through Kasamba.com. Anyone > genuinely interested or that can help please email me direct. > > Kind Regards (and apologies for being of no help to anyone in a NG!!) > > D > >Article: 62082
"nameiswolf" <nameiswolf@yahoo.it> ha scritto nel messaggio news:cb37e4f2.0310170705.5cd0db89@posting.google.com... > I think it is not a matter of Libia or Bulgaria or other > countries: if > the FPGA market in Italy can't swallow enough chips, then > Altera/Xilinx/XYZ will simply neglect this market. I can > understand > their position. Good point, but this seems a little like the story of the chicken and the egg (I don't know if the anglo-saxon people are familiar with it, I will explain if needed :)). How can the FPGA companies expect some interest from Italy, if they don't invest a penny in creating this interest? FPGA are without any doubt an interesting matter, at least more interesting than the average of what you study at the university; I have graduated completely unaware of their potentials, and I've had to learn them by myself, but many others won't (and the older, "classic" electronics engineers consider FPGA a thing completely out of their jurisdiction). The only way to spread FPGA knowledge is to teach them directly into the universities. FPGA and DSP are almost an unknown matter in the italian universities; it would take nothing for a giant like Xilinx or Altera to invest some spare money to "help" creating new italian engineers interested in FPGA. -- LorenzoArticle: 62083
jakab tanko wrote: > In my humble oppinion the best software from Xilinx was 4.2, > it's all downhill from there; I agree. 4.2 had bugs, but it was possible to work around them. Trying to compile the same project under 5.x and 6.x is a disaster. The bugs are so bad that it won't even synthesize.Article: 62084
chadb@beardendesigns.com (Chad Bearden) writes: > Could anyone recommend a tool for analyzing the pci or pci-x protocol? > > I'm developing a pci-x board that will plug into a pc architecture. I > have googled around and found several manufacturers but am looking for > testimonials from those that have actually used such products and > would comment on their usability and features. I've been using the VMETRO PCI analyzers and are pretty happy with them. I havent't used their PCI-X analyzer yet. Petter -- A: Because it messes up the order in which people normally read text. Q: Why is top-posting such a bad thing? A: Top-posting. Q: What is the most annoying thing on usenet and in e-mail?Article: 62085
Rene Tschaggelar wrote: > > Alessandro Strazzero wrote: > > "Geoffrey Mortimer" <me@privacy.net> wrote in message news:<bmjk16$ngmof$1@ID-163942.news.uni-berlin.de>... > >> > >>Anyone have any experience of BGA's (especially fine pitch types) in high > >>vibration environments? Is there a more appropriate newsgroup for this > >>topic? > > > > It strongly depends from your vibration requirements. > > > > I currently use electronic boards installed into railway equipments which use > > BGA components, and they are conforme to the European Union railway equipment > > manifacturing specification > > Hi Alessandro, > are there any specifications on the vibration ? > Frequency, amplitude, pattern ? > Perhaps a defined testing procedure ? This thread might do well in comp.arch.fpga. There are several FAEs there who love digging into just this sort of issue. I have crossposted there. -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAXArticle: 62086
Hi, does anybody have experience in using Altium DXP for designing Xilinx FPGA? Is it possible to compile Xilinx libraries (unisim/coregenlib/simprim) for using them in DXP? DXP is not supported by Xilinx, what are the risks in using it? kind regards Dieter KeldenichArticle: 62087
Dieter Keldenich wrote: > Hi, > > does anybody have experience in using Altium DXP for designing Xilinx FPGA? > Is it possible to compile Xilinx libraries (unisim/coregenlib/simprim) for > using them in DXP? > DXP is not supported by Xilinx, what are the risks in using it? You should ask this question on the altium forums, available at the altium website. Rene -- Ing.Buero R.Tschaggelar - http://www.ibrtses.com & commercial newsgroups - http://www.talkto.netArticle: 62088
On Sat, 18 Oct 2003 01:20:57 GMT, Philip Freidin <philip@fliptronics.com> wrote: > >Sure. > >(Although you don't say, I am assuming you are using Serial Slave >configuration mode) Right. > >The clue is that loading the CCLK fixes things. > >As I was reading your description I was thinking mechanical, so >great that you did a test with an insulator. > >Unfortunately you can't trust the scope picture, because as you have >said, probing the CCLK pin fixes it. Often people are using passive >probes (7 to 15 pf load) and scopes with bandwidth of 200 MHz or >lower. You don't say what you are using. When I look for this stuff, >I use at least 500 MHz bandwidth scope+probe system, with an active >FET probe with 1 pf load. This has shown stuff that passive probes >miss. > >My best guess is that you have a signal integrity problem (termination, >stubs, reflections, ...) and the problem is on the falling edge of CCLK, >which you are probably not looking at. What I have seen is that during >the falling edge, a SI problem leads to a little U turn in the clock >during either the rising OR falling edge. Murphy often causes the U turn >to occur at about the mid point of the falling edge, at about the trip >point of the receiver. This looks to the receiver (CCLK in, in your case) >as if there is a rising edge at the falling edge. The result is >sub-optimal. > >I last wrote about this in 12/13/2001 > > http://www.fpga-faq.com/archives/37500.html#37520 > >The reason that even INIT is not going low is that even the header >is not being received correctly, and so it is not even starting the >configuration process. > >One of the best ways to diagnose the start of configuration problems >is to look at the DOUT pin. You should see a complete copy of the >initial header come out the DOUT pin a cycle or 2 after it goes in >on DIN . If you don't see this, then neither did the FPGA. > > >Please let us know how things go on this. > >All the best, > >Philip > > > > >Philip Freidin >Fliptronics Hi, Philip, Well, we've probed it with a 1 pF, 1 GHz fet probe into a TDS3052 (500 MHz) scope, and CCLK still looks beautiful. Maybe I should try the 3 GHz sampling probe next! The 68332 port edge is pokey enough that we wouldn't expect much ringing on a short trace, and we've done much longer and nastier multiple-FPGA configs without problems. The fix is to kluge a 33 pF cap at the CCLK pin to ground. When we turn the PCB layout, we'll do something more elegant maybe, like source terminating *and* hanging the cap, but it remains a mystery. Heck, we're engineers: we don't have to understand it, we only have to make it work. Thanks Oh: I have a Windows command-line app that builds ROM images out of Motorola S28 files and multiple .RBTs. Any interest? JohnArticle: 62089
October 18, 2003 The procedure is posted at: <http://linuxan.tripod.com> If you experience any problem, (I may I missed something) post a message here.Article: 62090
October 18, 2003: just posted the procedure: <http://linuxan.tripod.com> If I forgot something, please let me know. (Post here). ----- uselinux2000@yahoo.com (linux user) wrote in message news:<c02536de.0310161303.20ebd240@posting.google.com>... > OK: > It seems there is some interest, give me a day or two and I will > verify and post a step by step list. Under the same subject/thread. > UL2K > > > uselinux2000@yahoo.com (linux user) wrote in message news:<c02536de.0310151721.7d855d14@posting.google.com>... > > Hello: > > Altera Quartus II version 3.0 runs fine on RedHat Linux 9.0. > > If you are interested, I will post here how to do this. > > ----Article: 62091
Nicholas C. Weaver wrote: > Well, I FINALLY finished my PhD. > > For those who are exceedingly bored, my dissrtation is online (The > SFRA: A Fixed-Frequency FPGA Architecture) at > http://www.cs.berkeley.edu/~nweaver/nweaver_thesis.pdf > Congrats -- read the TOC, final conclusion and bibliography . Job well done! JoeGArticle: 62092
Peter Alfke wrote: > If your homework is too tough, > and the time just flies away, > thinking hard is not enough, > click: comp.arch.fpga. > > There you find those friendly souls, > Austin, Philip, Peter, Ray > filling in your mental holes, > making problems go away. > > But learning is for you to do, > even if it hurts the brain. > The one that has to learn is you. > There's no substitute for pain. > > If you want to learn design > don't treat homework just as play. > Real life is not benign, > and you'll have to earn your pay! > > sooner or later... > > These lines were triggered by the endless dice discussion. > Peter Alfke, Xilinx Applications I'm glad I didn't have access to the Inet during my college days, as my efforts in class/homework would not have been as rewarding and industrious. You wonder if the intellecutal output of men like Augustine or Da Vinci would have been stunted if they had a laptop? JoeGArticle: 62093
Hi John, On Sat, 18 Oct 2003 16:39:38 -0700, John Larkin <jjlarkin@highlandSNIPtechTHISnologyPLEASE.com> wrote: >On Sat, 18 Oct 2003 01:20:57 GMT, Philip Freidin ><philip@fliptronics.com> wrote: >> >>(Although you don't say, I am assuming you are using Serial Slave >>configuration mode) > >Right. > >> ..... >>One of the best ways to diagnose the start of configuration problems >>is to look at the DOUT pin. You should see a complete copy of the >>initial header come out the DOUT pin a cycle or 2 after it goes in >>on DIN . If you don't see this, then neither did the FPGA. I really should have emphasized this. Since you are using serial slave, the DOUT pin can give you a clear view of what the chip thinks it is getting, and you can look at this pin without loading the CCLK pin, so the issue of probing CCLK goes away. Until the header is recognized and completed, the DOUT pin echos th DIN pin. So if there are clock integrity problems you will see weirdness on the DOUT pin. Since you are using XC2S15, the DOUT changes as a result of a CCLK rising edge. If you saw a DOUT change that followed a falling edge, this would be a significant indicator. Other interesting things you might see are bits being dropped, indicating a rising edge is being missed, or failing to meet setup and hold with regard to CCLK. Maybe your micro is putting CCLK out upside down? Maybe your micro (i.e. your download program) is changing the DIN bit at the same time as it changes the CCLK bit from '0' to '1' . This is a race condition. These need to be separate I/O writes to the output register, to make sure that DIN is stable at the new value, before you switch the CCLK from low to high. >> >>Please let us know how things go on this. >> >>All the best, >> >>Philip > .... > >The fix is to kluge a 33 pF cap at the CCLK pin to ground. When we >turn the PCB layout, we'll do something more elegant maybe, like >source terminating *and* hanging the cap, but it remains a mystery. Don't succumb to the dark side. There is a solution that does not involve 33 pf caps. :-) >Heck, we're engineers: we don't have to understand it, we only have to >make it work. ( you left off the smiley ) Unsurprisingly I disagree. If you don't understand it, it will come back to bite you over and over again. You have done far too many FPGA designs to believe that serial config does not work, so the tough question is to figure out what is wrong with this design. >Thanks > >Oh: I have a Windows command-line app that builds ROM images out of >Motorola S28 files and multiple .RBTs. Any interest? Little tools like this are always useful. If you want to donate it, I can make it available at www.fpga-faq.com . Just email it to me. >John Please dont go the 33 pf route. I want to know what the real problem is. Good luck, Philip Philip Freidin FliptronicsArticle: 62094
chadb@beardendesigns.com (Chad Bearden) wrote in message news:<906428f5.0310160842.420b70b8@posting.google.com>... > Is it possible to create a 3rd party pci dma engine? > > I would like to dma to/from host memory to a pci device that supports > burst read/writes but has no dma hardware. > > This mythical circuit would be saying "Hey! Mr Host please send a > block of data to that pci device over there." or "Hey, Mr Host grab a > block of data from that pci device and put it in your ram." > > chad. You need a PCI master: each DMA operation reads (using PCI Master transactions) from a source device to a FIFO, then writes (again, using PCI Master transactions) to the destination. Both X and A have an FPGA PCI master/target core, but its NRE is not trivial; if your application is not intended for a large design, I'd recommend using and off-the-shelf PCI interface chip (PLX or similar) and an FPGA on its local-bus side. IIRC, the PLX chip even has an integrated DMA controller between the PCI and local bus, making the FPGA much simpler and smaller than if it had to contain a PCI core and a DMA controller. Some additional issues: you need some sort of a DMA-Request signal (maybe use one of the INTx# lines and mask it for the CPU's int'pt controller?). The design would work better it you can distribute DMA cycles and not transfer everything in one huge burst. And finally: why not change your I/O device to one that has PCI-master capabilities? if it's a third-party one, there are probably others with the same functionality; if it's your own design, you can re-design it - adding PCI Master capabilities at the source is much easier than adding it in an additional, dedicated card.Article: 62095
A trivial point - are you sending enough CCLK pulses ? I had something vaguely similar to your problem, which turned out to be stopping generating CCLK pulses as soon as I had seen DONE, wheras you actually need a few more to startup everything ... Dave "Philip Freidin" <philip@fliptronics.com> wrote in message news:a964pvks3uor3v1dv7jse71jk8pq904gd0@4ax.com... > Hi John, > > On Sat, 18 Oct 2003 16:39:38 -0700, John Larkin <jjlarkin@highlandSNIPtechTHISnologyPLEASE.com> wrote: > >On Sat, 18 Oct 2003 01:20:57 GMT, Philip Freidin > ><philip@fliptronics.com> wrote: > >> > >>(Although you don't say, I am assuming you are using Serial Slave > >>configuration mode) > > > >Right. > > > >> ..... > >>One of the best ways to diagnose the start of configuration problems > >>is to look at the DOUT pin. You should see a complete copy of the > >>initial header come out the DOUT pin a cycle or 2 after it goes in > >>on DIN . If you don't see this, then neither did the FPGA. > > I really should have emphasized this. Since you are using serial slave, > the DOUT pin can give you a clear view of what the chip thinks it is > getting, and you can look at this pin without loading the CCLK pin, so > the issue of probing CCLK goes away. Until the header is recognized > and completed, the DOUT pin echos th DIN pin. So if there are clock > integrity problems you will see weirdness on the DOUT pin. Since you > are using XC2S15, the DOUT changes as a result of a CCLK rising edge. > > If you saw a DOUT change that followed a falling edge, this would be a > significant indicator. Other interesting things you might see are bits > being dropped, indicating a rising edge is being missed, or failing to > meet setup and hold with regard to CCLK. > > Maybe your micro is putting CCLK out upside down? > > Maybe your micro (i.e. your download program) is changing the DIN bit > at the same time as it changes the CCLK bit from '0' to '1' . This > is a race condition. These need to be separate I/O writes to the output > register, to make sure that DIN is stable at the new value, before you > switch the CCLK from low to high. > > >> > >>Please let us know how things go on this. > >> > >>All the best, > >> > >>Philip > > > .... > > > >The fix is to kluge a 33 pF cap at the CCLK pin to ground. When we > >turn the PCB layout, we'll do something more elegant maybe, like > >source terminating *and* hanging the cap, but it remains a mystery. > > Don't succumb to the dark side. There is a solution that does not > involve 33 pf caps. :-) > > >Heck, we're engineers: we don't have to understand it, we only have to > >make it work. > > ( you left off the smiley ) > > Unsurprisingly I disagree. If you don't understand it, it will come back > to bite you over and over again. You have done far too many FPGA designs > to believe that serial config does not work, so the tough question is to > figure out what is wrong with this design. > > >Thanks > > > >Oh: I have a Windows command-line app that builds ROM images out of > >Motorola S28 files and multiple .RBTs. Any interest? > > Little tools like this are always useful. If you want to donate it, I > can make it available at www.fpga-faq.com . Just email it to me. > > >John > > Please dont go the 33 pf route. I want to know what the real problem is. > > Good luck, > Philip > > > > > > Philip Freidin > FliptronicsArticle: 62096
ramntn@yahoo.com (ram) wrote in message news:<61c2cc9d.0310161026.2baece90@posting.google.com>... > Hi , > I am trying to find an example design that would explain me how to > set up the system ace configuration to configure MPU CF > interface.also, i am looking for documents or applicatoin notes other > than the system ACE data sheet from xilinx. > Any help is appreciated > thank you > Regards > RAm grab ML300 scheamatics from xilinx web there is SystemACE also included. anttiArticle: 62097
Thanks for the reply. However, I am not using the Xilinx Coregen! Anyways, I figured out the answer to this question and now I have another Q. The handbook claims that there are certain submodules (of the MULT18X18S) available for use. These are submodules like MULT4X4 etc. How does one get access to this and what is the primitive name? Anil "Peng Cong" <pc_dragon@sohu.com> wrote in message news:bmqfru$j8h$1@news.yaako.com... > If you use Xilinx IP Core > A - 6 bit B - 6 bit B- 12 bit > is enough > > "Anil Khanna" <anil_khanna@mentor.com> 写入消息新闻 > :3f906a1c$1@solnews.wv.mentorg.com... > > I am trying to construct a 6x6 signed multiplier using the Virtex II block > > multipliers. I know that the V-II multipliers are inherently a 2's > > complement signed multiplier. However, my question is - by how much should > I > > sign-extend the inputs? > > > > Example: > > Input A - 6 bit > > Input B - 6 bit > > Output B- 12 bit > > > > Should I connect the remaining ports of the multiplier input (A(7:18)) to > > A(6) or just A(7:12) to A(6)? The handbook suggests that the > sign-extension > > of the inputs is done till the width of the output. Is this enough or > should > > I do it till the physical width of the multiplier? > > > > Thanks > > > > Anil > > > > > >Article: 62098
Hi, I want to get rid of the warnings when not using the SPO port on a dual port ram(DPR). Using RAM16X1D's to build a DPR within a Spartan2 using ISE. When writing to the DPR on the synchronous port I never want to get the data out of SPO. Is there a way I can remove the warnings "SPO has no load" by connecting some sort of 'sink' to this port. I have tried pulldowns but still "no load". I use the asynchronous port (DPRA and DPO) to read the data out. Thanks,Ben.Article: 62099
> > I'm glad I didn't have access to the Inet during my college days, as my > efforts in class/homework would not have been as rewarding and industrious. > > You wonder if the intellecutal output of men like Augustine or Da Vinci > would have been stunted if they had a laptop? > > JoeG Now, its all about speed Finding the solution by yourself, is rewarding ever but, "will you get the job done by time" I am not suggesting getting solutions are the best way,i am pointing out, the hurdles on your path towards goal may not be totally relevent, eg, there might some glitch in software tools,though your program is correct, what if the tool suggests otherwise, unless you ask someone, you wouldnt know. There I belive Inet is much rewarding. bye RAm
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