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"Peter Alfke" <peter@xilinx.com> wrote in message news:3F8D76F9.416635DF@xilinx.com... [...snip poetry...] > These lines were triggered by the endless dice discussion. > Peter Alfke, Xilinx Applications Surely you should have signed it "e e alfke" ??? (With apologies to the other Cummings, of course.) -- Jonathan Bromley, Consultant DOULOS - Developing Design Know-how VHDL * Verilog * SystemC * Perl * Tcl/Tk * Verification * Project Services Doulos Ltd. Church Hatch, 22 Market Place, Ringwood, Hampshire, BH24 1AW, UK Tel: +44 (0)1425 471223 mail: jonathan.bromley@doulos.com Fax: +44 (0)1425 471573 Web: http://www.doulos.com The contents of this message may contain personal views which are not the views of Doulos Ltd., unless specifically stated.Article: 62001
Peter Alfke <peter@xilinx.com> wrote in message news:3F8C5BC4.641FA8DA@xilinx.com... > I admit, my "irony detector" was temporarily asleep, and the German > seriousness took over... Coming from Northern Ireland my 'irony detector' is stuck at 10. Nial ------------------------------------------------ Nial Stewart Developments Ltd FPGA and High Speed Digital Design www.nialstewartdevelopments.co.ukArticle: 62002
I am trying to do a simple project using Atmel's WinCUPL, and having some problems finding documentation. In particular, I don't have the help file(s) for WinSim - that is, the <help - simulator> menu selection yields no content. I don't find any WinSim docs the Atmel website. Any clues would be appreciated. TIA, George Eccles -----= Posted via Newsfeeds.Com, Uncensored Usenet News =----- http://www.newsfeeds.com - The #1 Newsgroup Service in the World! -----== Over 100,000 Newsgroups - 19 Different Servers! =-----Article: 62003
Could anyone recommend a tool for analyzing the pci or pci-x protocol? I'm developing a pci-x board that will plug into a pc architecture. I have googled around and found several manufacturers but am looking for testimonials from those that have actually used such products and would comment on their usability and features. chad.Article: 62004
Rick, The startup current is very small, probably less than 20 mA. The 50 mA number was a good number over PVT. As for speed at temp, the part is probably the last one to have a classic design of CLBs and interconnect (No DLL, No other "fancy features") so some of the old "rules of thumb" for CMOS logic performance vs. temperature still apply to it. Maybe Peter can help us here with some rule of thumb numbers for plain 'ole CMOS logic. If you open a case on the hotline with your specifc tool and support question, you will get an answer quickly. Austin rickman wrote: > Before I close the door on this, I want to take one last look at using > the SpartanXL for this socket. Right now there are several reasons not > to use the part, but only one is a show stopper. That is the lack of an > industrial temp part in the CS280 package. Looking at other lines, I > see that there is nothing inherent about the package that precludes > this. > > So what would it take for me to use a commercial temp part, say the > XCS40XL-5CS280C and use it over an industrial temp range? If I scaled > my timing requirements by say, 33%, would that give me enough margin > over the industrial temp range? > > Of course the other issues are not trivial. List price is way up there, > the lack of support in the ISE tools will require me to buy a $5000 > synthesis tool, and I am still a little leary of designing in such an > old part to a product line that may have a lifetime of 8 years. > > I recall working with one of these parts some 6 or 7 years ago. The > toolset from Xilinx included synthesis, IIRC. Is that package no longer > available? > > I see in the archives here that the quiescent current for the SpartanXL > is very low, much lower than the data sheet number. But I can't find a > clear statement about the startup current. The data sheet says 100 mA > (which should not be a problem) but I wanted to know if this is much > lower in current chips. > > -- > > Rick "rickman" Collins > > rick.collins@XYarius.com > Ignore the reply address. To email me use the above address with the XY > removed. > > Arius - A Signal Processing Solutions Company > Specializing in DSP and FPGA design URL http://www.arius.com > 4 King Ave 301-682-7772 Voice > Frederick, MD 21701-3110 301-682-7666 FAXArticle: 62005
I have the impression that partial reconfig is sort of dying on the vine.
Tools for it are far from ready for prime time, and the devices have been
growing fast enough that the added development cost to implement partial
reconfig generally outweighs the cost savings achieved for all but the
highest volume designs. I'd done a number of designs that took advantage
of reconfig several years back, but now am not seeing much call for it.
rickman wrote:
> "Nicholas C. Weaver" wrote:
> >
> > Well, I FINALLY finished my PhD.
> >
> > For those who are exceedingly bored, my dissrtation is online (The
> > SFRA: A Fixed-Frequency FPGA Architecture) at
> > http://www.cs.berkeley.edu/~nweaver/nweaver_thesis.pdf
>
> Congrats... I am sure it was a lot of work. :)
>
> Since you are in that lofty group and must have a much better view than
> the rest of us, are you aware of much research in FPGAs about
> partial/modular configuration?
>
> Just curious.
>
> --
>
> Rick "rickman" Collins
>
> rick.collins@XYarius.com
> Ignore the reply address. To email me use the above address with the XY
> removed.
>
> Arius - A Signal Processing Solutions Company
> Specializing in DSP and FPGA design URL http://www.arius.com
> 4 King Ave 301-682-7772 Voice
> Frederick, MD 21701-3110 301-682-7666 FAX
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 62006Hi JuHwa, ICAP can also access the IPIF. But of course, you should avoid moidfying the area defining the IPIF since it may introduce misbehavior in the ICAP. To set a system up, you can use the EDK to design an embedded system supporting Linux port. Basically, the system consists of a processor (Microblaze, or PPC450 in Virtex-II Pro), some IP core peripherals and PLB/OPB/DCR buses to connect the processor core to other cores. You can refer to the ML300 embedded system reference deisgn to get an idea of it. To use the ICAP in a system mentioned before is straightforward. You merely need to attach the "ipif_slv_sram" in XAPP 662 reference design to PLB/OPB. Hope this helps, tk t depends on the device you use. If you are using Virtex-II Pro, you can "PanJuHwa" <panjuhwa_fpga@yahoo.com> ???????:89e30c0c.0310150853.415294f4@posting.google.com... > Hi, > > I am very interested in exploring the use of ICAP for > self-reconfiguration of the Virtex2 fpga. XAPP 662 describes the > in-system reconfiguration of RocketIO attributes, and I have been > trying to understand the process of self-reconfiguration through this > application note as well as the reference design that comes with it. > > It seems that we need to configure the FPGA with a bitstream > generated from hdl that includes an PLB bus arbitrator and controller, > as well as ICAP IPIF to the PLB. Does this mean the ICAP, possessing > access the configuration memory, would actually have access to parts > of the configuration memory that defines the arbitrator and ICAP IPIF > as well? Or are is the information used to configure the arbitrator > and IPIF somewhere else? Say for instance the fpga is to be configured > with a jpeg encoder. Would the configuration memory accessed by the > ICAP be solely occupied by the jpeg encoder configuration, or by the > ipif etc as well? If in the latter case, then ICAP should never modify > areas defining the IPIF, is this correct? > > I would appreciate too if someone who has done this before can > provide some guidelines on how I can set the system up to use the > ICAP. Thanks in advance!:) > > Ju HwaArticle: 62007
The traditional view was that delays increase at a rate of 0.25% per degree C. With Industrial being nominally 15 degr hotter than Comm, this would mean a 4% loss in speed at the hot end. We gave the ususal warnings: "Not guaranteed since not tested," but I never heard any complaints. I have never heard about a Comm part failing functionally at Ind temperature. But the speed loss is real. If your part is running hot, and Industrial it's not, use this factor to derate and let's finish the debate. Peter Alfke =========================== Austin Lesea wrote: > > Rick, > > The startup current is very small, probably less than 20 mA. The 50 mA > number was a good number over PVT. > > As for speed at temp, the part is probably the last one to have a classic > design of CLBs and interconnect (No DLL, No other "fancy features") so some > of the old "rules of thumb" for CMOS logic performance vs. temperature still > apply to it. Maybe Peter can help us here with some rule of thumb numbers > for plain 'ole CMOS logic. > > If you open a case on the hotline with your specifc tool and support > question, you will get an answer quickly. > > Austin > > rickman wrote: > > > Before I close the door on this, I want to take one last look at using > > the SpartanXL for this socket. Right now there are several reasons not > > to use the part, but only one is a show stopper. That is the lack of an > > industrial temp part in the CS280 package. Looking at other lines, I > > see that there is nothing inherent about the package that precludes > > this. > > > > So what would it take for me to use a commercial temp part, say the > > XCS40XL-5CS280C and use it over an industrial temp range? If I scaled > > my timing requirements by say, 33%, would that give me enough margin > > over the industrial temp range? > > > > Of course the other issues are not trivial. List price is way up there, > > the lack of support in the ISE tools will require me to buy a $5000 > > synthesis tool, and I am still a little leary of designing in such an > > old part to a product line that may have a lifetime of 8 years. > > > > I recall working with one of these parts some 6 or 7 years ago. The > > toolset from Xilinx included synthesis, IIRC. Is that package no longer > > available? > > > > I see in the archives here that the quiescent current for the SpartanXL > > is very low, much lower than the data sheet number. But I can't find a > > clear statement about the startup current. The data sheet says 100 mA > > (which should not be a problem) but I wanted to know if this is much > > lower in current chips. > > > > -- > > > > Rick "rickman" Collins > > > > rick.collins@XYarius.com > > Ignore the reply address. To email me use the above address with the XY > > removed. > > > > Arius - A Signal Processing Solutions Company > > Specializing in DSP and FPGA design URL http://www.arius.com > > 4 King Ave 301-682-7772 Voice > > Frederick, MD 21701-3110 301-682-7666 FAXArticle: 62008
"vick" <vhdl200@yahoo.com> wrote: > hi to all can anyone please explain to me how each line of the code work please..... > thank to all EVERY LINE?!!!! >>>>>> cleaned up by archive manager :-) In general terms, out of respect for those who might take time away from their work to help out on a newsgroup, it is customary to at least make an attempt to exhaust generally available sources of information FIRST and only then resort to posting on a newsgroup. There are many freely available VHDL tutorials on the Web. Do a search for such topics as "VHDL", "VHDL Tutorial", "FPGA Tutorial", "HDL Tutorial", etc. Get creative. Spend a week trying to learn and figure this out on your own. If you have specific questions I'm sure many here would be glad to help you. -- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ Martin Euredjian To send private email: 0_0_0_0_@pacbell.net where "0_0_0_0_" = "martineu"Article: 62009
Then you've seen www.portadownnews.com ? The 'Drumcree VII' edition, featuring "Vatican sends Holy Water Cannon", is a favourite! cheers, Syms. > > Coming from Northern Ireland my 'irony detector' is stuck at > 10. > > > NialArticle: 62010
Hey. I have a customer who wants to buy a couple of Hot 2 boards but I really don't want to make another run. If anyone has any Hot 2 boards they want to sell back us please let me know. Thanks Steve Casselman Virtual ComputerArticle: 62011
Is it possible to create a 3rd party pci dma engine? I would like to dma to/from host memory to a pci device that supports burst read/writes but has no dma hardware. This mythical circuit would be saying "Hey! Mr Host please send a block of data to that pci device over there." or "Hey, Mr Host grab a block of data from that pci device and put it in your ram." chad.Article: 62012
I want to test the example in page 217 of DK2 Handel-C Language
Reference Manual.
-------
ram unsigned 8 RAM1[4] = {0,1,2,3} with {block="BlockRAM"};
ram unsigned 8 RAM2[4] with {block="BlockRAM"};
signal s;
unsigned x;
unsigned i;
while(1)
{
par
{
s = RAM1[i];
RAM2[i] = s;
x = s;
i++;
}
}
-------
BUt it doesn't compile, I get the following error: Illegal
initializer. I suppose that I can't initialize the RAM, then why
Celoxica give examples that doesn't works? or what's missing?
Thanks
Gerardo
Article: 62013OK, a simple system: a Motorola MC68332 uP is trying to configure a Spartan2 chip, an XC2S15-VQ100. We've done this sort of thing tons of times without incident. There are two short traces from the a uP parallel port to the CCLK and DIN pins on the FPGA; PROGRAM- is wired to the uP RESET- line, so we can config the chip after powerup. We're using code that has always worked; the bits from the RBT file are built into the uP rom image, and the processor just bangs the bits out. Timing is legal and conservative; setup/hold times exceed a microsecond. CCLK and DIN are 5 volt, fairly slow HCMOS levels, but that should be OK here. Powerup sequence is legal. But this one won't configure. INIT just stays high after reset, even if I load deliberately bad data frames. This for three days! CCLK and DIN look OK, in fact very clean, on their test points, but finally I decide to look at CCLK and DIN *at the fpga pins*. So, when I touch a scope probe on the CCLK pin and run the code, the green LED (on DONE) lights! It works! It also works if the CCLK pin is touched with a small insulated screwdriver, 330 ohms to ground, or an x-acto knife, but not a toothpick (so it's not mechanical). The scope waveform looks fine, no serious ringing or whatever, but the probe capacitance is doing something. Anybody seen anything like this? JohnArticle: 62014
i is used before it is set. Maybe
unsigned i = 0;
as the declaration.
Steve
"Gerardo Sosa" <gerardo_sr@yahoo.com> wrote in message
news:f4ee0441.0310160852.5e4ecb48@posting.google.com...
> I want to test the example in page 217 of DK2 Handel-C Language
> Reference Manual.
>
> -------
> ram unsigned 8 RAM1[4] = {0,1,2,3} with {block="BlockRAM"};
> ram unsigned 8 RAM2[4] with {block="BlockRAM"};
> signal s;
> unsigned x;
> unsigned i;
> while(1)
> {
> par
> {
> s = RAM1[i];
> RAM2[i] = s;
> x = s;
> i++;
> }
> }
> -------
>
> BUt it doesn't compile, I get the following error: Illegal
> initializer. I suppose that I can't initialize the RAM, then why
> Celoxica give examples that doesn't works? or what's missing?
>
> Thanks
>
> Gerardo
Article: 62015Hi, Thats a sequential 30 state state machine.Depending on the value of presetn_dte it selects one of the cases and does the specified operation. get any VHDL book, look for modelling a state machine. or refer to Digital system desing using VHDL by charles H.Roth. chapter 2. The program uses a case statement eg, let a be a one bit signal, so when a == '1' it does some operation or when a == '2' it does diff operation. code: case a is when '1' => <stmts> when '2' => <.. > end case; bye RAm vhdl200@yahoo.com (vick) wrote in message news:<eac82d4b.0310152336.1c07273f@posting.google.com>... > hi to all can anyone please explain to me how each line of the code work please..... > thank to all > :) >Article: 62016
Hi , I am trying to find an example design that would explain me how to set up the system ace configuration to configure MPU CF interface.also, i am looking for documents or applicatoin notes other than the system ACE data sheet from xilinx. Any help is appreciated thank you Regards RAmArticle: 62017
"Antti Lukats" <antti@case2000.com> wrote in message news:80a3aea5.0310152229.4ada1a00@posting.google.com... > "SneakerNet" <nospam@nospam.org> wrote in message news:<x_hjb.179653$JA5.4501661@news.xtra.co.nz>... > > "Antti Lukats" <antti@case2000.com> wrote in message > > news:80a3aea5.0310150300.79f98bbd@posting.google.com... > > > "SneakerNet" <nospam@nospam.org> wrote in message > > news:<Qf%ib.178724$JA5.4476502@news.xtra.co.nz>... > > > > Hi All > > > > > > > > Has anyone got this going fully (using the VB code from the site)? I'm > [snip] > 1 englsish translation please post or send per email antti@openchip.org > 2 sorry if the japanese version doesnt work together with the VB code, > I did not check for that, only assumed. > > Q: When you plugin the device windows does show a popup? > Q: the leds on the hardware indicate what usb activity? > Q: you connected (the japanese version) usb DP/DM directly to altera fpga? > > using opencores USB 1.1: it works out of box (for xilinx) you need to > grab some additional cores from CVS then it is completer. > > opencores usb1.1 enumerates as usb device (with no microcontroller) but > it does act as USB HID device so you can not use VB code to talk to it > (at least without Windriver or something alike) > > if you have working hardware (connection from cyclone to usb connector) > then you dont have to use USB11T1A just adopt the philio.v from japanese > and connect it between the opencores PHY and usb connector. minor > adoption may be required. > > if you made the japanese version to synthesize for altera is possible > to get access to that modified code? > > hope it was of some help! > > antti Hi Antti I have sent you a email at antti@openchip.org Pls read CheersArticle: 62018
rickman wrote: >Steve Lass wrote: > > >>ram wrote: >> >> >> >>>Hi all, >>>I am interested in doing partial reconfiguration using Xilinx Virtex >>>2 pro, i am having a HW AFX xilinx prototype baord. >>>I tried the small bit manipulation method defined in Xilinx >>>application note >>>xapp290, with the simple example , Example 1 simple system desing from >>>xilinx EDK examples web page. >>>Ok , my desing is this, >>> I am using PPC405, and uartlite and gpio with uart continiously >>>writing some data in Hyper terminal and gpio is connected to four leds >>>and writing '1' to it >>>I tried to change the routing for the LEDs , I do have to mention >>>here, my board has 8 user LEDS, i changed the routing from upper half >>>to lower half and generated the partial bit stream. >>> >>> >>> >>The configuration frames are columns, so if the routing you are changing >>is in the same column >>as the PPC, UART, or any of their routing, they will probably stop. >> >> > >I am looking at using this feature, although not while the chip is >running. One problem I foresee is that with a column alignment, a >module might be very hard to route if it is restricted to just a small >number of columns. > >In my application there are 5 modules with one being constant and four >being changed according to the hardware that is connected. Some of the >planned modules are much larger than others, so I don't see them mapping >to a fixed footprint. Some may be as narrow as two or even one column >in an XC3S400. > >So I have been thinking about partitioning the designs differently. >Instead of mapping modules to columns, I would divide the columns in >half and map the designs to half columns. This won't be an issue as >long as none of the logic (or interconnect) in the column is being used >by running circuitry. But it will require that the bit files be >assembled from partial bit files. Each column will need to be made of >two halves glued together. As long as there is no routing between them, >this should be a simple matter of concatenating two separate streams for >each column. > >Anyone know if this might be practical? > Anything is possible, but I wouldn't call it practical. There are no tools to help out with this type of methodology. I'm not sure how many different combinations you have, but if it's a reaasonable amount, I would suggest creating bistreams for each combination. It seems like you have to do that anyway with your proposal. Steve > > >Article: 62019
ge wrote: > > I am trying to do a simple project using Atmel's WinCUPL, and having > some problems finding documentation. In particular, I don't have the > help file(s) for WinSim - that is, the <help - simulator> menu > selection yields no content. I don't find any WinSim docs the Atmel > website. Any clues would be appreciated. Hmmm. On my install there is a winsim.hlp in the winsim directory. Personally I avoid this GUI - Winsim was a Visual Basic wrapper to CSIM.EXE. The CSIM.exe is much more reliable, and can be called from cupl command line, with a simple -s switch. You create the .SI file in a text editor, and also have the .SO file in another pane, then iterate your way thru the design. This keeps the location between edits, can handle large simulations, and also allows multiple ORDER: VECTORS: sections in a single .SI file. Winsim can only handle a single context SI file. -jgArticle: 62020
OK: It seems there is some interest, give me a day or two and I will verify and post a step by step list. Under the same subject/thread. UL2K uselinux2000@yahoo.com (linux user) wrote in message news:<c02536de.0310151721.7d855d14@posting.google.com>... > Hello: > Altera Quartus II version 3.0 runs fine on RedHat Linux 9.0. > If you are interested, I will post here how to do this. > ----Article: 62021
Ray Andraka wrote: > > I did a similar 3 die design way back when (ca 1976) using TTL parts. > It could easily be done in a small CPLD and a short time with > current tools. With some care (challenge for todays students ?) I believe one can pack 2 dice into a 16V8 - smallest/cheapest programmable logic device made. Ideal for backgammon etc.... What games need 3 dice ? -jgArticle: 62022
rickman wrote: > > So what would it take for me to use a commercial temp part, say the > XCS40XL-5CS280C and use it over an industrial temp range? If I scaled > my timing requirements by say, 33%, would that give me enough margin > over the industrial temp range? Atmel, in their CPLD data state this : # Using “C” Product for Industrial #To use commercial product for industrial temperature ranges, #down-grade one speed grade from the “I” to the “C” device #(7 ns “C” = 10 ns “I”) and de-rate power by 30%. Power here means thermal margin, due to higher Ta. So long as the self-heating is not significant, you will be well under Tj limits. I don't think you are pushing the MHz :) -jgArticle: 62023
In article <mdnjb.16916$ZH4.13630@twister.socal.rr.com>, Vinh Pham <a@a.a> wrote: >Congratulations! Sounds like you didn't have the luxary to concentrate >solely on your PhD. You had to juggle a job and perhaps a family also? Nope. Just had to juggle with interesting distractions like Internet Worms and the like. :) >How was your dissertation defense? What was the topic? Berkeley believes "The best defense is a good offense", I did my thesis offense (qualifying exam) about 2 years ago. >Congrats again, I'm sure you're glad to have it done with. Now you get to >bust your butt getting tenure, if that's your route ;_) Tell me about it! Worse, Darpa is NOT funding security work, at least unclassified security work. -- Nicholas C. Weaver nweaver@cs.berkeley.eduArticle: 62024
Thanks Steve, but I don't think that this be the error, because the
error put the cursor in the line:
ram unsigned 8 RAM1[4] = {0,1,2,3} with {block="BlockRAM"};
Anyway I probed:
unsigned i=0;
and
unsigned i;
i=0;
But, both either don't work.
Regards
Gerardo
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