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Hi all, a simple question: We intend to use a DCM in a Virtex-II Pro to drive multiple OBUF's but only ne feedback signal - of course. What is the best way to minimize the delay difference between the OBUF's? Any help would be appreciated. MarkusArticle: 61876
Markus, Keep the OBUFs to the right or left sides, and near the center of the parts (least H Clock Tree skew from IOB to IOB <<50 ps). Worst is to have them in the center of the top or bottom, and go to the extreme right or left corners (~500 to 600 ps in 2VP100 skew). You can infer the skew on the hclck tree by examining delays in FPGA editor. Austin Markus Meng wrote: > Hi all, > > a simple question: > > We intend to use a DCM in a Virtex-II Pro to drive multiple OBUF's but > only ne feedback signal - of course. What is the best way to minimize the > delay difference between the OBUF's? > > Any help would be appreciated. > > MarkusArticle: 61878
I have sent you a mail regarding this ;o) Thanks "Henry" <otc_friend@gmx.net> wrote in message news:3f8bcdf3_2@news.arcor-ip.de... > There was a project using a Atmel FPSLIC (=AVR+FPGA)vcfor all processing. > The FPGA realized a IDE interface and a 32-bit DSP (!) for decoding MP3 ! > Don't know where but if you mail me I will see on my harddisk. > - Henry > > SneakerNet schrieb in Nachricht ... > >Hi All > > > >Has anyone done/come across a mp3 personal project which is done using FPGA > >with added circuitry. Please let me know. I'm looking at making one myself > >and would like some added help. > > > >Right now i'm doing research on it, so any info pls pass it on. > > > >Kind Regards > > > > > > > > > >Article: 61879
Peter Alfke <peter@xilinx.com> wrote in message news:3F8C3A8E.46F71A51@xilinx.com... > Hi, Jonathan, let me disagree. > I would run this with a single 200 MHz oscillator, and drive the > indicators with a simple counter ( three mod 6 counters cascaded). > The counter goes through all its 216 values once per microsecond, and I > am sure that the human hand cannot cheat with fractional microsecond accuracy. > > Peter Alfke Peter, Was Jonathan not being ironic? The original request reeked of 'late assignment'. Nial. ------------------------------------------------ Nial Stewart Developments Ltd FPGA and High Speed Digital Design www.nialstewartdevelopments.co.ukArticle: 61880
"John_H" wrote: > Did I miss something and all your macros broke when you included only one > RPM_GRID macro? I think they did. I say "I think" because this was several layers back (and days) in a troubleshooting session and I don't remember. I'm reasonably certain that this is what happened: 1- Existing macro with regular grid consisting of several RPMs instantiated at the macro's top level. 2- The macro was built with the lower-left component at X0Y0 (SRL) 3- Had problems with multipliers 4- Decided to use RPM_GRID for the multiplier 5- The macro broke (wouldn't implement) 6- Converted all sub-macros to RPM_GRID 7- Had other problems 8- Went back to a non RPM_GRID implementation and used timing attributes to pull the multiplier into the right location. 9- Moved on I have to say that Xilinx has been very supportive. We are looking into a number of the things I've run into over the last couple of weeks. While no vendor can and will offer perfection, the difference might very well be in the way the user base is supported. ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ Martin Euredjian To send private email: 0_0_0_0_@pacbell.net where "0_0_0_0_" = "martineu"Article: 61881
I admit, my "irony detector" was temporarily asleep, and the German seriousness took over... But the scare story was really so neat. Beware of these super-urgent class assignments! Peter ================== Nial Stewart wrote: > > Peter Alfke <peter@xilinx.com> wrote in message > news:3F8C3A8E.46F71A51@xilinx.com... > > Hi, Jonathan, let me disagree. > > I would run this with a single 200 MHz oscillator, and drive the > > indicators with a simple counter ( three mod 6 counters cascaded). > > The counter goes through all its 216 values once per microsecond, and I > > am sure that the human hand cannot cheat with fractional microsecond > accuracy. > > > > Peter Alfke > > Peter, > > Was Jonathan not being ironic? > > The original request reeked of 'late assignment'. > > Nial. > > ------------------------------------------------ > Nial Stewart Developments Ltd > FPGA and High Speed Digital Design > www.nialstewartdevelopments.co.ukArticle: 61882
I don't received your email. Sent? - Henry SneakerNet schrieb in Nachricht <13Yib.178545$JA5.4472724@news.xtra.co.nz>... >I have sent you a mail regarding this ;o) >Thanks > >"Henry" <otc_friend@gmx.net> wrote in message >news:3f8bcdf3_2@news.arcor-ip.de... >> There was a project using a Atmel FPSLIC (=AVR+FPGA)vcfor all processing. >> The FPGA realized a IDE interface and a 32-bit DSP (!) for decoding MP3 ! >> Don't know where but if you mail me I will see on my harddisk. >> - Henry >> >> SneakerNet schrieb in Nachricht ... >> >Hi All >> > >> >Has anyone done/come across a mp3 personal project which is done using >FPGA >> >with added circuitry. Please let me know. I'm looking at making one >myself >> >and would like some added help. >> > >> >Right now i'm doing research on it, so any info pls pass it on. >> > >> >Kind Regards >> > >> > >> > >> > >> >> > >Article: 61883
Hello, > Well it is not just a bridge, and thats why I cant buy an ASSP. Fair enough. > In the Half Bridge application note from Xilinx, there is specific > chapter dealing with bridging between several PCI-X cores. I do not > need the core to be fully PCI bridge compliant, nor have PCI bridge > configuration header within it. What I need is that the core will > capture type 1 configuration cycles and reflect them on the user > application side of the core. In this way I could have my own logic > to translate those transactions to type 0 configuration transaction > on other busses I have connected to our FPGA. The Xilinx PCI and PCI-X LogiCORE products do not accept Type 1 configuration cycles. They can, however, generate both Type 1 and Type 0 configuration cycles. This makes them suitable for host bridge designs. It makes them unsuitable for the type of design you described. You may ask, then, what the application note is referring to when it discusses bridging bus segments. That application is for making a "cross-link" bridge between two bus segments, where there is already a host for each segment. I will admit that the document is not entirely clear on this point, and I have asked the authors to correct the application note. If you are interested in pursuing your desired application, you should contact your Xilinx FAE, who will be able to assist you. Good luck, Eric > > Hello, > > > > To get a better answer, you'll have to be more specific > > about what you want to build. Are you trying to build a > > fully compliant PCI(-X) to PCI(-X) bridge? If that is > > the case, you should buy an ASSP to do the job. > > > > The Xilinx PCI and PCI-X LogiCOREs, as you might buy them > > over the web, have Type 0 configuration spaces and are not > > suitable for compliant bridging applications. However, > > there are other options and it depends on what you are > > trying to do. > > > > What exactly are you trying to do? > > Eric > > > > > Hi. > > > > > > I'm considering Xilinx LogiCORE PCI-X core, and Xilinx > > > HalfBridge core for building a PCI-X bridge. > > > > > > Can anyone share experience with these cores for PCI bridge > > > application? Does these cores deal with the address > > > translation from "type 1" to "type 0" ? > > > > > > Thankx > > > NAHUMArticle: 61884
Hi Henry I sent you a mail regarding this at otc_friend@gmx.net. Is this your right email? If not what email should I mail you at? Thanks again ;o) "Henry" <otc_friend@gmx.net> wrote in message news:3f8c5ad9_1@news.arcor-ip.de... > I don't received your email. Sent? > - Henry > > SneakerNet schrieb in Nachricht > <13Yib.178545$JA5.4472724@news.xtra.co.nz>... > >I have sent you a mail regarding this ;o) > >Thanks > > > >"Henry" <otc_friend@gmx.net> wrote in message > >news:3f8bcdf3_2@news.arcor-ip.de... > >> There was a project using a Atmel FPSLIC (=AVR+FPGA)vcfor all processing. > >> The FPGA realized a IDE interface and a 32-bit DSP (!) for decoding MP3 ! > >> Don't know where but if you mail me I will see on my harddisk. > >> - Henry > >> > >> SneakerNet schrieb in Nachricht ... > >> >Hi All > >> > > >> >Has anyone done/come across a mp3 personal project which is done using > >FPGA > >> >with added circuitry. Please let me know. I'm looking at making one > >myself > >> >and would like some added help. > >> > > >> >Right now i'm doing research on it, so any info pls pass it on. > >> > > >> >Kind Regards > >> > > >> > > >> > > >> > > >> > >> > > > > > >Article: 61885
hi folks ... since I often see comments in this group pounding on the manufacturers technical support problems I thought I'd offer a different view ... I currently have three Cyclone projects in development, one in house and two for contract customers , and I recently got in the tough stuff over my head and fired off two Altera mySupport requests, the next business day both were answered thoughtfully and in detail ( one took about half a page of typed out steps ) ... yes sometimes the 24hr response time can be a drain but I once again have been suprised with quality support. just my 2'c KB (come on Cyclone 2)Article: 61886
Peter Alfke <peter@xilinx.com> wrote in message > news:3F8C3A8E.46F71A51@xilinx.com... > > Hi, Jonathan, let me disagree. > > I would run this with a single 200 MHz oscillator, and drive the > > indicators with a simple counter ( three mod 6 counters cascaded). > > The counter goes through all its 216 values once per microsecond, and I > > am sure that the human hand cannot cheat with fractional microsecond > accuracy. No, but suppose this has a single push button ? Each spin is going to be close to random, but the designer might be a tad dissappointed at the correlation _across_ the 3 displays ? Maybe some prime number freq multiplies, to give three vfast clocks with different spin rates, would be sufficent. Could be a good exercise for the student, to check the cross-correlation of the 3 displays ? Nial Stewart wrote: > > The original request reeked of 'late assignment'. It certainly did :) -jgArticle: 61887
Peter, thanks, but we have had this conversation several times. None of the Virtex or Spartan II devices can be used in this socket because of the high start up currents. Right now the socket is slated to be filled by an Altera EP1K30 since it meets all the requirements. I was looking at the SpartanXL only because there would be some advantage to having all the PLDs on the board be from one vendor using one tool. But I don't see much advantage to using the SpXL if I have to use the "classic" tools and go with a large package. Peter Alfke wrote: > > Rick, > SpartanXL is an XC4000XL-derivative, while Spartan-II is Virtex-derived. > That means it is a big generation-step younger, more modern, better supported. > All the devices mentioned have 3.3V I/O that are 5-V tolerant. Take a > look at the younger parts, they may give you more flexibility. I hate to > contradict your FAE :-( > > Peter Alfke > ============= > rickman wrote: > > > > I had a meeting with my local salesperson, rep and FAE and they got me > > to take another look at the SpartanXL for the 5 volt tolerant socket on > > my board. The part looks pretty good in most respects, but there are > > two flies in the ointment. One is the lack of support in the current > > tools. I know Xilinx still provides the "classic" tool set which should > > work ok, but I am not comfortable using a different tool and would have > > to buy a third party synthesis tool to support this. > > > > The other problem is that I would have to use the XCS40XL-5CS280 to get > > the density in a small package. But they don't offer an industrial temp > > version in this package. Is there a thermal reason that this package > > won't support the industrial temp range, or is this just a matter of > > space on the shelf for yet another chip version? Any way to get around > > this issue? Is there a spread sheet for calculating the power > > consumption? I have a design that I can extract data from to drive a > > power consumption model if I can get a model. > > > > -- > > > > Rick "rickman" Collins > > > > rick.collins@XYarius.com > > Ignore the reply address. To email me use the above address with the XY > > removed. > > > > Arius - A Signal Processing Solutions Company > > Specializing in DSP and FPGA design URL http://www.arius.com > > 4 King Ave 301-682-7772 Voice > > Frederick, MD 21701-3110 301-682-7666 FAX -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAXArticle: 61888
Jonathan,
Please pay attention to the OPs spec. He/she said 'randomly'. This
implies the measurement of some random process, I suggest radioactive
decay measurement is the preferred solution. This is why Xilinx offer
radiation hardened devices specifically so people can make reliable
unbiased dice. (It's no coincidence the chips are also called 'dice'.)
Note these parts are not usually offered in BGA packages, but in
leaded ones. The lead protects against radiation.
HTH, Syms.
"Jonathan Bromley" <jonathan.bromley@doulos.com> wrote in message news:<bmh9qo$ohc$1$8302bc10@news.demon.co.uk>...
> "Amstel" <lange360@hotmail.com> wrote in message
> news:56f7756d.0310140824.7d8fe744@posting.google.com...
> > I'm trying to make an electronic dice (3 die). Basically the dice has
> > 3 seven-segment displays and the 3 dice values will run randomly so
> > that we would always get different values combinations. However I
> > tried and was unable to write the program in VHDL .
>
> Do you have any idea how incredibly hard this is?
>
snipped to avoid wrath of Uwe!
Article: 61889rickman wrote: > > "José F. da Rocha" wrote: > > > > Hello. > > > > I’m new at the FPGA/CPLDs world and I’m currently subscribed to > > receive Xilinx email communications. > > > > I would like to know if is there some FPGA/CPLD incorporating some few > > analog functions or analog blocks like instrumentation amplifiers, > > OPerational AMPlifiers/(analog amplification), ADCs > > (Analog-to-Digital-Converter) and DACs? > > > > Thank you very much if you are kindly enough to answer. > > (jose_rocha@yahoo.com) > > There are two devices you might be interested in. One is an MCU with > programmable digital and analog blocks made by Cypress Semi. This is > not really an FPGA since they don't make it easy for you to design your > own digital functions. They used to, but they seem to have gone to a > canned module approach where you have lots of standard functions to > choose from. Did you see info that documented this ? - all I ever saw was 'marketing arm waving' and I was looking for better detail, on just what was SFR based, and what was programmable logic in the true sense. > But I think the digital blocks are easier to work with > than the analog blocks, so you might be able to do what you need. > > The other chip is an FPAA (field programmable analog array). This is an > analog analog (pun intended) to digital FPGAs. I don't know a lot about > them, but a google search should tell you the maker(s) and you can read > up. > > AFAIK, there are no chips that combine programmable digital and analog > functions on one chip. Well, none that do it with any performance.... The FPAAs I've seen have very poor analog numbers, and high prices. Lattice have a power-sequencer device, that has a SPLD, and voltage comparator / timers - but costs a lot more than a 16V8 and LM339's STm have devices with uC + ADC / PWM and 16-32 Macrocell CPLDs > The processing technologies are different enough > that this would be a poor tradeoff and would be neither a good digital > or a good analog chip. Eventually when FPGAs have gotten dense enough > that they are mostly overkill for many apps, they will sacrifice digital > speed and density for the added features of built in analog functions. > But don't hold your breath. And don't expect the analog functions to be > programmable, at least not at first. There are devices that combine uC+FLASH+PGA+24 bit ADCs/ 16 Bit DACS, that are impressive indications of what IS possible, but they come from very experienced ANALOG companies. -jgArticle: 61890
Nitin wrote: > > Hi, > I am a graduate student of Auburn Univeristy doing my research in > SoC testing. I am really an amateur in FPGAs and would like your help. > I have a question, which I think you people can answer. For my > research, I would like to implement a transmission gate into a FPGA. > Can it be done? If yes could you tell me how? No, not in the true analog transmission gate sense, pin to pin. You can get tinylogic SPST / SPDT analog transmission gates and drive those from your FPGA. FPGAs can do Open Drain, so can switch to ground thru 'some ohms', but that ground will be noisy. In some apps, that may be enough. FPGAs also support JTAG boundary scan, for contact integrity testing. -jgArticle: 61891
rickman <spamgoeshere4@yahoo.com> wrote: : Peter, thanks, but we have had this conversation several times. None of : the Virtex or Spartan II devices can be used in this socket because of : the high start up currents. For Spartan II the specifications for the startup current for recent silicon has been revised some days ago. Do they still not meet your requirements? Bye -- Uwe Bonnes bon@elektron.ikp.physik.tu-darmstadt.de Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt --------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------Article: 61892
Martin Euredjian wrote: >One way to look at it might be from the point of view of resources, data >rates, etc. As you hike up in resolution/frame rate (say, 4K x 4K at 60 >frames per second, which is what I'm working on) you need some pretty >massive frame store widths to be able to slow things down to where the >processing is manageable. I was looking into the idea of not having to add >yet another frame buffer for something as "simple" as drawing very basic >graphic primitives (let's just call them cursors used to mark things). If >this could be done in real time, as the actual display data is being output >it would/could make an important difference in the design. > > > Oh, if you just want to superimpose cursors, selection boxes, and things like that onto a live video signal, I think that may be very easy to do without a frame buffer. There are many systems that do this sort of thing, and have been doing it since the 70's. JonArticle: 61893
Brad Eckert wrote: >Hi all, > >Could anyone tell me of universities in the US that are strong in IC >design and/or DSP design? > > You might check with Southern Illinois University at Edwardsville. A guy there is designing a VERY difficult mixed-signal IC for us, and he has done amazing things! He uses his grad students to help design and layout the chips, so he is teaching while he does it. JonArticle: 61894
I have to say I'm pretty disgruntled with Xilinx right now. I've talked to two people there so far, including a lengthy private email exchange with Peter, and nobody seems to want to tell me how to do this. Peter was unable to suggest a single newer 5V part, and was unwilling to tell me what tools can be used to program the older 5V parts. I'm beginning to look at other vendors; perhaps they support their customers a bit better than that. Peter Alfke <peter@xilinx.com> wrote in message news:<3F8C2262.633780A8@xilinx.com>... > Adam, why do you want to use such an old device? Unless you have very > special circumstances, it is best to throw away such old parts and > design with and for newer devices like Virtex and Spartan. > One year in the life of an FPGA equals 15 years in human life. That > means your 5210 really belongs in the old folks' home. > Rest assured that we still sell XC3000, 4000 and 5200 devices for > replacement purposes. But we discourage new designs with them. Newer > devices are so much better and cheaper, and supported by better software. > > Peter Alfke > =============== > Adam wrote: > > > > I have VHDL. I want to create a bitfile for a Xilinx XC5210. > > What tool(s?) do/can I use? > > > > I have ISE webpack 6.1, but it does not seem to support this device.Article: 61895
Patrick Robin wrote: >Hello, > >I have been using Web ISE for over a year to program Xilinx CPLDs >XC9572XL > >Everything was working fine for hundreds of units until my computer >crashed and I had to resinstall ISE. I now get a "Programming failed" >error. Everything else seems to work as far as communicating with the >chip using the parallel cable. Impact detects the chip, I can query >the ID compute the checksum (zero) and erase it fine. > >But I get the "Programming failed error" when I try to program chips. >I tried a number of brand new CPLDs. Is there a way to get more >specific error messages. At this point there are many variables since >I had to resintall Windows XP and ISE. > > You didn't change the computer, did you? Some motherboard parallel port chips do not work well AT ALL with the parallel cable III. I have clearly demonstrated it is the motherboard, as I can swap out the computer, using all the other hardware exactly as it was, and get a perfect programming every time. I think it is MB's with the UMC parallel port chip that have the problem. JonArticle: 61896
In a total time-span of seven hours and 29 minutes we have not been able to come up with a satisfying answer. Shame on us ! Peter Alfke ============================================ Adam wrote: > > I have to say I'm pretty disgruntled with Xilinx right now. I've > talked to two people there so far, including a lengthy private email > exchange with Peter, and nobody seems to want to tell me how to do > this. Peter was unable to suggest a single newer 5V part, and was > unwilling to tell me what tools can be used to program the older 5V > parts. > > I'm beginning to look at other vendors; perhaps they support their > customers a bit better than that. > > Peter Alfke <peter@xilinx.com> wrote in message news:<3F8C2262.633780A8@xilinx.com>... > > Adam, why do you want to use such an old device? Unless you have very > > special circumstances, it is best to throw away such old parts and > > design with and for newer devices like Virtex and Spartan. > > One year in the life of an FPGA equals 15 years in human life. That > > means your 5210 really belongs in the old folks' home. > > Rest assured that we still sell XC3000, 4000 and 5200 devices for > > replacement purposes. But we discourage new designs with them. Newer > > devices are so much better and cheaper, and supported by better software. > > > > Peter Alfke > > =============== > > Adam wrote: > > > > > > I have VHDL. I want to create a bitfile for a Xilinx XC5210. > > > What tool(s?) do/can I use? > > > > > > I have ISE webpack 6.1, but it does not seem to support this device.Article: 61897
Hi All Has anyone got this going fully (using the VB code from the site)? I'm still stuck *wawawa* Pls reply to this post.. Thanks ppl CheersArticle: 61898
Uwe Bonnes wrote: > > rickman <spamgoeshere4@yahoo.com> wrote: > : Peter, thanks, but we have had this conversation several times. None of > : the Virtex or Spartan II devices can be used in this socket because of > : the high start up currents. > > For Spartan II the specifications for the startup current for recent silicon > has been revised some days ago. Do they still not meet your requirements. Interesting. I see the Spartan IIE also had a tweak downwards, and gained on dV/dT caveats. MAX static currents are still not nice. -jgArticle: 61899
How about using linear feedback shift registers instead of counters. I've never actually used one so someone correct me if I'm wrong. They could be driven by a single clock. They each could be initialized with a different seed and could be long enough to run for a long time before repeating. They would still be coupled in the respect that each time the electronic dice is powered up each shift register will output the same pseudo random sequence. Then a roll consists of registering some of the lfsr bits when the dice button is released (the lsfr is still changing while the button is not pressed) Thus, if you could roll the dice at exactly the same times throughout an entire game you would get the same (pseuorandom) sequence of dice values. (But this would be highly unlikely) lange360@hotmail.com (Amstel) wrote in message news:<56f7756d.0310140824.7d8fe744@posting.google.com>... > Hi to all, > > I'm trying to make an electronic dice (3 die). Basically the dice has > 3 seven-segment displays and the 3 dice values will run randomly so > that we would always get different values combinations. However I > tried and was unable to write the program in VHDL . > > I need help urgently .. > Anyone know how to write the program ? > > Thanks a lot :-)
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