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>In the Spartan 2 datasheet I read: >'The IOB includes an optional register in the output path, >the input path, and the 3 state control pin. > >In the diagram this is clear. > >Questions arise: >Can the 3 state register be controlled independently? What do you mean by "independently"? Look at the diagram. Are the clocks shared? Are separate clock enables good enough for your application? >So what are the exact commands for the UCF file to: >Switch off / on the input register. >Select a pos or neg clock for the input and output registers. >What are the defaults? The usual approach is that your code or schematics makes the registers and tri-state buffer, and then you place them in the IOB (if that's where you want them). There are probably convenient library elements that may help you easily get what you want. You probably want to find the library documentation anyway - lots of good ideas in there, especially for the details like you are asking about. -- The suespammers.org mail server is located in California. So are all my other mailboxes. Please do not send unsolicited bulk e-mail or unsolicited commercial e-mail to my suespammers.org address or any of my other addresses. These are my opinions, not necessarily my employer's. I hate spam.Article: 63126
Hi Krysztof,
The connections described in your post are not possible with the Stratix
architecture.
- Subroto Datta
Altera Corp.
"Krzysztof Szczepanski" <kszczepa@poczta.wp.pl> wrote in message
news:bp2sl9$s60$1@korweta.task.gda.pl...
> Hello,
>
> I have a problem with Stratix's PLLs.
> I want to feed input of Enhanced PLL from Fast PLL and Enhanced PLL form
> Enhanced PLL.
>
> CLK input -> Fast PLL -> Enhanced PLL -> PLL output
> -> other logic
> or
> CLK input -> Enhanced PLL -> Enhanced PLL -> PLL output
> -> other logic
>
> Is this two configuration possible to achieve in EP1S25 device?
>
> Quartus 3 signalize errors when I am trying to do that:
> "Error: inclk0 port of PLL
> interface_block_hes:INB|hes_plla:u2|altpll:altpll_component|pll must be
> driven by a non-inverted input pin or, in a fast PLL, the output of a
PLL".
>
> Regards,
> Krzysiek
>
>
>
>
Article: 63127"Gerd B." <nospam@nonononospam.de> wrote in message news:<bp5669$b5u$1@online.de>... > Yes, I've written an EPCS1 Programmer. > Whast Do you want to know ? Thanks for replying! Did you get help from SRUNNER, or some other material? What I need to know is: 1. Erase command, and how do you detect, if chip has been ersaed 2. Write command(s). and how do you detect, if it has been written 3. Read mode command Can I get the source code, if it's written better than SRUNNER? I would appreciate any help here. Thanks againArticle: 63128
Eman wrote:
> How does one start out in fpga development
related thread:
http://groups.google.com/groups?q=ranjith++oe_demo
-- Mike Treseler
Article: 63129On a sunny day (Sat, 15 Nov 2003 18:32:18 -0000) it happened hmurray@suespammers.org (Hal Murray) wrote in <vrcs9idi6l0s42@corp.supernews.com>: > >>So what are the exact commands for the UCF file to: >>Switch off / on the input register. >>Select a pos or neg clock for the input and output registers. >>What are the defaults? > >The usual approach is that your code or schematics makes the registers >and tri-state buffer, and then you place them in the IOB (if that's >where you want them). OK, I see, so it is more a matter of to pick a setup, and then force it to be in the IOB... Somehow I got confused about this.... thought IOB was perhaps a complete block with all those control / clock lines as input... If not then, if you place it in the IOB or not, only has influence on routing and thus speed? >There are probably convenient library elements that may help you >easily get what you want. You probably want to find the library >documentation anyway - lots of good ideas in there, especially >for the details like you are asking about. I will go over all docs again until any confusion is gone. Thank you (all) for the help so far.Article: 63131
Does anybody know if there is a stand alone version of IMPACT? We have several workstations that we would like to use with the DCL5 parallel cable. tks JerArticle: 63132
Impact can run standalone. You will find it under xilinx -> accessories Simon "Jerry" <nospam@nowhere.com> wrote in message news:vrdgcnbf6g3s49@corp.supernews.com... > Does anybody know if there is a stand alone version of IMPACT? We have > several workstations > that we would like to use with the DCL5 parallel cable. > > tks > Jer > > >Article: 63133
"Eman" <vze3tx4k@verizon.net> wrote in message = news:d7dce3cf.0311132339.57ab7886@posting.google.com... > Howdy folks. >=20 > I've got a recent BS in computer sytems engineering, which is a like > EE with some compsci mixed in. I've used CPLDs, and really want to > get a good start in FPGAs so I can build my career in the 'embedded' > direction. >=20 > How does one start out in fpga development given that funds are > limited ? >=20 > thanks=20 >=20 > - moi for boards burched.com digilentinc.com xess.comArticle: 63134
"Naveed" <visualfor@yahoo.com> schrieb im Newsbeitrag news:864a80dc.0311151334.686cbd72@posting.google.com... > "Gerd B." <nospam@nonononospam.de> wrote in message news:<bp5669$b5u$1@online.de>... > > > Yes, I've written an EPCS1 Programmer. > > Whast Do you want to know ? > > Thanks for replying! > Did you get help from SRUNNER, or some other material? > > What I need to know is: > 1. Erase command, and how do you detect, if chip has been ersaed > 2. Write command(s). and how do you detect, if it has been written > 3. Read mode command > > Can I get the source code, if it's written better than SRUNNER? I > would appreciate any help here. Thanks again No Problem. I'll send you the source code an the documentation via eMail. GerdArticle: 63137
Sorry about my laziness. Altera has very nicely written data sheet for EPCS devices on their web page. That's the one I was looking for. I thought SRUNNER is the only support they have for programming EPCS devicesArticle: 63138
Hi Jan, I suggest, that you download the latest version of the Xilinx tool chain if you don't have one yet supporting Spartan-II devices. Then create a very simple design using IOB's ;-) Do the synthesis, P&R and start the FPGA Editor. This is for most of the time a nice tool, in order to see what the technology offers. Zooming into the IOB will clarify most of your questions ... have a nice day Markus "Jan Panteltje" <pNaonStpealmtje@yahoo.com> schrieb im Newsbeitrag news:1068938476.738202@evisp-news-01.ops.asmr-01.energis-idc.net... > On a sunny day (Sat, 15 Nov 2003 18:32:18 -0000) it happened > hmurray@suespammers.org (Hal Murray) wrote in > <vrcs9idi6l0s42@corp.supernews.com>: > > > >>So what are the exact commands for the UCF file to: > >>Switch off / on the input register. > >>Select a pos or neg clock for the input and output registers. > >>What are the defaults? > > > >The usual approach is that your code or schematics makes the registers > >and tri-state buffer, and then you place them in the IOB (if that's > >where you want them). > OK, I see, so it is more a matter of to pick a setup, and then force it > to be in the IOB... > Somehow I got confused about this.... thought IOB was perhaps a complete > block with all those control / clock lines as input... > If not then, if you place it in the IOB or not, only has influence on routing > and thus speed? > > > >There are probably convenient library elements that may help you > >easily get what you want. You probably want to find the library > >documentation anyway - lots of good ideas in there, especially > >for the details like you are asking about. > I will go over all docs again until any confusion is gone. > Thank you (all) for the help so far. >Article: 63139
> Is this going to turn into a project of its own? (Don't I need to > somehow synchronize hw and sw - use hw to initiate read at a slower > speed, then check with SAMPLE instruction via sw, back to hw to > increment addr, etc.?) You can also do it purely using JTAG with a combination of EXTEST and SAMPLE commands. Use EXTEST to set up read controls and address via FPGA pins and then use SAMPLE to read the SRAM data back. Jim Wu jimwu88NOOOSPAM@yahoo.com (remove capital letters) http://www.geocities.com/jimwu88/chipsArticle: 63140
Download web pack and place it on every machine you want to configure from. It can be run from Xilinx accessories. "Jerry" <nospam@nowhere.com> wrote in message news:vrdgcnbf6g3s49@corp.supernews.com... > Does anybody know if there is a stand alone version of IMPACT? We have > several workstations > that we would like to use with the DCL5 parallel cable. > > tks > Jer > > >Article: 63141
>I am using windows 2000, the two PCI card I am about to use is a >Display card and a FPGA based DSP card, they both have workable >driver, what I wonder is if a PCI-Bridge based slot expansion card can >make these two only ocupy one main PCI-bus slot, with out any change >of driver. >Do you know if there are any product card can do this? or any >available design for this? PCI bridges are mature technology. I would expect it to just work. I know next to nothing about MS software. There are, of course, many ways to screwup the software. I think I have seen PCI expansion/extender cards (mostly for testing?) that contained a bridge chip. If you can find one of them it might let you test something close to your desired configuration. Multiport Ethernet cards based on a normal ethernet chips behind a PCI bridge chip are popular. You might be able to borrow one for long enough to verify that your setup at least supports PCI bridges. -- The suespammers.org mail server is located in California. So are all my other mailboxes. Please do not send unsolicited bulk e-mail or unsolicited commercial e-mail to my suespammers.org address or any of my other addresses. These are my opinions, not necessarily my employer's. I hate spam.Article: 63142
Hi, I'm using ise 6.1 to write, synthesise and implement my designs. I'm now trying to use synplify to synthesize without leaving the ise gui. Everything works fine, except that xilinx doesn't seem to pass the .ucf file with my pin assignments to synplify. The resulting .edf file doesn't have any constraints associatted with it, and ise cannot use the .ucf with the .edf. Is it possible to still use the xilinx constraints editor to generate the .ucf, or I absolutely need to open synplify and recreate all my constraints in their scope editor? Rgds, DavidArticle: 63143
[context is bypass caps] >I came to the conclusion that above 100-150MHz you couldn't do a lot >with capacitors anyway. So what do you do then? 1 ns edge rates are reasonably common now. That's well above 150 MHz. -- The suespammers.org mail server is located in California. So are all my other mailboxes. Please do not send unsolicited bulk e-mail or unsolicited commercial e-mail to my suespammers.org address or any of my other addresses. These are my opinions, not necessarily my employer's. I hate spam.Article: 63144
Synplify uses an SDC file to define the pin location, type, timing constrains etc. After synthesis it generate a UCF file for the EDIF file it generated and this can be used with Xilinx tools. You should probably read the documentation for Synplify synthesis flow. Regards, Erez. "Dave" <gretzteam@hotmail.com> wrote in message news:8uGdnTEajNgemSWiRVn-jg@comcast.com... > Hi, > I'm using ise 6.1 to write, synthesise and implement my designs. I'm now > trying to use synplify to synthesize without leaving the ise gui. Everything > works fine, except that xilinx doesn't seem to pass the .ucf file with my > pin assignments to synplify. The resulting .edf file doesn't have any > constraints associatted with it, and ise cannot use the .ucf with the .edf. > Is it possible to still use the xilinx constraints editor to generate the > .ucf, or I absolutely need to open synplify and recreate all my constraints > in their scope editor? > > Rgds, > David > >Article: 63145
Hi all, I'm trying to configur my FPGA with the ARM, and controlled CCLK is used (/WE of ARM). After loading configur data, there still a Startup process needs a clock. Do I need an extra free running clock, and instantiate the start-up module to complete the startup process?Article: 63146
You can also try http://www.fpga4fun.com/ Jean "Eman" <vze3tx4k@verizon.net> wrote in message news:d7dce3cf.0311132339.57ab7886@posting.google.com... > Howdy folks. > > I've got a recent BS in computer sytems engineering, which is a like > EE with some compsci mixed in. I've used CPLDs, and really want to > get a good start in FPGAs so I can build my career in the 'embedded' > direction. > > How does one start out in fpga development given that funds are > limited ? > > thanks > > - moiArticle: 63147
Hello All, I'm wondering, if it's possible to use SRL16s to synchronize external signals to your clock. If I do the standard thing in VHDL, e.g. a couple of assignments in a clocked process, then XST gives me a SRL anyway. Mabe I could just leave it that way, without having to instantiate FDEs manually? Is there any difference w.r.t metastability in using SRLs compared to FDs? Regards Hans DornArticle: 63148
hmurray@suespammers.org (Hal Murray) writes: > [context is bypass caps] > > >I came to the conclusion that above 100-150MHz you couldn't do a lot > >with capacitors anyway. > > So what do you do then? 1 ns edge rates are reasonably common now. > That's well above 150 MHz. > Once you get above the package resonance frequency, you have to rely on the chip vendor doing the right thing (witness the caps placed on the package of P4 and Athlon devices for example). I don't know what X and A are doing about this, given the wildly varying things people want to do with their devices at "silly" clock rates... Cheers, Martin -- martin.j.thompson@trw.com TRW Conekt, Solihull, UK http://www.trw.com/conektArticle: 63149
Lasse Langwadt Christensen wrote: > Anders Hellerup Madsen wrote: >> From what I've gathered from the displays datasheet, it seems the >> display is controlled by two different clock signals, one for vertical >> and one for horizontal lines. Once these clock signals are set >> correctly, it should just be a matter of clocking the pixel data in >> right? >> > kinda, you would normally have something like a clk to clock in the > pixels, a sync for each line and a sync for each frame. Ok, this is like I thought then. >> There seems to be three bits for each color component, red, blue and >> green, and by my calculation this gives 8 different colors. However >> the display is listed as beeing able to show up to 65,000 different >> colors. How exactly is this possible? > > shouldn't that be, ... 8*8*8 = 512 colors I'm sorry, I was unclear at this point. There is three bits per pixel, one for each color component, so it is only eight colors. >> >> I have thought about various dithering schemes, but i think most of >> them implies very dramatical losses in refresh speeds, resolution and >> image quality. What is the normal way of producing colors on a CSTN >> display? > > if you stick to some form of toggling between different intensities of > each color to get apparent intensities in between, shouldn't only the > resulting refresh rate go down? Yep, and apperently this is the way things are expected to be done. I was also considering a kind of dithering where I would use, fx. four adjectant pixels of different colors, to give the illusion that the four pixels together were a mixed shade of another color. But this would halve the resolution and generally look very ugly. But still I am very puzzled about this display. It's a Hitachi SX16H003 display which can display up to 65000 different colors according to this site: http://www.hitachi-displays.com/catalog/skg-225-e.html However according to the datasheet it seems there is only 3 bits per pixels. I am still puzzled. The datasheet can be found here: http://www.hitachi-displays-eu.com/pdf/sx16h003.pdf Thank you for your answer, Regards Anders
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