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In article <bsurcd$1k7c1$1@ID-212430.news.uni-berlin.de>, valentinNOSPAM@abelectron.com says... > > If I understand the question (it is confusing) you want to know *which* > > option to use to enable the register, ACK or WRITE. > ACK or EMPTY, you cannot load a register if it is loaded. Ah, my mistake. > > I'd normally opt to take the faster signal to improve the setup time. > ...but perhaps I don't > > see the issue. > This is an option, thanks. I do not take it into consiteration since setup > time is the longest way the signal travels. As I have both signals (ACK and > EMPTY) anyway, there is no additional gate delay. But in your equations you have: ACK <= EMPTY and WRITE; ...which infers a gate and thus at least a gate delay between ACK and EMPTY. > However, if reg loading > controlling signal turns out to appear at the longest trace this option may > gain sense. But (I may mistake) in modern HW traces play as an important > role as the gates. If a signal is available at a certain part of a design > then why to trace another one? This is an unknown in this problem. If this is a big problem, I'd do it both ways and let synthesis/PAR work out the best solution. This is often done, though I don't think I've done it at this low of a level (usually different implementations of larger blocks). > > So, any other options? Let the software do its thing. ;-) -- KeithArticle: 64376
kkaranasos@in.gr (kpk) wrote in message news:<f2753b28.0312310022.7c2153f6@posting.google.com>... > Can anyone send me a 4-bit binary divider circuit in this email : > kkaranasos@in.gr ? I must make this homework for my university and i > am late. > I have to make this circuit only with NAND gates. > > PLEASE HELP !!!!!!!!! > > Thanks a lot Sorry, I don't mind helping someone with homework if they have made a effort and are stuck. I draw the line when the student submits nothing to show that he/she has even tried to do the work. The purpose of school is not to turn in someone else's work--what do you learn from that? I also have to question the utility of assigning such a problem. I think the professor is out of touch with reality or is a sadist. Also, without considerable research, I cannot design such a counter using only NAND gates--not that I would want to. CharlesArticle: 64377
On 31 Dec 2003 09:24:02 -0800, charles.elias@wpafb.af.mil (Charles M.
Elias) wrote:
>kkaranasos@in.gr (kpk) wrote in message news:<f2753b28.0312310022.7c2153f6@posting.google.com>...
>> Can anyone send me a 4-bit binary divider circuit in this email :
>> kkaranasos@in.gr ? I must make this homework for my university and i
>> am late.
>> I have to make this circuit only with NAND gates.
>>
>> PLEASE HELP !!!!!!!!!
>>
>> Thanks a lot
>
>Sorry,
>
>I don't mind helping someone with homework if they have made a effort
>and are stuck. I draw the line when the student submits nothing to
>show that he/she has even tried to do the work. The purpose of school
>is not to turn in someone else's work--what do you learn from that? I
>also have to question the utility of assigning such a problem. I
>think the professor is out of touch with reality or is a sadist.
>Also, without considerable research, I cannot design such a counter
>using only NAND gates--not that I would want to.
>
>Charles
You can't? Sheeeesh! I'm an analog designer and I can. Ever heard
of master-slave. Takes 9 2-in-nands (one used as an inverter) to make
a D-flop.
...Jim Thompson
--
| James E.Thompson, P.E. | mens |
| Analog Innovations, Inc. | et |
| Analog/Mixed-Signal ASIC's and Discrete Systems | manus |
| Phoenix, Arizona Voice:(480)460-2350 | |
| E-mail Address at Website Fax:(480)460-2142 | Brass Rat |
| http://www.analog-innovations.com | 1962 |
I love to cook with wine. Sometimes I even put it in the food.
Article: 64378
> But in your equations you have:
> ACK <= EMPTY and WRITE;
> ...which infers a gate and thus at least a gate delay between ACK and
> EMPTY.
Yes, but in the example the ACK signal is calculated for another purpose (to
inform data provider that we consume the data). Thus, I have this data delay
in any case, whether control loading by EMPTY or ACK.
>
> > However, if reg loading
> > controlling signal turns out to appear at the longest trace this option
may
> > gain sense. But (I may mistake) in modern HW traces play as an important
> > role as the gates. If a signal is available at a certain part of a
design
> > then why to trace another one?
>
> This is an unknown in this problem. If this is a big problem, I'd do
> it both ways and let synthesis/PAR work out the best solution. This is
> often done, though I don't think I've done it at this low of a level
> (usually different implementations of larger blocks).
May be this is not a big problem, but lots of small problems is always a one
big problem. Bad style means you have small errors/drawbacks throughout your
code. As I'm relatively young to HW I try to develop a good style.
> Let the software do its thing. ;-)
Load the reg with *don't care* when it is empty and with data input on ACK?
Good idea. But synthesier placer, router are still different tools. From the
sithesier point of view, there is no difference in delay controlling the
load. I don't stop wonder how intelligent sometems morern tools can be, but
in general they are stupid. Optimization task is NP-complete, it is always
better to simplify SW can optimize a design replacing its parts as far as
behafviur is the same.
**** Let the software do its thing *****
if ACK then
DATA_REG <= DATA
elsif EMPTY then
DATA <= '-';
-- else hold value
end if;
thanks.
Article: 64379If your homework is too tough, and the time just flies away, thinking hard is not enough, click: comp.arch.fpga. There you find those friendly souls, Austin, Philip, Peter, Ray filling in your knowledge holes, making problems go away. But learning is for you to do, even if it hurts the brain. The one that has to learn is you. There is no substitute for pain. If you want to learn design don't treat homework just as play. Real life is not benign, and you'll have to earn your pay! sooner or later... Peter Alfke (originally posted a few months ago, but bears repeating.) kpk wrote: > Can anyone send me a 4-bit binary divider circuit in this email : > kkaranasos@in.gr ? I must make this homework for my university and i > am late. > I have to make this circuit only with NAND gates. > > PLEASE HELP !!!!!!!!! > > Thanks a lotArticle: 64380
More constructively,
your professor wants you to:
1. realize that you need four cascaded flip-flops,
2. then "re-invent" the master/slave flip-flop,
which you can also find in old TTL databooks (7474).
Maybe an interesting learning experience,
kind of like the boy-scout test of starting a fire without matches...
Have fun !
Peter Alfke
==============================
Peter Alfke wrote:
> If your homework is too tough,
> and the time just flies away,
> thinking hard is not enough,
> click: comp.arch.fpga.
>
> There you find those friendly souls,
> Austin, Philip, Peter, Ray
> filling in your knowledge holes,
> making problems go away.
>
> But learning is for you to do,
> even if it hurts the brain.
> The one that has to learn is you.
> There is no substitute for pain.
>
> If you want to learn design
> don't treat homework just as play.
> Real life is not benign,
> and you'll have to earn your pay!
>
> sooner or later...
>
> Peter Alfke
> (originally posted a few months ago, but bears repeating.)
>
> kpk wrote:
>
> > Can anyone send me a 4-bit binary divider circuit in this email :
> > kkaranasos@in.gr ? I must make this homework for my university and i
> > am late.
> > I have to make this circuit only with NAND gates.
> >
> >
Article: 64381In article <bsv1sd$1ppl2$1@ID-212430.news.uni-berlin.de>, valentinNOSPAM@abelectron.com says... > > But in your equations you have: > > ACK <= EMPTY and WRITE; > > ...which infers a gate and thus at least a gate delay between ACK and > > EMPTY. > Yes, but in the example the ACK signal is calculated for another purpose (to > inform data provider that we consume the data). Thus, I have this data delay > in any case, whether control loading by EMPTY or ACK. Sure, but the slack for this register will be better, allowing easier PAR and perhaps allowing a better solution for something else. There is no point in making things worse. > > > However, if reg loading > > > controlling signal turns out to appear at the longest trace this option > may > > > gain sense. But (I may mistake) in modern HW traces play as an important > > > role as the gates. If a signal is available at a certain part of a > design > > > then why to trace another one? > > > > This is an unknown in this problem. If this is a big problem, I'd do > > it both ways and let synthesis/PAR work out the best solution. This is > > often done, though I don't think I've done it at this low of a level > > (usually different implementations of larger blocks). > May be this is not a big problem, but lots of small problems is always a one > big problem. Bad style means you have small errors/drawbacks throughout your > code. As I'm relatively young to HW I try to develop a good style. Good plan. Be consistent with your style and white-space too. Lots of comments also make for a good style. I always spend a lot of time making things easy to read. It *undoubtedly* will save me time next week figuring what the hell I just did. > > > Let the software do its thing. ;-) > Load the reg with *don't care* when it is empty and with data input on ACK? No. Don't use "don't cares" in synthesizable logic. The "don't care" state isn't realizable and the synthesizer may puke. You should also have a reset clause in your process. > Good idea. But synthesier placer, router are still different tools. From the > sithesier point of view, there is no difference in delay controlling the > load. That depends on your toolset. The toolset I used had delays built into the synthesizer. They weren't always of great use because, as you note, wiring delay is significant and the synthesizer can't know where PAR puts things. OTOH, if your PHB is rich (I had a virtually unlimited budget ;-) there are physical synthesis tools out there that can do a much better job before PAR. > I don't stop wonder how intelligent sometems morern tools can be, but > in general they are stupid. Optimization task is NP-complete, it is always > better to simplify SW can optimize a design replacing its parts as far as > behafviur is the same. The problem is that your synthesizer doesn't have all the information needed to do the job you're asking it to do. You need timing feedback from the PAR tools. > > **** Let the software do its thing ***** > if ACK then > DATA_REG <= DATA > elsif EMPTY then > DATA <= '-'; > -- else hold value > end if; Ack! ;-) You're using ACK as your clock and it's going to produce a level sensitive latch (not good in most technologies). (or did you just leave out the clock?) It's also rather unlikely that your target technology has a '-' level. What I meant by "letting the software do its thing" was implement it both ways and see which does a better job. Let the software tell you where the negative slack is, then fix it. This sort of thing is likely going to be highly implementation dependant. There is unlikely a "best way", other than not to shoot yourself (before you need to ;-). -- KeithArticle: 64382
"Peter Alfke" <Peter.Alfke@xilinx.com> wrote in message news:3FF318F1.DA8D8FF3@xilinx.com... > More constructively, > your professor wants you to: > 1. realize that you need four cascaded flip-flops, > 2. then "re-invent" the master/slave flip-flop, > which you can also find in old TTL databooks (7474). > > Maybe an interesting learning experience, > kind of like the boy-scout test of starting a fire without matches... I got thrown out for that. Potassium Permanganate and glycerine which spontaneously combusts and gets hot enough to light the Magnesium, which is hot enough to light the thermite. I thought it was impressive.Article: 64383
I am trying to use a CPLD as a bus decoder and also have the device
latch 6 bits of data back to the host via a shared data bus. I cannot
get this code to simulate, using Xilinx Webpack. I have asked the
local Xilinx FAE for help but he is not versed in VHDL. This can't be
as difficult as it seems... nobody would be using these devices. I am
getting the following signal for most all of the signals that I have
declared. I have patterned my code after one of the examples included
in WebPack(Xilinx software).
WARNING:Xst:646 - Signal <dat_out<0>> is assigned but never used.
I have included my code... it is not that large.
I would appreciate a kick in the right direction.
Thanks,
David Thurlow
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
-- DESCRIPTION:
-- Decode/Respond to specific addressed commands
-- from the Host, via the BUS.
-- The commands control the FIFOs... READ/WRITE and
-- also send Status Bits back to the Host.
--
--
-- ************************************************************
entity decoder is
Port (ADDR : in std_logic_vector(9 downto 0); -- ADDRESS BUS
D : out std_logic_vector(5 downto 0); -- OUTPUT BITS 6 OF
THEM
N_GWR : in std_logic; -- BUS WRITE PULSE
N_GRD : in std_logic; -- BUS READ PULSE
N_DRV_ENAB: out std_logic; -- ENABLE THE 245 DRIVERS
PCK_READY: in std_logic; -- MESSAGE TO HOST READY
DIR : out std_logic; -- DIRECTION SEL FOR 245 DRIVERS
IN_FIFO_EMPTY : in std_logic; -- FIFO EMPTY SIGNAL
OUT_FIFO_EMPTY : in std_logic; -- FIFO EMPTY SIGNAL
N_RST_IN : out std_logic; -- RESET IN FIFOS
N_RST_OUT : out std_logic; -- RESET OUT FIFOS
N_RST_SYS : in std_logic; -- MASTER RESET
N_X_RD : out std_logic; -- HOST READS THE FIFOS
N_X_WR : out std_logic; -- HOST WRITES TO FIFOS
FIRST : out std_logic; -- SET BIT 9 IN FIFOa... 1st BYTE
LAST : out std_logic; -- SET BIT 9 IN FIFOb... last BYTE
G_BUS_ACTIVE : out std_logic; -- LIGHT LED DURING HOST CMDS
TRI_STATE : out std_logic; -- CONTROL GTS1...address selected
TRI_STATE_IN : in std_logic); -- CONTROL TRI-STATE OUTPUTS
end decoder;
architecture Glonet_Decode of decoder is
-- the READx and WRITEx signals will be set when a proper
-- address and either /GRD or /GWR are active. They will be
-- cleared when /GRD or /GWR are inactive.
signal DAT_OUT : std_logic_vector(5 downto 0); -- STORE STATUS
FLAGS
signal READ0 : std_logic; -- FLAG TO INDICATE VALID ADDRESS AND
/GRD
signal READ1 : std_logic; -- FLAG TO INDICATE VALID ADDRESS AND
/GRD
signal WRITE0 : std_logic; -- FLAG TO INDICATE VALID ADDRESS AND
/GWR
signal WRITE1 : std_logic; -- FLAG TO INDICATE VALID ADDRESS AND
/GWR
signal WRITE2 : std_logic; -- FLAG TO INDICATE VALID ADDRESS AND
/GWR
signal WRITE3 : std_logic; -- FLAG TO INDICATE VALID ADDRESS AND
/GWR
begin
process(N_GRD, N_GWR) -- THESE SIGNALS ARE THE TRIGGER FOR ANY
ACTION
begin
-- IF A READ WAS COMMANDED, CHECK THE ADDRESS.
-- ONLY RESPOND TO SPECIFIC ADDRESSES.
-- SET 'FUNCTION' FLAG AND BUSY FLAG
if N_GRD'event and N_GRD = '0' THEN -- IF HOST READ AND NOT
BUSY
case ADDR is
when "0001110000" => -- IF 1C0h READ FIFOs
READ0 <= '1'; -- SET FUNCTION FLAG FOR USE LATER
when "0001110001" => -- IF 1C1h READ THE STATUS FLAG LATCH
READ1 <= '1'; -- SET FUNCTION FLAG
when others => -- READ PULSE NOT FOR US, IGNORE IT
end case;
END IF;
if N_GWR'event and N_GWR = '0' THEN -- IF HOST WRITE AND NOT BUSY
case ADDR is
when "0001110000" => -- 1C0h WRITE TO FIFOs
WRITE0 <= '1';
when "0001110001" => -- 1C1h WRITE TO FIFOs
WRITE1 <= '1';
when "0001110010" => -- 1C2h WRITE TO FIFOs
WRITE2 <= '1';
when "0001110011" => -- 1C3h RESET FIFOs
WRITE3 <= '1';
when others => -- WRITE PULSE NOT FOR US, IGNORE IT
end case;
END IF;
if N_GRD = '1' and N_GWR = '1' then -- NOTHING HAPPENING ON BUS
N_X_RD <= '1'; -- DISABLE IN_FIFO READS
N_DRV_ENAB <= '1'; -- DISABLE THE '245 DRIVERS
N_X_WR <= '1'; -- DISABLE OUT_FIFO WRITES
TRI_STATE <= '1'; -- TRI-STATE THE LATCHED BITS
FIRST <= '0'; -- RESET FLAG
LAST <= '0'; -- RESET FLAG
G_BUS_ACTIVE <= '1'; -- TURN OFF BUS ACTIVITY FLAG
END IF;
if N_GRD = '1' then -- NO HOST READ PULSE
READ0 <= '0'; -- RESET BOTH FLAGS
READ1 <= '0';
END IF;
if N_GWR = '1' then -- NO HOST WRITE PULSE
WRITE0 <= '0'; -- RESET ALL WRITE FLAGS
WRITE1 <= '0';
WRITE2 <= '0';
WRITE3 <= '0';
END IF;
END PROCESS;
PROCESS(READ0,READ1,WRITE0,WRITE1,WRITE2,WRITE3,IN_FIFO_EMPTY,
OUT_FIFO_EMPTY)
begin
-- **********************************************************************
-- FUNCTION FLAGS!!!!
-- **********************************************************************
if READ0 = '1' then -- LET HOST READ FIFOs
DIR <= '1'; -- SET '245s TO SEND DIRECTION
N_X_RD <= '0'; -- HAVE THE FIFOs SPIT OUT A BYTE
N_DRV_ENAB <= '0'; -- ENABLE THE '245 OUTPUTS
G_BUS_ACTIVE <= '0'; -- TURN ON LED
END IF;
if READ1 = '1' then -- LET HOST READ THE LATCHED STATUS FLAGS
DAT_OUT(0) <= PCK_READY; -- SET DATA TO LATCHED OUTPUTS
DAT_OUT(1) <= IN_FIFO_EMPTY;
DAT_OUT(2) <= OUT_FIFO_EMPTY;
D <= DAT_OUT;
DIR <= '1'; -- SET '245s TO SEND DIRECTION
TRI_STATE <= '0'; -- ENABLE DATA TO OUTPUT LATCHES
N_DRV_ENAB <= '0'; -- ENABLE THE '245 OUTPUTS
G_BUS_ACTIVE <= '0'; -- TURN ON LED
END IF;
if WRITE0 = '1' then -- HOST WRITES TO FIFOs
N_X_WR <= '0'; -- ENABLE FIFOs FOR WRITING
DIR <= '0'; -- SET '245s TO RECEIVE DIRECTION
N_DRV_ENAB <= '0'; -- ENABLE THE '245 OUTPUTS
G_BUS_ACTIVE <= '0'; -- TURN ON LED
END IF;
if WRITE1 = '1' then -- HOST WRITES TO FIFOs W/First FLAG
FIRST <= '1'; -- FLAG TO INDICATE FIRST BYTE OF MESSAGE
N_X_WR <= '0'; -- ENABLE FIFOs FOR WRITING
DIR <= '0'; -- SET '245s TO RECEIVE DIRECTION
N_DRV_ENAB <= '0'; -- ENABLE THE '245 OUTPUTS
G_BUS_ACTIVE <= '0'; -- TURN ON LED
END IF;
if WRITE2 = '1' then -- HOST WRITES TO FIFOs W/Last FLAG
LAST <= '1'; -- FLAG TO INDICATE LAST BYTE OF MESSAGE
N_X_WR <= '0'; -- ENABLE FIFOs FOR WRITING
DIR <= '0'; -- SET '245s TO RECEIVE DIRECTION
N_DRV_ENAB <= '0'; -- ENABLE THE '245 OUTPUTS
G_BUS_ACTIVE <= '0'; -- TURN ON LED
END IF;
if WRITE3 = '1' then -- HOST RESETS FIFOs ?? WE MAY NOT USE
THIS !!
G_BUS_ACTIVE <= '0'; -- TURN ON LED
END IF;
END PROCESS;
process(N_RST_SYS)
begin
-- ******************************************************************
-- RESET: DEFAULT SETTINGS FOR DEVICE
-- ******************************************************************
if N_RST_SYS = '0' then -- SYSTEM RESET
N_RST_IN <= '0'; -- RESET THE INPUT FIFOs
N_RST_OUT <= '0'; -- RESET THE OUTPUT FIFOs
N_DRV_ENAB <= '1'; -- DISABLE THE '245s
N_X_RD <= '1'; -- DISABLE THE FIFOs
N_X_WR <= '1'; --
FIRST <= '0'; -- CLEAR FLAGS
LAST <= '0'; --
G_BUS_ACTIVE <= '1'; -- SHUT OF LED
TRI_STATE <= '1'; -- TRISTATE OUTPUTS TO SHARED BUS
READ0 <= '0'; -- RESET ALL STATUS FLAGS
READ1 <= '0'; --
WRITE0 <= '0'; --
WRITE1 <= '0'; --
WRITE2 <= '0'; --
WRITE3 <= '0'; --
DAT_OUT <= "000000"; -- RESET ALL FLAGS TO ZERO
ELSE
N_RST_IN <= '1'; -- FIFOs
N_RST_OUT <= '1'; --
END IF;
END PROCESS;
end Glonet_Decode;
Article: 64384On Wed, 31 Dec 2003 00:22:06 +0000, kpk wrote: > Can anyone send me a 4-bit binary divider circuit in this email : > kkaranasos@in.gr ? I must make this homework for my university and i > am late. > I have to make this circuit only with NAND gates. > > PLEASE HELP !!!!!!!!! > > Thanks a lot Everbody is assuming that this is a clock divider. But it could be an arithmetic divider. Just thought I'd point that out. MacArticle: 64385
You are assigning DAT_OUT in two different processes. Your latch surely daoes
not
work the way you want. Additionally I would assume a Tri-State drive for "D"
when connected to the data bus.
if N_RST_SYS = '0' then -- SYSTEM RESET
DAT_OUT <= (others => '0');
elsif (YOUR LATCH TRANSPARENT CONDITION)
DAT_OUT(0) <= PCK_READY; -- SET DATA TO LATCHED OUTPUTS
DAT_OUT(1) <= IN_FIFO_EMPTY;
DAT_OUT(2) <= OUT_FIFO_EMPTY; end if;
end if;
D <= DAT_OUT when (YOUR READ CONDITION) else (others => 'Z');
This surely applies to other signals either.
Regards
Thomas
"David T." wrote:
> I am trying to use a CPLD as a bus decoder and also have the device
> latch 6 bits of data back to the host via a shared data bus. I cannot
> get this code to simulate, using Xilinx Webpack. I have asked the
> local Xilinx FAE for help but he is not versed in VHDL. This can't be
> as difficult as it seems... nobody would be using these devices. I am
> getting the following signal for most all of the signals that I have
> declared. I have patterned my code after one of the examples included
> in WebPack(Xilinx software).
>
> WARNING:Xst:646 - Signal <dat_out<0>> is assigned but never used.
>
> I have included my code... it is not that large.
> I would appreciate a kick in the right direction.
>
> Thanks,
> David Thurlow
>
> library IEEE;
> use IEEE.STD_LOGIC_1164.ALL;
> use IEEE.STD_LOGIC_UNSIGNED.ALL;
>
> -- DESCRIPTION:
> -- Decode/Respond to specific addressed commands
> -- from the Host, via the BUS.
> -- The commands control the FIFOs... READ/WRITE and
> -- also send Status Bits back to the Host.
> --
> --
> -- ************************************************************
>
> entity decoder is
> Port (ADDR : in std_logic_vector(9 downto 0); -- ADDRESS BUS
> D : out std_logic_vector(5 downto 0); -- OUTPUT BITS 6 OF
> THEM
> N_GWR : in std_logic; -- BUS WRITE PULSE
> N_GRD : in std_logic; -- BUS READ PULSE
> N_DRV_ENAB: out std_logic; -- ENABLE THE 245 DRIVERS
> PCK_READY: in std_logic; -- MESSAGE TO HOST READY
> DIR : out std_logic; -- DIRECTION SEL FOR 245 DRIVERS
> IN_FIFO_EMPTY : in std_logic; -- FIFO EMPTY SIGNAL
> OUT_FIFO_EMPTY : in std_logic; -- FIFO EMPTY SIGNAL
> N_RST_IN : out std_logic; -- RESET IN FIFOS
> N_RST_OUT : out std_logic; -- RESET OUT FIFOS
> N_RST_SYS : in std_logic; -- MASTER RESET
> N_X_RD : out std_logic; -- HOST READS THE FIFOS
> N_X_WR : out std_logic; -- HOST WRITES TO FIFOS
> FIRST : out std_logic; -- SET BIT 9 IN FIFOa... 1st BYTE
> LAST : out std_logic; -- SET BIT 9 IN FIFOb... last BYTE
> G_BUS_ACTIVE : out std_logic; -- LIGHT LED DURING HOST CMDS
> TRI_STATE : out std_logic; -- CONTROL GTS1...address selected
> TRI_STATE_IN : in std_logic); -- CONTROL TRI-STATE OUTPUTS
> end decoder;
>
> architecture Glonet_Decode of decoder is
> -- the READx and WRITEx signals will be set when a proper
> -- address and either /GRD or /GWR are active. They will be
> -- cleared when /GRD or /GWR are inactive.
> signal DAT_OUT : std_logic_vector(5 downto 0); -- STORE STATUS
> FLAGS
> signal READ0 : std_logic; -- FLAG TO INDICATE VALID ADDRESS AND
> /GRD
> signal READ1 : std_logic; -- FLAG TO INDICATE VALID ADDRESS AND
> /GRD
> signal WRITE0 : std_logic; -- FLAG TO INDICATE VALID ADDRESS AND
> /GWR
> signal WRITE1 : std_logic; -- FLAG TO INDICATE VALID ADDRESS AND
> /GWR
> signal WRITE2 : std_logic; -- FLAG TO INDICATE VALID ADDRESS AND
> /GWR
> signal WRITE3 : std_logic; -- FLAG TO INDICATE VALID ADDRESS AND
> /GWR
> begin
>
> process(N_GRD, N_GWR) -- THESE SIGNALS ARE THE TRIGGER FOR ANY
> ACTION
>
> begin
> -- IF A READ WAS COMMANDED, CHECK THE ADDRESS.
> -- ONLY RESPOND TO SPECIFIC ADDRESSES.
> -- SET 'FUNCTION' FLAG AND BUSY FLAG
> if N_GRD'event and N_GRD = '0' THEN -- IF HOST READ AND NOT
> BUSY
> case ADDR is
> when "0001110000" => -- IF 1C0h READ FIFOs
> READ0 <= '1'; -- SET FUNCTION FLAG FOR USE LATER
> when "0001110001" => -- IF 1C1h READ THE STATUS FLAG LATCH
> READ1 <= '1'; -- SET FUNCTION FLAG
> when others => -- READ PULSE NOT FOR US, IGNORE IT
> end case;
> END IF;
>
> if N_GWR'event and N_GWR = '0' THEN -- IF HOST WRITE AND NOT BUSY
> case ADDR is
> when "0001110000" => -- 1C0h WRITE TO FIFOs
> WRITE0 <= '1';
> when "0001110001" => -- 1C1h WRITE TO FIFOs
> WRITE1 <= '1';
> when "0001110010" => -- 1C2h WRITE TO FIFOs
> WRITE2 <= '1';
> when "0001110011" => -- 1C3h RESET FIFOs
> WRITE3 <= '1';
> when others => -- WRITE PULSE NOT FOR US, IGNORE IT
> end case;
> END IF;
>
> if N_GRD = '1' and N_GWR = '1' then -- NOTHING HAPPENING ON BUS
> N_X_RD <= '1'; -- DISABLE IN_FIFO READS
> N_DRV_ENAB <= '1'; -- DISABLE THE '245 DRIVERS
> N_X_WR <= '1'; -- DISABLE OUT_FIFO WRITES
> TRI_STATE <= '1'; -- TRI-STATE THE LATCHED BITS
> FIRST <= '0'; -- RESET FLAG
> LAST <= '0'; -- RESET FLAG
> G_BUS_ACTIVE <= '1'; -- TURN OFF BUS ACTIVITY FLAG
> END IF;
>
> if N_GRD = '1' then -- NO HOST READ PULSE
> READ0 <= '0'; -- RESET BOTH FLAGS
> READ1 <= '0';
> END IF;
>
> if N_GWR = '1' then -- NO HOST WRITE PULSE
> WRITE0 <= '0'; -- RESET ALL WRITE FLAGS
> WRITE1 <= '0';
> WRITE2 <= '0';
> WRITE3 <= '0';
> END IF;
> END PROCESS;
>
> PROCESS(READ0,READ1,WRITE0,WRITE1,WRITE2,WRITE3,IN_FIFO_EMPTY,
> OUT_FIFO_EMPTY)
> begin
> -- **********************************************************************
> -- FUNCTION FLAGS!!!!
> -- **********************************************************************
> if READ0 = '1' then -- LET HOST READ FIFOs
> DIR <= '1'; -- SET '245s TO SEND DIRECTION
> N_X_RD <= '0'; -- HAVE THE FIFOs SPIT OUT A BYTE
> N_DRV_ENAB <= '0'; -- ENABLE THE '245 OUTPUTS
> G_BUS_ACTIVE <= '0'; -- TURN ON LED
> END IF;
>
> if READ1 = '1' then -- LET HOST READ THE LATCHED STATUS FLAGS
> DAT_OUT(0) <= PCK_READY; -- SET DATA TO LATCHED OUTPUTS
> DAT_OUT(1) <= IN_FIFO_EMPTY;
> DAT_OUT(2) <= OUT_FIFO_EMPTY;
> D <= DAT_OUT;
> DIR <= '1'; -- SET '245s TO SEND DIRECTION
> TRI_STATE <= '0'; -- ENABLE DATA TO OUTPUT LATCHES
> N_DRV_ENAB <= '0'; -- ENABLE THE '245 OUTPUTS
> G_BUS_ACTIVE <= '0'; -- TURN ON LED
> END IF;
>
> if WRITE0 = '1' then -- HOST WRITES TO FIFOs
> N_X_WR <= '0'; -- ENABLE FIFOs FOR WRITING
> DIR <= '0'; -- SET '245s TO RECEIVE DIRECTION
> N_DRV_ENAB <= '0'; -- ENABLE THE '245 OUTPUTS
> G_BUS_ACTIVE <= '0'; -- TURN ON LED
> END IF;
>
> if WRITE1 = '1' then -- HOST WRITES TO FIFOs W/First FLAG
> FIRST <= '1'; -- FLAG TO INDICATE FIRST BYTE OF MESSAGE
> N_X_WR <= '0'; -- ENABLE FIFOs FOR WRITING
> DIR <= '0'; -- SET '245s TO RECEIVE DIRECTION
> N_DRV_ENAB <= '0'; -- ENABLE THE '245 OUTPUTS
> G_BUS_ACTIVE <= '0'; -- TURN ON LED
> END IF;
>
> if WRITE2 = '1' then -- HOST WRITES TO FIFOs W/Last FLAG
> LAST <= '1'; -- FLAG TO INDICATE LAST BYTE OF MESSAGE
> N_X_WR <= '0'; -- ENABLE FIFOs FOR WRITING
> DIR <= '0'; -- SET '245s TO RECEIVE DIRECTION
> N_DRV_ENAB <= '0'; -- ENABLE THE '245 OUTPUTS
> G_BUS_ACTIVE <= '0'; -- TURN ON LED
> END IF;
>
> if WRITE3 = '1' then -- HOST RESETS FIFOs ?? WE MAY NOT USE
> THIS !!
> G_BUS_ACTIVE <= '0'; -- TURN ON LED
> END IF;
>
> END PROCESS;
>
> process(N_RST_SYS)
> begin
> -- ******************************************************************
> -- RESET: DEFAULT SETTINGS FOR DEVICE
> -- ******************************************************************
> if N_RST_SYS = '0' then -- SYSTEM RESET
> N_RST_IN <= '0'; -- RESET THE INPUT FIFOs
> N_RST_OUT <= '0'; -- RESET THE OUTPUT FIFOs
> N_DRV_ENAB <= '1'; -- DISABLE THE '245s
> N_X_RD <= '1'; -- DISABLE THE FIFOs
> N_X_WR <= '1'; --
> FIRST <= '0'; -- CLEAR FLAGS
> LAST <= '0'; --
> G_BUS_ACTIVE <= '1'; -- SHUT OF LED
> TRI_STATE <= '1'; -- TRISTATE OUTPUTS TO SHARED BUS
> READ0 <= '0'; -- RESET ALL STATUS FLAGS
> READ1 <= '0'; --
> WRITE0 <= '0'; --
> WRITE1 <= '0'; --
> WRITE2 <= '0'; --
> WRITE3 <= '0'; --
> DAT_OUT <= "000000"; -- RESET ALL FLAGS TO ZERO
> ELSE
> N_RST_IN <= '1'; -- FIFOs
> N_RST_OUT <= '1'; --
> END IF;
> END PROCESS;
> end Glonet_Decode;
Article: 64386"valentin tihomirov" <valentinNOSPAM@abelectron.com> wrote: :Is there any standard package that can convert TRUE to '1' and FALSE to '0'? :Should I write my function? Why there isn't implicit sythax of that? : There are a number of standard functions for this, in the various libraries. Example: ieee.numeric_extra.to_std_logic() There isn't "implicit syntax" because VHDL is a strongly-typed language. You can only change one type to another explicitly. (Some day, that will save your life :)Article: 64387
Pete Fraser wrote: > "Peter Alfke" <Peter.Alfke@xilinx.com> wrote in message > news:3FF318F1.DA8D8FF3@xilinx.com... > >>More constructively, >>your professor wants you to: >>1. realize that you need four cascaded flip-flops, >>2. then "re-invent" the master/slave flip-flop, >> which you can also find in old TTL databooks (7474). >> >>Maybe an interesting learning experience, >>kind of like the boy-scout test of starting a fire without matches... > > > I got thrown out for that. > > Potassium Permanganate and glycerine which spontaneously > combusts and gets hot enough to light the Magnesium, which > is hot enough to light the thermite. > > I thought it was impressive. > > Hey, how about amonium-tri-iodide? 15 molar amonia and iodine crystals. Make a slurry but dont let it dry out until you want it to explode. (we had a lot of fun painting this stuff in dorm-room locks) -- Luhan Monat, "LuhanKnows" At 'Yahoo' dot 'Com' http://members.cox.net/berniekm "The future is not what it used to be."Article: 64388
Jim Thompson <invalid@invalid.invalid> responded to a deperate
crosspost initiated by kkaranasos@in.gr (kpk) involving:
comp.lang.vhdl,
comp.arch.arithmetic,
comp.arch.fpga,
sci.electronics.design, and
comp.lang.verilog thusly:
>On 31 Dec 2003 09:24:02 -0800, charles.elias@wpafb.af.mil (Charles M.
>Elias) wrote:
>
>>kkaranasos@in.gr (kpk) wrote in message news:<f2753b28.0312310022.7c2153f6@posting.google.com>...
>>> Can anyone send me a 4-bit binary divider circuit in this email :
>>> kkaranasos@in.gr ? I must make this homework for my university and i
>>> am late.
An honest request for the answer to a homework assignment - I don't
think I've ever seen this before!
>>> I have to make this circuit only with NAND gates.
>>>
>>> PLEASE HELP !!!!!!!!!
>>>
>>> Thanks a lot
>>
>>Sorry,
>>
>>I don't mind helping someone with homework if they have made a effort
>>and are stuck. I draw the line when the student submits nothing to
>>show that he/she has even tried to do the work. The purpose of school
>>is not to turn in someone else's work--what do you learn from that?
He learns, at a low level, how to cheat the system. Of course if
there's anywhere that the phrase "you're only cheating yourself"
totally applies, it's in school.
>>I
>>also have to question the utility of assigning such a problem.
Perhaps it reinforces the concept that you can build any logic
device out of a sufficient number of NAND (or NOR) gates?
>>I
>>think the professor is out of touch with reality or is a sadist.
That's surely true of some professors, but how can you tell that
just from what the OP said?
>>Also, without considerable research, I cannot design such a counter
>>using only NAND gates--not that I would want to.
As Jim said, it's not a big deal at all. Would you rather use
LM339's? ;)
>>Charles
>
>You can't? Sheeeesh! I'm an analog designer and I can. Ever heard
>of master-slave. Takes 9 2-in-nands (one used as an inverter) to make
>a D-flop.
I don't know if I'd have the patience to spend three minutes doing
it when I know I could get a schematic that I could easily convert to
all-NAND-all-the-time off a (don't tell the OP) "d-a-t-a s-h-e-e-t" in
less time than that.
> ...Jim Thompson
Bonus question(s): How many 74(xxx)00's (quad nand gate) does it
take to make the 4-bit divider using Jim's solution, and why is "12"
an incorrect answer?
-----
http://mindspring.com/~benbradley
Article: 64389
On Wed, 31 Dec 2003 11:26:14 -0800 in comp.arch.arithmetic, "Pete
Fraser" <pete@rgb.com> wrote:
>
>"Peter Alfke" <Peter.Alfke@xilinx.com> wrote in message
>news:3FF318F1.DA8D8FF3@xilinx.com...
>> More constructively,
>> your professor wants you to:
>> 1. realize that you need four cascaded flip-flops,
>> 2. then "re-invent" the master/slave flip-flop,
>> which you can also find in old TTL databooks (7474).
>>
>> Maybe an interesting learning experience,
>> kind of like the boy-scout test of starting a fire without matches...
>
>I got thrown out for that.
>
>Potassium Permanganate and glycerine which spontaneously
>combusts and gets hot enough to light the Magnesium, which
>is hot enough to light the thermite.
>
>I thought it was impressive.
The establishment doesn't always like creative types -- did you demo
it or just explain it?
--
Thanks. Take care, Brian Inglis Calgary, Alberta, Canada
Brian.Inglis@CSi.com (Brian dot Inglis at SystematicSw dot ab dot ca)
fake address use address above to reply
Article: 64390> I draw the line when the student submits nothing to >show that he/she has even tried to do the work. The purpose of school >is not to turn in someone else's work--what do you learn from that? How to be a manager? I >also have to question the utility of assigning such a problem. I >think the professor is out of touch with reality or is a sadist. >Also, without considerable research, I cannot design such a counter >using only NAND gates--not that I would want to. counter? the OP asked for a multiplier. I could very well imagine asking a sketch of a multiplier with an estimate of the amount of gates involved. An easy solution would be a total 8->256 decoder followed by a 256->5 encoder. Wouter van Ooijen -- ------------------------------------ http://www.voti.nl PICmicro chips, programmers, consultingArticle: 64391
Hi, there: I am a little confused with the partial reconfiguration flow. In the Active module implementation, I found that I must use the *.NGO file. However .NGO file is only available when I use EDIF file as input, and XST cannot produce EDIF file. Does it mean I have no choice but to use something other than XST (e.g. Synplicity) to synthesize my designs? ngdbuild -p xc2v250-fg256-4 -modular module -active iq_gen ../../top1/initial/sig_gen.ngo Best Regards, KelvinArticle: 64392
"Wouter van Ooijen (www.voti.nl)" <wouter@voti.nl> wrote in message news:3ff3c9cd.1463913656@news.xs4all.nl... > > I draw the line when the student submits nothing to > >show that he/she has even tried to do the work. The purpose of school > >is not to turn in someone else's work--what do you learn from that? > > How to be a manager? > > > I also have to question the utility of assigning such a problem. I > >think the professor is out of touch with reality or is a sadist. > >Also, without considerable research, I cannot design such a counter > >using only NAND gates--not that I would want to. > > counter? the OP asked for a multiplier. I could very well imagine > asking a sketch of a multiplier with an estimate of the amount of > gates involved. An easy solution would be a total 8->256 decoder > followed by a 256->5 encoder. > > Wouter van Ooijen > Ummm take a look at the subject line of this thread.. the OP asked for a 4-bit binary divider... 4 R-S flipflops in a chain.. no need for decoders (or maybe I missed something in a later post). -- Tweetldee Tweetldee at att dot net (Just subsitute the appropriate characters in the address) Never take a laxative and a sleeping pill at the same time!!Article: 64393
>Ummm take a look at the subject line of this thread.. the OP asked for a >4-bit binary divider... 4 R-S flipflops in a chain.. no need for decoders >(or maybe I missed something in a later post). Sorry, I mixed multiply and divide :) But are you sure he meant a clock divider? It could also be a binary ALU-style divider. Wouter van Ooijen -- ------------------------------------ http://www.voti.nl PICmicro chips, programmers, consultingArticle: 64394
On 31 Dec 2003 00:22:06 -0800, kkaranasos@in.gr (kpk) wrote: >Can anyone send me a 4-bit binary divider circuit in this email : >kkaranasos@in.gr ? I must make this homework for my university and i >am late. >I have to make this circuit only with NAND gates. > >PLEASE HELP !!!!!!!!! > >Thanks a lot If I were your prof, and I caught you blatantly trying to get others to do your thinking for you, I'd make you design it using nothing but BC547's, resistors and diodes. That way you might l-e-a-r-n something. That is why you are at uni? djArticle: 64395
kkaranasos@in.gr (kpk) wrote in message news:<f2753b28.0312310022.7c2153f6@posting.google.com>... > Can anyone send me a 4-bit binary divider circuit in this email : > kkaranasos@in.gr ? I must make this homework for my university and i > am late. > I have to make this circuit only with NAND gates. Your university probably has a synthesis tool for asics installed. Just write your design in VHDL, remove all gates from the library but the NAND gates and press the synthesis button. Kolja Sulimma Peter: Applause for the poem....Article: 64396
Yachooo !!! I got my linux JTAG programmer working !!! Right now it is very primitive and has only been tested with Virtex devices, but my guess is that it will work with most Xilinx FPGAs. If you try this, please drop me an email with your success/failure story, I will add a summary as I go along. Also if you fix anything, please email me. If anybody (wants to make this a sourceforge project and maintain, please do so (I'll continue to be a contributor) !!! To summarize: - It works under LINUX ! YES ! - Should work with Parallel Cable 3(not tested yet) and 4 - takes a plain binary .bit file - Open/Free Source code ! YES ! Sorry could not figure out how to attach the small file to this poting using google, may be it's better this way anyway. You can download the source code from: http://www.asics.ws/tools/ljp.c.gz Best Regards, rudi ======================================================== ASICS.ws ::: Solutions for your ASIC/FPGA needs ::: ..............::: FPGAs * Full Custom ICs * IP Cores ::: FREE IP Cores -> http://www.asics.ws/ <- FREE EDA ToolsArticle: 64397
I have compiled a design with XSE 6.1i. It produced post-synthesis/fitting VHDL model. ActiveHDL 6.1 simulator fails compilation with *Unknown identifier "X_ROC"* error. X_ROC is the only primitive that cannot be found in the SIMPRIM library provided with ActiveHDL. What is the standard procedure of getting up-to-date libraries: asking library sources from Xilinx or precompiled .lib file from Aldec? Simulator vendors somehow optimize pre-compiled libraries.Article: 64398
In sci.electronics.design, wouter@voti.nl (Wouter van Ooijen (www.voti.nl)) wrote: >>Ummm take a look at the subject line of this thread.. the OP asked for a >>4-bit binary divider... 4 R-S flipflops in a chain.. no need for decoders >>(or maybe I missed something in a later post). > >Sorry, I mixed multiply and divide :) But are you sure he meant a >clock divider? It could also be a binary ALU-style divider. But you can do that with nothing but NAND gates, too. ;) > >Wouter van Ooijen > >-- ------------------------------------ >http://www.voti.nl >PICmicro chips, programmers, consulting ----- http://mindspring.com/~benbradleyArticle: 64399
WOW, your prof let you use NANDs? we had to do this using only relays. Wish I had an easy prof like yours. (:>) Jer "Kolja Sulimma" <news@sulimma.de> wrote in message news:b890a7a.0401010514.18392ca@posting.google.com... > kkaranasos@in.gr (kpk) wrote in message news:<f2753b28.0312310022.7c2153f6@posting.google.com>... > > Can anyone send me a 4-bit binary divider circuit in this email : > > kkaranasos@in.gr ? I must make this homework for my university and i > > am late. > > I have to make this circuit only with NAND gates. > > Your university probably has a synthesis tool for asics installed. > Just write your design in VHDL, remove all gates from the library but > the NAND gates and press the synthesis button. > > Kolja Sulimma > > Peter: > Applause for the poem....
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